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GEN1/STM/Debug/STM_gen.list

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STM_gen.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00003870 08000188 08000188 00010188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000010 080039f8 080039f8 000139f8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08003a08 08003a08 00020010 2**0
CONTENTS
4 .ARM 00000008 08003a08 08003a08 00013a08 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08003a10 08003a10 00020010 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08003a10 08003a10 00013a10 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08003a14 08003a14 00013a14 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000010 20000000 08003a18 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .ccmram 00000000 10000000 10000000 00020010 2**0
CONTENTS
10 .bss 00000128 20000010 20000010 00020010 2**2
ALLOC
11 ._user_heap_stack 00000600 20000138 20000138 00020010 2**0
ALLOC
12 .ARM.attributes 00000030 00000000 00000000 00020010 2**0
CONTENTS, READONLY
13 .comment 00000043 00000000 00000000 00020040 2**0
CONTENTS, READONLY
14 .debug_info 0000b230 00000000 00000000 00020083 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_abbrev 0000195c 00000000 00000000 0002b2b3 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_loclists 00000230 00000000 00000000 0002cc0f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_aranges 00000b68 00000000 00000000 0002ce40 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_rnglists 00000900 00000000 00000000 0002d9a8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_macro 00020a0e 00000000 00000000 0002e2a8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_line 0000c576 00000000 00000000 0004ecb6 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_str 000c65f4 00000000 00000000 0005b22c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
22 .debug_frame 00002ff8 00000000 00000000 00121820 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
23 .debug_line_str 0000004b 00000000 00000000 00124818 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 20000010 .word 0x20000010
80001a4: 00000000 .word 0x00000000
80001a8: 080039e0 .word 0x080039e0
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000014 .word 0x20000014
80001c4: 080039e0 .word 0x080039e0
080001c8 <__aeabi_uldivmod>:
80001c8: b953 cbnz r3, 80001e0 <__aeabi_uldivmod+0x18>
80001ca: b94a cbnz r2, 80001e0 <__aeabi_uldivmod+0x18>
80001cc: 2900 cmp r1, #0
80001ce: bf08 it eq
80001d0: 2800 cmpeq r0, #0
80001d2: bf1c itt ne
80001d4: f04f 31ff movne.w r1, #4294967295
80001d8: f04f 30ff movne.w r0, #4294967295
80001dc: f000 b970 b.w 80004c0 <__aeabi_idiv0>
80001e0: f1ad 0c08 sub.w ip, sp, #8
80001e4: e96d ce04 strd ip, lr, [sp, #-16]!
80001e8: f000 f806 bl 80001f8 <__udivmoddi4>
80001ec: f8dd e004 ldr.w lr, [sp, #4]
80001f0: e9dd 2302 ldrd r2, r3, [sp, #8]
80001f4: b004 add sp, #16
80001f6: 4770 bx lr
080001f8 <__udivmoddi4>:
80001f8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80001fc: 9e08 ldr r6, [sp, #32]
80001fe: 460d mov r5, r1
8000200: 4604 mov r4, r0
8000202: 460f mov r7, r1
8000204: 2b00 cmp r3, #0
8000206: d14a bne.n 800029e <__udivmoddi4+0xa6>
8000208: 428a cmp r2, r1
800020a: 4694 mov ip, r2
800020c: d965 bls.n 80002da <__udivmoddi4+0xe2>
800020e: fab2 f382 clz r3, r2
8000212: b143 cbz r3, 8000226 <__udivmoddi4+0x2e>
8000214: fa02 fc03 lsl.w ip, r2, r3
8000218: f1c3 0220 rsb r2, r3, #32
800021c: 409f lsls r7, r3
800021e: fa20 f202 lsr.w r2, r0, r2
8000222: 4317 orrs r7, r2
8000224: 409c lsls r4, r3
8000226: ea4f 4e1c mov.w lr, ip, lsr #16
800022a: fa1f f58c uxth.w r5, ip
800022e: fbb7 f1fe udiv r1, r7, lr
8000232: 0c22 lsrs r2, r4, #16
8000234: fb0e 7711 mls r7, lr, r1, r7
8000238: ea42 4207 orr.w r2, r2, r7, lsl #16
800023c: fb01 f005 mul.w r0, r1, r5
8000240: 4290 cmp r0, r2
8000242: d90a bls.n 800025a <__udivmoddi4+0x62>
8000244: eb1c 0202 adds.w r2, ip, r2
8000248: f101 37ff add.w r7, r1, #4294967295
800024c: f080 811c bcs.w 8000488 <__udivmoddi4+0x290>
8000250: 4290 cmp r0, r2
8000252: f240 8119 bls.w 8000488 <__udivmoddi4+0x290>
8000256: 3902 subs r1, #2
8000258: 4462 add r2, ip
800025a: 1a12 subs r2, r2, r0
800025c: b2a4 uxth r4, r4
800025e: fbb2 f0fe udiv r0, r2, lr
8000262: fb0e 2210 mls r2, lr, r0, r2
8000266: ea44 4402 orr.w r4, r4, r2, lsl #16
800026a: fb00 f505 mul.w r5, r0, r5
800026e: 42a5 cmp r5, r4
8000270: d90a bls.n 8000288 <__udivmoddi4+0x90>
8000272: eb1c 0404 adds.w r4, ip, r4
8000276: f100 32ff add.w r2, r0, #4294967295
800027a: f080 8107 bcs.w 800048c <__udivmoddi4+0x294>
800027e: 42a5 cmp r5, r4
8000280: f240 8104 bls.w 800048c <__udivmoddi4+0x294>
8000284: 4464 add r4, ip
8000286: 3802 subs r0, #2
8000288: ea40 4001 orr.w r0, r0, r1, lsl #16
800028c: 1b64 subs r4, r4, r5
800028e: 2100 movs r1, #0
8000290: b11e cbz r6, 800029a <__udivmoddi4+0xa2>
8000292: 40dc lsrs r4, r3
8000294: 2300 movs r3, #0
8000296: e9c6 4300 strd r4, r3, [r6]
800029a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800029e: 428b cmp r3, r1
80002a0: d908 bls.n 80002b4 <__udivmoddi4+0xbc>
80002a2: 2e00 cmp r6, #0
80002a4: f000 80ed beq.w 8000482 <__udivmoddi4+0x28a>
80002a8: 2100 movs r1, #0
80002aa: e9c6 0500 strd r0, r5, [r6]
80002ae: 4608 mov r0, r1
80002b0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002b4: fab3 f183 clz r1, r3
80002b8: 2900 cmp r1, #0
80002ba: d149 bne.n 8000350 <__udivmoddi4+0x158>
80002bc: 42ab cmp r3, r5
80002be: d302 bcc.n 80002c6 <__udivmoddi4+0xce>
80002c0: 4282 cmp r2, r0
80002c2: f200 80f8 bhi.w 80004b6 <__udivmoddi4+0x2be>
80002c6: 1a84 subs r4, r0, r2
80002c8: eb65 0203 sbc.w r2, r5, r3
80002cc: 2001 movs r0, #1
80002ce: 4617 mov r7, r2
80002d0: 2e00 cmp r6, #0
80002d2: d0e2 beq.n 800029a <__udivmoddi4+0xa2>
80002d4: e9c6 4700 strd r4, r7, [r6]
80002d8: e7df b.n 800029a <__udivmoddi4+0xa2>
80002da: b902 cbnz r2, 80002de <__udivmoddi4+0xe6>
80002dc: deff udf #255 ; 0xff
80002de: fab2 f382 clz r3, r2
80002e2: 2b00 cmp r3, #0
80002e4: f040 8090 bne.w 8000408 <__udivmoddi4+0x210>
80002e8: 1a8a subs r2, r1, r2
80002ea: ea4f 471c mov.w r7, ip, lsr #16
80002ee: fa1f fe8c uxth.w lr, ip
80002f2: 2101 movs r1, #1
80002f4: fbb2 f5f7 udiv r5, r2, r7
80002f8: fb07 2015 mls r0, r7, r5, r2
80002fc: 0c22 lsrs r2, r4, #16
80002fe: ea42 4200 orr.w r2, r2, r0, lsl #16
8000302: fb0e f005 mul.w r0, lr, r5
8000306: 4290 cmp r0, r2
8000308: d908 bls.n 800031c <__udivmoddi4+0x124>
800030a: eb1c 0202 adds.w r2, ip, r2
800030e: f105 38ff add.w r8, r5, #4294967295
8000312: d202 bcs.n 800031a <__udivmoddi4+0x122>
8000314: 4290 cmp r0, r2
8000316: f200 80cb bhi.w 80004b0 <__udivmoddi4+0x2b8>
800031a: 4645 mov r5, r8
800031c: 1a12 subs r2, r2, r0
800031e: b2a4 uxth r4, r4
8000320: fbb2 f0f7 udiv r0, r2, r7
8000324: fb07 2210 mls r2, r7, r0, r2
8000328: ea44 4402 orr.w r4, r4, r2, lsl #16
800032c: fb0e fe00 mul.w lr, lr, r0
8000330: 45a6 cmp lr, r4
8000332: d908 bls.n 8000346 <__udivmoddi4+0x14e>
8000334: eb1c 0404 adds.w r4, ip, r4
8000338: f100 32ff add.w r2, r0, #4294967295
800033c: d202 bcs.n 8000344 <__udivmoddi4+0x14c>
800033e: 45a6 cmp lr, r4
8000340: f200 80bb bhi.w 80004ba <__udivmoddi4+0x2c2>
8000344: 4610 mov r0, r2
8000346: eba4 040e sub.w r4, r4, lr
800034a: ea40 4005 orr.w r0, r0, r5, lsl #16
800034e: e79f b.n 8000290 <__udivmoddi4+0x98>
8000350: f1c1 0720 rsb r7, r1, #32
8000354: 408b lsls r3, r1
8000356: fa22 fc07 lsr.w ip, r2, r7
800035a: ea4c 0c03 orr.w ip, ip, r3
800035e: fa05 f401 lsl.w r4, r5, r1
8000362: fa20 f307 lsr.w r3, r0, r7
8000366: 40fd lsrs r5, r7
8000368: ea4f 491c mov.w r9, ip, lsr #16
800036c: 4323 orrs r3, r4
800036e: fbb5 f8f9 udiv r8, r5, r9
8000372: fa1f fe8c uxth.w lr, ip
8000376: fb09 5518 mls r5, r9, r8, r5
800037a: 0c1c lsrs r4, r3, #16
800037c: ea44 4405 orr.w r4, r4, r5, lsl #16
8000380: fb08 f50e mul.w r5, r8, lr
8000384: 42a5 cmp r5, r4
8000386: fa02 f201 lsl.w r2, r2, r1
800038a: fa00 f001 lsl.w r0, r0, r1
800038e: d90b bls.n 80003a8 <__udivmoddi4+0x1b0>
8000390: eb1c 0404 adds.w r4, ip, r4
8000394: f108 3aff add.w sl, r8, #4294967295
8000398: f080 8088 bcs.w 80004ac <__udivmoddi4+0x2b4>
800039c: 42a5 cmp r5, r4
800039e: f240 8085 bls.w 80004ac <__udivmoddi4+0x2b4>
80003a2: f1a8 0802 sub.w r8, r8, #2
80003a6: 4464 add r4, ip
80003a8: 1b64 subs r4, r4, r5
80003aa: b29d uxth r5, r3
80003ac: fbb4 f3f9 udiv r3, r4, r9
80003b0: fb09 4413 mls r4, r9, r3, r4
80003b4: ea45 4404 orr.w r4, r5, r4, lsl #16
80003b8: fb03 fe0e mul.w lr, r3, lr
80003bc: 45a6 cmp lr, r4
80003be: d908 bls.n 80003d2 <__udivmoddi4+0x1da>
80003c0: eb1c 0404 adds.w r4, ip, r4
80003c4: f103 35ff add.w r5, r3, #4294967295
80003c8: d26c bcs.n 80004a4 <__udivmoddi4+0x2ac>
80003ca: 45a6 cmp lr, r4
80003cc: d96a bls.n 80004a4 <__udivmoddi4+0x2ac>
80003ce: 3b02 subs r3, #2
80003d0: 4464 add r4, ip
80003d2: ea43 4308 orr.w r3, r3, r8, lsl #16
80003d6: fba3 9502 umull r9, r5, r3, r2
80003da: eba4 040e sub.w r4, r4, lr
80003de: 42ac cmp r4, r5
80003e0: 46c8 mov r8, r9
80003e2: 46ae mov lr, r5
80003e4: d356 bcc.n 8000494 <__udivmoddi4+0x29c>
80003e6: d053 beq.n 8000490 <__udivmoddi4+0x298>
80003e8: b156 cbz r6, 8000400 <__udivmoddi4+0x208>
80003ea: ebb0 0208 subs.w r2, r0, r8
80003ee: eb64 040e sbc.w r4, r4, lr
80003f2: fa04 f707 lsl.w r7, r4, r7
80003f6: 40ca lsrs r2, r1
80003f8: 40cc lsrs r4, r1
80003fa: 4317 orrs r7, r2
80003fc: e9c6 7400 strd r7, r4, [r6]
8000400: 4618 mov r0, r3
8000402: 2100 movs r1, #0
8000404: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000408: f1c3 0120 rsb r1, r3, #32
800040c: fa02 fc03 lsl.w ip, r2, r3
8000410: fa20 f201 lsr.w r2, r0, r1
8000414: fa25 f101 lsr.w r1, r5, r1
8000418: 409d lsls r5, r3
800041a: 432a orrs r2, r5
800041c: ea4f 471c mov.w r7, ip, lsr #16
8000420: fa1f fe8c uxth.w lr, ip
8000424: fbb1 f0f7 udiv r0, r1, r7
8000428: fb07 1510 mls r5, r7, r0, r1
800042c: 0c11 lsrs r1, r2, #16
800042e: ea41 4105 orr.w r1, r1, r5, lsl #16
8000432: fb00 f50e mul.w r5, r0, lr
8000436: 428d cmp r5, r1
8000438: fa04 f403 lsl.w r4, r4, r3
800043c: d908 bls.n 8000450 <__udivmoddi4+0x258>
800043e: eb1c 0101 adds.w r1, ip, r1
8000442: f100 38ff add.w r8, r0, #4294967295
8000446: d22f bcs.n 80004a8 <__udivmoddi4+0x2b0>
8000448: 428d cmp r5, r1
800044a: d92d bls.n 80004a8 <__udivmoddi4+0x2b0>
800044c: 3802 subs r0, #2
800044e: 4461 add r1, ip
8000450: 1b49 subs r1, r1, r5
8000452: b292 uxth r2, r2
8000454: fbb1 f5f7 udiv r5, r1, r7
8000458: fb07 1115 mls r1, r7, r5, r1
800045c: ea42 4201 orr.w r2, r2, r1, lsl #16
8000460: fb05 f10e mul.w r1, r5, lr
8000464: 4291 cmp r1, r2
8000466: d908 bls.n 800047a <__udivmoddi4+0x282>
8000468: eb1c 0202 adds.w r2, ip, r2
800046c: f105 38ff add.w r8, r5, #4294967295
8000470: d216 bcs.n 80004a0 <__udivmoddi4+0x2a8>
8000472: 4291 cmp r1, r2
8000474: d914 bls.n 80004a0 <__udivmoddi4+0x2a8>
8000476: 3d02 subs r5, #2
8000478: 4462 add r2, ip
800047a: 1a52 subs r2, r2, r1
800047c: ea45 4100 orr.w r1, r5, r0, lsl #16
8000480: e738 b.n 80002f4 <__udivmoddi4+0xfc>
8000482: 4631 mov r1, r6
8000484: 4630 mov r0, r6
8000486: e708 b.n 800029a <__udivmoddi4+0xa2>
8000488: 4639 mov r1, r7
800048a: e6e6 b.n 800025a <__udivmoddi4+0x62>
800048c: 4610 mov r0, r2
800048e: e6fb b.n 8000288 <__udivmoddi4+0x90>
8000490: 4548 cmp r0, r9
8000492: d2a9 bcs.n 80003e8 <__udivmoddi4+0x1f0>
8000494: ebb9 0802 subs.w r8, r9, r2
8000498: eb65 0e0c sbc.w lr, r5, ip
800049c: 3b01 subs r3, #1
800049e: e7a3 b.n 80003e8 <__udivmoddi4+0x1f0>
80004a0: 4645 mov r5, r8
80004a2: e7ea b.n 800047a <__udivmoddi4+0x282>
80004a4: 462b mov r3, r5
80004a6: e794 b.n 80003d2 <__udivmoddi4+0x1da>
80004a8: 4640 mov r0, r8
80004aa: e7d1 b.n 8000450 <__udivmoddi4+0x258>
80004ac: 46d0 mov r8, sl
80004ae: e77b b.n 80003a8 <__udivmoddi4+0x1b0>
80004b0: 3d02 subs r5, #2
80004b2: 4462 add r2, ip
80004b4: e732 b.n 800031c <__udivmoddi4+0x124>
80004b6: 4608 mov r0, r1
80004b8: e70a b.n 80002d0 <__udivmoddi4+0xd8>
80004ba: 4464 add r4, ip
80004bc: 3802 subs r0, #2
80004be: e742 b.n 8000346 <__udivmoddi4+0x14e>
080004c0 <__aeabi_idiv0>:
80004c0: 4770 bx lr
80004c2: bf00 nop
080004c4 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80004c4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
80004c8: b08b sub sp, #44 ; 0x2c
GPIO_InitTypeDef GPIO_InitStruct = {0};
80004ca: 2400 movs r4, #0
80004cc: 9405 str r4, [sp, #20]
80004ce: 9406 str r4, [sp, #24]
80004d0: 9407 str r4, [sp, #28]
80004d2: 9408 str r4, [sp, #32]
80004d4: 9409 str r4, [sp, #36] ; 0x24
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOH_CLK_ENABLE();
80004d6: 9401 str r4, [sp, #4]
80004d8: 4b2b ldr r3, [pc, #172] ; (8000588 <MX_GPIO_Init+0xc4>)
80004da: 6b1a ldr r2, [r3, #48] ; 0x30
80004dc: f042 0280 orr.w r2, r2, #128 ; 0x80
80004e0: 631a str r2, [r3, #48] ; 0x30
80004e2: 6b1a ldr r2, [r3, #48] ; 0x30
80004e4: f002 0280 and.w r2, r2, #128 ; 0x80
80004e8: 9201 str r2, [sp, #4]
80004ea: 9a01 ldr r2, [sp, #4]
__HAL_RCC_GPIOC_CLK_ENABLE();
80004ec: 9402 str r4, [sp, #8]
80004ee: 6b1a ldr r2, [r3, #48] ; 0x30
80004f0: f042 0204 orr.w r2, r2, #4
80004f4: 631a str r2, [r3, #48] ; 0x30
80004f6: 6b1a ldr r2, [r3, #48] ; 0x30
80004f8: f002 0204 and.w r2, r2, #4
80004fc: 9202 str r2, [sp, #8]
80004fe: 9a02 ldr r2, [sp, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000500: 9403 str r4, [sp, #12]
8000502: 6b1a ldr r2, [r3, #48] ; 0x30
8000504: f042 0201 orr.w r2, r2, #1
8000508: 631a str r2, [r3, #48] ; 0x30
800050a: 6b1a ldr r2, [r3, #48] ; 0x30
800050c: f002 0201 and.w r2, r2, #1
8000510: 9203 str r2, [sp, #12]
8000512: 9a03 ldr r2, [sp, #12]
__HAL_RCC_GPIOE_CLK_ENABLE();
8000514: 9404 str r4, [sp, #16]
8000516: 6b1a ldr r2, [r3, #48] ; 0x30
8000518: f042 0210 orr.w r2, r2, #16
800051c: 631a str r2, [r3, #48] ; 0x30
800051e: 6b1b ldr r3, [r3, #48] ; 0x30
8000520: f003 0310 and.w r3, r3, #16
8000524: 9304 str r3, [sp, #16]
8000526: 9b04 ldr r3, [sp, #16]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1, GPIO_PIN_RESET);
8000528: f8df 9064 ldr.w r9, [pc, #100] ; 8000590 <MX_GPIO_Init+0xcc>
800052c: 4622 mov r2, r4
800052e: 2102 movs r1, #2
8000530: 4648 mov r0, r9
8000532: f000 ffc3 bl 80014bc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1|GPIO_PIN_3, GPIO_PIN_RESET);
8000536: 4d15 ldr r5, [pc, #84] ; (800058c <MX_GPIO_Init+0xc8>)
8000538: 4622 mov r2, r4
800053a: 210a movs r1, #10
800053c: 4628 mov r0, r5
800053e: f000 ffbd bl 80014bc <HAL_GPIO_WritePin>
/*Configure GPIO pin : PC1 */
GPIO_InitStruct.Pin = GPIO_PIN_1;
8000542: f04f 0802 mov.w r8, #2
8000546: f8cd 8014 str.w r8, [sp, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800054a: 2601 movs r6, #1
800054c: 9606 str r6, [sp, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800054e: 9407 str r4, [sp, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000550: 2703 movs r7, #3
8000552: 9708 str r7, [sp, #32]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000554: a905 add r1, sp, #20
8000556: 4648 mov r0, r9
8000558: f000 fe14 bl 8001184 <HAL_GPIO_Init>
/*Configure GPIO pin : PA1 */
GPIO_InitStruct.Pin = GPIO_PIN_1;
800055c: f8cd 8014 str.w r8, [sp, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000560: 9606 str r6, [sp, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000562: 9407 str r4, [sp, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000564: 9408 str r4, [sp, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000566: a905 add r1, sp, #20
8000568: 4628 mov r0, r5
800056a: f000 fe0b bl 8001184 <HAL_GPIO_Init>
/*Configure GPIO pin : PA3 */
GPIO_InitStruct.Pin = GPIO_PIN_3;
800056e: 2308 movs r3, #8
8000570: 9305 str r3, [sp, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000572: 9606 str r6, [sp, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000574: 9407 str r4, [sp, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000576: 9708 str r7, [sp, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000578: a905 add r1, sp, #20
800057a: 4628 mov r0, r5
800057c: f000 fe02 bl 8001184 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000580: b00b add sp, #44 ; 0x2c
8000582: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
8000586: bf00 nop
8000588: 40023800 .word 0x40023800
800058c: 40020000 .word 0x40020000
8000590: 40020800 .word 0x40020800
08000594 <SetInvert>:
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
}
void SetInvert(Mode *mode_ptr) {
8000594: b508 push {r3, lr}
if (mode_ptr->invert == 1) {
8000596: 7943 ldrb r3, [r0, #5]
8000598: 2b01 cmp r3, #1
800059a: d005 beq.n 80005a8 <SetInvert+0x14>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, GPIO_PIN_SET); // Инвертированный L12 (1 - да, 0 - нет)
} else {
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, GPIO_PIN_RESET);
800059c: 2200 movs r2, #0
800059e: 2108 movs r1, #8
80005a0: 4804 ldr r0, [pc, #16] ; (80005b4 <SetInvert+0x20>)
80005a2: f000 ff8b bl 80014bc <HAL_GPIO_WritePin>
}
}
80005a6: bd08 pop {r3, pc}
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, GPIO_PIN_SET); // Инвертированный L12 (1 - да, 0 - нет)
80005a8: 2201 movs r2, #1
80005aa: 2108 movs r1, #8
80005ac: 4801 ldr r0, [pc, #4] ; (80005b4 <SetInvert+0x20>)
80005ae: f000 ff85 bl 80014bc <HAL_GPIO_WritePin>
80005b2: e7f8 b.n 80005a6 <SetInvert+0x12>
80005b4: 40020000 .word 0x40020000
080005b8 <FillMode>:
// HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET);
// }
//}
void FillMode(Mode *mode_ptr, uint8_t *recData, int start) {
mode_ptr->time_mode = recData[start];
80005b8: 5c8b ldrb r3, [r1, r2]
80005ba: 7003 strb r3, [r0, #0]
mode_ptr->f = recData[start + 3];
80005bc: 4411 add r1, r2
80005be: 78cb ldrb r3, [r1, #3]
80005c0: 7103 strb r3, [r0, #4]
mode_ptr->pwm_value = (uint16_t)(recData[start + 1] << 8) | recData[start + 2];
80005c2: 784a ldrb r2, [r1, #1]
80005c4: 788b ldrb r3, [r1, #2]
80005c6: ea43 2302 orr.w r3, r3, r2, lsl #8
80005ca: 8043 strh r3, [r0, #2]
mode_ptr->invert = recData[start + 4];
80005cc: 790b ldrb r3, [r1, #4]
80005ce: 7143 strb r3, [r0, #5]
//mode_ptr->in_r1 = recData[start + 5];
}
80005d0: 4770 bx lr
080005d2 <Error_Handler>:
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80005d2: b672 cpsid i
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80005d4: e7fe b.n 80005d4 <Error_Handler+0x2>
...
080005d8 <MX_TIM2_Init>:
{
80005d8: b500 push {lr}
80005da: b08f sub sp, #60 ; 0x3c
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80005dc: 2300 movs r3, #0
80005de: 930a str r3, [sp, #40] ; 0x28
80005e0: 930b str r3, [sp, #44] ; 0x2c
80005e2: 930c str r3, [sp, #48] ; 0x30
80005e4: 930d str r3, [sp, #52] ; 0x34
TIM_MasterConfigTypeDef sMasterConfig = {0};
80005e6: 9308 str r3, [sp, #32]
80005e8: 9309 str r3, [sp, #36] ; 0x24
TIM_OC_InitTypeDef sConfigOC = {0};
80005ea: 9301 str r3, [sp, #4]
80005ec: 9302 str r3, [sp, #8]
80005ee: 9303 str r3, [sp, #12]
80005f0: 9304 str r3, [sp, #16]
80005f2: 9305 str r3, [sp, #20]
80005f4: 9306 str r3, [sp, #24]
80005f6: 9307 str r3, [sp, #28]
htim2.Instance = TIM2;
80005f8: 481f ldr r0, [pc, #124] ; (8000678 <MX_TIM2_Init+0xa0>)
80005fa: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
80005fe: 6002 str r2, [r0, #0]
htim2.Init.Prescaler = 0;
8000600: 6043 str r3, [r0, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8000602: 6083 str r3, [r0, #8]
htim2.Init.Period = 65535;
8000604: f64f 72ff movw r2, #65535 ; 0xffff
8000608: 60c2 str r2, [r0, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800060a: 6103 str r3, [r0, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800060c: 6183 str r3, [r0, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
800060e: f001 ffff bl 8002610 <HAL_TIM_Base_Init>
8000612: bb30 cbnz r0, 8000662 <MX_TIM2_Init+0x8a>
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000614: f44f 5380 mov.w r3, #4096 ; 0x1000
8000618: 930a str r3, [sp, #40] ; 0x28
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
800061a: a90a add r1, sp, #40 ; 0x28
800061c: 4816 ldr r0, [pc, #88] ; (8000678 <MX_TIM2_Init+0xa0>)
800061e: f002 fcc7 bl 8002fb0 <HAL_TIM_ConfigClockSource>
8000622: bb00 cbnz r0, 8000666 <MX_TIM2_Init+0x8e>
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
8000624: 4814 ldr r0, [pc, #80] ; (8000678 <MX_TIM2_Init+0xa0>)
8000626: f002 f90c bl 8002842 <HAL_TIM_PWM_Init>
800062a: b9f0 cbnz r0, 800066a <MX_TIM2_Init+0x92>
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800062c: 2300 movs r3, #0
800062e: 9308 str r3, [sp, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000630: 9309 str r3, [sp, #36] ; 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000632: a908 add r1, sp, #32
8000634: 4810 ldr r0, [pc, #64] ; (8000678 <MX_TIM2_Init+0xa0>)
8000636: f003 f8c5 bl 80037c4 <HAL_TIMEx_MasterConfigSynchronization>
800063a: b9c0 cbnz r0, 800066e <MX_TIM2_Init+0x96>
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800063c: 2360 movs r3, #96 ; 0x60
800063e: 9301 str r3, [sp, #4]
sConfigOC.Pulse = 10000;
8000640: f242 7310 movw r3, #10000 ; 0x2710
8000644: 9302 str r3, [sp, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000646: 2200 movs r2, #0
8000648: 9203 str r2, [sp, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
800064a: 9205 str r2, [sp, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800064c: a901 add r1, sp, #4
800064e: 480a ldr r0, [pc, #40] ; (8000678 <MX_TIM2_Init+0xa0>)
8000650: f002 fbec bl 8002e2c <HAL_TIM_PWM_ConfigChannel>
8000654: b968 cbnz r0, 8000672 <MX_TIM2_Init+0x9a>
HAL_TIM_MspPostInit(&htim2);
8000656: 4808 ldr r0, [pc, #32] ; (8000678 <MX_TIM2_Init+0xa0>)
8000658: f000 fae4 bl 8000c24 <HAL_TIM_MspPostInit>
}
800065c: b00f add sp, #60 ; 0x3c
800065e: f85d fb04 ldr.w pc, [sp], #4
Error_Handler();
8000662: f7ff ffb6 bl 80005d2 <Error_Handler>
Error_Handler();
8000666: f7ff ffb4 bl 80005d2 <Error_Handler>
Error_Handler();
800066a: f7ff ffb2 bl 80005d2 <Error_Handler>
Error_Handler();
800066e: f7ff ffb0 bl 80005d2 <Error_Handler>
Error_Handler();
8000672: f7ff ffae bl 80005d2 <Error_Handler>
8000676: bf00 nop
8000678: 200000cc .word 0x200000cc
0800067c <MX_TIM1_Init>:
{
800067c: b510 push {r4, lr}
800067e: b096 sub sp, #88 ; 0x58
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000680: 2400 movs r4, #0
8000682: 9412 str r4, [sp, #72] ; 0x48
8000684: 9413 str r4, [sp, #76] ; 0x4c
8000686: 9414 str r4, [sp, #80] ; 0x50
8000688: 9415 str r4, [sp, #84] ; 0x54
TIM_MasterConfigTypeDef sMasterConfig = {0};
800068a: 9410 str r4, [sp, #64] ; 0x40
800068c: 9411 str r4, [sp, #68] ; 0x44
TIM_OC_InitTypeDef sConfigOC = {0};
800068e: 9409 str r4, [sp, #36] ; 0x24
8000690: 940a str r4, [sp, #40] ; 0x28
8000692: 940b str r4, [sp, #44] ; 0x2c
8000694: 940c str r4, [sp, #48] ; 0x30
8000696: 940d str r4, [sp, #52] ; 0x34
8000698: 940e str r4, [sp, #56] ; 0x38
800069a: 940f str r4, [sp, #60] ; 0x3c
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
800069c: 2220 movs r2, #32
800069e: 4621 mov r1, r4
80006a0: a801 add r0, sp, #4
80006a2: f003 f971 bl 8003988 <memset>
htim1.Instance = TIM1;
80006a6: 482a ldr r0, [pc, #168] ; (8000750 <MX_TIM1_Init+0xd4>)
80006a8: 4b2a ldr r3, [pc, #168] ; (8000754 <MX_TIM1_Init+0xd8>)
80006aa: 6003 str r3, [r0, #0]
htim1.Init.Prescaler = 23999;
80006ac: f645 53bf movw r3, #23999 ; 0x5dbf
80006b0: 6043 str r3, [r0, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
80006b2: 6084 str r4, [r0, #8]
htim1.Init.Period = 999;
80006b4: f240 33e7 movw r3, #999 ; 0x3e7
80006b8: 60c3 str r3, [r0, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80006ba: 6104 str r4, [r0, #16]
htim1.Init.RepetitionCounter = 0;
80006bc: 6144 str r4, [r0, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80006be: 6184 str r4, [r0, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
80006c0: f001 ffa6 bl 8002610 <HAL_TIM_Base_Init>
80006c4: 2800 cmp r0, #0
80006c6: d136 bne.n 8000736 <MX_TIM1_Init+0xba>
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80006c8: f44f 5380 mov.w r3, #4096 ; 0x1000
80006cc: 9312 str r3, [sp, #72] ; 0x48
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
80006ce: a912 add r1, sp, #72 ; 0x48
80006d0: 481f ldr r0, [pc, #124] ; (8000750 <MX_TIM1_Init+0xd4>)
80006d2: f002 fc6d bl 8002fb0 <HAL_TIM_ConfigClockSource>
80006d6: 2800 cmp r0, #0
80006d8: d12f bne.n 800073a <MX_TIM1_Init+0xbe>
if (HAL_TIM_OC_Init(&htim1) != HAL_OK)
80006da: 481d ldr r0, [pc, #116] ; (8000750 <MX_TIM1_Init+0xd4>)
80006dc: f002 f858 bl 8002790 <HAL_TIM_OC_Init>
80006e0: 2800 cmp r0, #0
80006e2: d12c bne.n 800073e <MX_TIM1_Init+0xc2>
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80006e4: 2300 movs r3, #0
80006e6: 9310 str r3, [sp, #64] ; 0x40
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80006e8: 9311 str r3, [sp, #68] ; 0x44
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
80006ea: a910 add r1, sp, #64 ; 0x40
80006ec: 4818 ldr r0, [pc, #96] ; (8000750 <MX_TIM1_Init+0xd4>)
80006ee: f003 f869 bl 80037c4 <HAL_TIMEx_MasterConfigSynchronization>
80006f2: bb30 cbnz r0, 8000742 <MX_TIM1_Init+0xc6>
sConfigOC.OCMode = TIM_OCMODE_TIMING;
80006f4: 2200 movs r2, #0
80006f6: 9209 str r2, [sp, #36] ; 0x24
sConfigOC.Pulse = 0;
80006f8: 920a str r2, [sp, #40] ; 0x28
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80006fa: 920b str r2, [sp, #44] ; 0x2c
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
80006fc: 920c str r2, [sp, #48] ; 0x30
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80006fe: 920d str r2, [sp, #52] ; 0x34
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
8000700: 920e str r2, [sp, #56] ; 0x38
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
8000702: 920f str r2, [sp, #60] ; 0x3c
if (HAL_TIM_OC_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000704: a909 add r1, sp, #36 ; 0x24
8000706: 4812 ldr r0, [pc, #72] ; (8000750 <MX_TIM1_Init+0xd4>)
8000708: f002 fb34 bl 8002d74 <HAL_TIM_OC_ConfigChannel>
800070c: b9d8 cbnz r0, 8000746 <MX_TIM1_Init+0xca>
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
800070e: 2300 movs r3, #0
8000710: 9301 str r3, [sp, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8000712: 9302 str r3, [sp, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8000714: 9303 str r3, [sp, #12]
sBreakDeadTimeConfig.DeadTime = 0;
8000716: 9304 str r3, [sp, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
8000718: 9305 str r3, [sp, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
800071a: f44f 5200 mov.w r2, #8192 ; 0x2000
800071e: 9206 str r2, [sp, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
8000720: 9308 str r3, [sp, #32]
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
8000722: a901 add r1, sp, #4
8000724: 480a ldr r0, [pc, #40] ; (8000750 <MX_TIM1_Init+0xd4>)
8000726: f003 f8c9 bl 80038bc <HAL_TIMEx_ConfigBreakDeadTime>
800072a: b970 cbnz r0, 800074a <MX_TIM1_Init+0xce>
HAL_TIM_MspPostInit(&htim1);
800072c: 4808 ldr r0, [pc, #32] ; (8000750 <MX_TIM1_Init+0xd4>)
800072e: f000 fa79 bl 8000c24 <HAL_TIM_MspPostInit>
}
8000732: b016 add sp, #88 ; 0x58
8000734: bd10 pop {r4, pc}
Error_Handler();
8000736: f7ff ff4c bl 80005d2 <Error_Handler>
Error_Handler();
800073a: f7ff ff4a bl 80005d2 <Error_Handler>
Error_Handler();
800073e: f7ff ff48 bl 80005d2 <Error_Handler>
Error_Handler();
8000742: f7ff ff46 bl 80005d2 <Error_Handler>
Error_Handler();
8000746: f7ff ff44 bl 80005d2 <Error_Handler>
Error_Handler();
800074a: f7ff ff42 bl 80005d2 <Error_Handler>
800074e: bf00 nop
8000750: 20000084 .word 0x20000084
8000754: 40010000 .word 0x40010000
08000758 <MX_SPI1_Init>:
{
8000758: b508 push {r3, lr}
hspi1.Instance = SPI1;
800075a: 480a ldr r0, [pc, #40] ; (8000784 <MX_SPI1_Init+0x2c>)
800075c: 4b0a ldr r3, [pc, #40] ; (8000788 <MX_SPI1_Init+0x30>)
800075e: 6003 str r3, [r0, #0]
hspi1.Init.Mode = SPI_MODE_SLAVE;
8000760: 2300 movs r3, #0
8000762: 6043 str r3, [r0, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
8000764: 6083 str r3, [r0, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
8000766: 60c3 str r3, [r0, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
8000768: 6103 str r3, [r0, #16]
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
800076a: 6143 str r3, [r0, #20]
hspi1.Init.NSS = SPI_NSS_HARD_INPUT;
800076c: 6183 str r3, [r0, #24]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
800076e: 6203 str r3, [r0, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
8000770: 6243 str r3, [r0, #36] ; 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000772: 6283 str r3, [r0, #40] ; 0x28
hspi1.Init.CRCPolynomial = 10;
8000774: 230a movs r3, #10
8000776: 62c3 str r3, [r0, #44] ; 0x2c
if (HAL_SPI_Init(&hspi1) != HAL_OK)
8000778: f001 fade bl 8001d38 <HAL_SPI_Init>
800077c: b900 cbnz r0, 8000780 <MX_SPI1_Init+0x28>
}
800077e: bd08 pop {r3, pc}
Error_Handler();
8000780: f7ff ff27 bl 80005d2 <Error_Handler>
8000784: 2000002c .word 0x2000002c
8000788: 40013000 .word 0x40013000
0800078c <SystemClock_Config>:
{
800078c: b500 push {lr}
800078e: b095 sub sp, #84 ; 0x54
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000790: 2230 movs r2, #48 ; 0x30
8000792: 2100 movs r1, #0
8000794: a808 add r0, sp, #32
8000796: f003 f8f7 bl 8003988 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800079a: 2300 movs r3, #0
800079c: 9303 str r3, [sp, #12]
800079e: 9304 str r3, [sp, #16]
80007a0: 9305 str r3, [sp, #20]
80007a2: 9306 str r3, [sp, #24]
80007a4: 9307 str r3, [sp, #28]
__HAL_RCC_PWR_CLK_ENABLE();
80007a6: 9301 str r3, [sp, #4]
80007a8: 4a18 ldr r2, [pc, #96] ; (800080c <SystemClock_Config+0x80>)
80007aa: 6c11 ldr r1, [r2, #64] ; 0x40
80007ac: f041 5180 orr.w r1, r1, #268435456 ; 0x10000000
80007b0: 6411 str r1, [r2, #64] ; 0x40
80007b2: 6c12 ldr r2, [r2, #64] ; 0x40
80007b4: f002 5280 and.w r2, r2, #268435456 ; 0x10000000
80007b8: 9201 str r2, [sp, #4]
80007ba: 9a01 ldr r2, [sp, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
80007bc: 9302 str r3, [sp, #8]
80007be: 4a14 ldr r2, [pc, #80] ; (8000810 <SystemClock_Config+0x84>)
80007c0: 6811 ldr r1, [r2, #0]
80007c2: f441 4180 orr.w r1, r1, #16384 ; 0x4000
80007c6: 6011 str r1, [r2, #0]
80007c8: 6812 ldr r2, [r2, #0]
80007ca: f402 4280 and.w r2, r2, #16384 ; 0x4000
80007ce: 9202 str r2, [sp, #8]
80007d0: 9a02 ldr r2, [sp, #8]
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80007d2: 2201 movs r2, #1
80007d4: 9208 str r2, [sp, #32]
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
80007d6: f44f 22a0 mov.w r2, #327680 ; 0x50000
80007da: 9209 str r2, [sp, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
80007dc: 930e str r3, [sp, #56] ; 0x38
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80007de: a808 add r0, sp, #32
80007e0: f000 fe86 bl 80014f0 <HAL_RCC_OscConfig>
80007e4: b970 cbnz r0, 8000804 <SystemClock_Config+0x78>
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80007e6: 230f movs r3, #15
80007e8: 9303 str r3, [sp, #12]
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
80007ea: 2301 movs r3, #1
80007ec: 9304 str r3, [sp, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80007ee: 2100 movs r1, #0
80007f0: 9105 str r1, [sp, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80007f2: 9106 str r1, [sp, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80007f4: 9107 str r1, [sp, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80007f6: a803 add r0, sp, #12
80007f8: f001 f8f2 bl 80019e0 <HAL_RCC_ClockConfig>
80007fc: b920 cbnz r0, 8000808 <SystemClock_Config+0x7c>
}
80007fe: b015 add sp, #84 ; 0x54
8000800: f85d fb04 ldr.w pc, [sp], #4
Error_Handler();
8000804: f7ff fee5 bl 80005d2 <Error_Handler>
Error_Handler();
8000808: f7ff fee3 bl 80005d2 <Error_Handler>
800080c: 40023800 .word 0x40023800
8000810: 40007000 .word 0x40007000
08000814 <main>:
{
8000814: b530 push {r4, r5, lr}
8000816: b085 sub sp, #20
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
8000818: 4a65 ldr r2, [pc, #404] ; (80009b0 <main+0x19c>)
800081a: 6b13 ldr r3, [r2, #48] ; 0x30
800081c: f043 0301 orr.w r3, r3, #1
8000820: 6313 str r3, [r2, #48] ; 0x30
GPIOA->MODER &= ~(3U << (0 * 2));
8000822: 4b64 ldr r3, [pc, #400] ; (80009b4 <main+0x1a0>)
8000824: 6819 ldr r1, [r3, #0]
8000826: f021 0103 bic.w r1, r1, #3
800082a: 6019 str r1, [r3, #0]
GPIOA->MODER &= ~(3U << (3 * 2));
800082c: 6819 ldr r1, [r3, #0]
800082e: f021 01c0 bic.w r1, r1, #192 ; 0xc0
8000832: 6019 str r1, [r3, #0]
GPIOA->MODER |= (1U << (0 * 2));
8000834: 6819 ldr r1, [r3, #0]
8000836: f041 0101 orr.w r1, r1, #1
800083a: 6019 str r1, [r3, #0]
GPIOA->MODER |= (1U << (3 * 2));
800083c: 6819 ldr r1, [r3, #0]
800083e: f041 0140 orr.w r1, r1, #64 ; 0x40
8000842: 6019 str r1, [r3, #0]
GPIOA->BSRR = GPIO_BSRR_BR0;
8000844: f44f 3180 mov.w r1, #65536 ; 0x10000
8000848: 6199 str r1, [r3, #24]
GPIOA->BSRR = GPIO_BSRR_BR3;
800084a: f44f 2100 mov.w r1, #524288 ; 0x80000
800084e: 6199 str r1, [r3, #24]
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
8000850: 6b13 ldr r3, [r2, #48] ; 0x30
8000852: f043 0304 orr.w r3, r3, #4
8000856: 6313 str r3, [r2, #48] ; 0x30
GPIOC->MODER &= ~(3U << (1 * 2)); // Сброс режима входа
8000858: 4c57 ldr r4, [pc, #348] ; (80009b8 <main+0x1a4>)
800085a: 6823 ldr r3, [r4, #0]
800085c: f023 030c bic.w r3, r3, #12
8000860: 6023 str r3, [r4, #0]
GPIOC->MODER |= (1U << (1 * 2)); // Установка режима выхода
8000862: 6823 ldr r3, [r4, #0]
8000864: f043 0304 orr.w r3, r3, #4
8000868: 6023 str r3, [r4, #0]
GPIOC->BSRR = GPIO_BSRR_BR1;
800086a: f44f 3300 mov.w r3, #131072 ; 0x20000
800086e: 61a3 str r3, [r4, #24]
HAL_Init();
8000870: f000 fb04 bl 8000e7c <HAL_Init>
SystemClock_Config();
8000874: f7ff ff8a bl 800078c <SystemClock_Config>
MX_GPIO_Init();
8000878: f7ff fe24 bl 80004c4 <MX_GPIO_Init>
MX_TIM2_Init();
800087c: f7ff feac bl 80005d8 <MX_TIM2_Init>
MX_TIM1_Init();
8000880: f7ff fefc bl 800067c <MX_TIM1_Init>
MX_SPI1_Init();
8000884: f7ff ff68 bl 8000758 <MX_SPI1_Init>
uint8_t recData[10] = {0};
8000888: 2300 movs r3, #0
800088a: 9301 str r3, [sp, #4]
800088c: 9302 str r3, [sp, #8]
800088e: f8ad 300c strh.w r3, [sp, #12]
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1, GPIO_PIN_SET);
8000892: 2201 movs r2, #1
8000894: 2102 movs r1, #2
8000896: 4620 mov r0, r4
8000898: f000 fe10 bl 80014bc <HAL_GPIO_WritePin>
if (HAL_SPI_Receive(&hspi1, recData, 10, HAL_MAX_DELAY) == HAL_OK) {
800089c: f04f 33ff mov.w r3, #4294967295
80008a0: 220a movs r2, #10
80008a2: a901 add r1, sp, #4
80008a4: 4845 ldr r0, [pc, #276] ; (80009bc <main+0x1a8>)
80008a6: f001 fad0 bl 8001e4a <HAL_SPI_Receive>
80008aa: b168 cbz r0, 80008c8 <main+0xb4>
FillMode(&modes[0], recData, 0);
80008ac: 4c44 ldr r4, [pc, #272] ; (80009c0 <main+0x1ac>)
80008ae: 2200 movs r2, #0
80008b0: a901 add r1, sp, #4
80008b2: 4620 mov r0, r4
80008b4: f7ff fe80 bl 80005b8 <FillMode>
FillMode(&modes[1], recData, 5);
80008b8: 2205 movs r2, #5
80008ba: a901 add r1, sp, #4
80008bc: f104 000c add.w r0, r4, #12
80008c0: f7ff fe7a bl 80005b8 <FillMode>
for (int i = 0; i < CHANNELS; i++) {
80008c4: 2000 movs r0, #0
80008c6: e018 b.n 80008fa <main+0xe6>
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1, GPIO_PIN_RESET);
80008c8: 2200 movs r2, #0
80008ca: 2102 movs r1, #2
80008cc: 4620 mov r0, r4
80008ce: f000 fdf5 bl 80014bc <HAL_GPIO_WritePin>
80008d2: e7eb b.n 80008ac <main+0x98>
int F_tmp = F_CPU / modes[i].coef;
80008d4: eb00 0140 add.w r1, r0, r0, lsl #1
80008d8: 4a39 ldr r2, [pc, #228] ; (80009c0 <main+0x1ac>)
80008da: eb02 0281 add.w r2, r2, r1, lsl #2
80008de: 7994 ldrb r4, [r2, #6]
80008e0: 4938 ldr r1, [pc, #224] ; (80009c4 <main+0x1b0>)
80008e2: fb91 f1f4 sdiv r1, r1, r4
modes[i].freq_pwm_new = (F_tmp * T) / 1000;
80008e6: fb01 f303 mul.w r3, r1, r3
80008ea: 4937 ldr r1, [pc, #220] ; (80009c8 <main+0x1b4>)
80008ec: fb81 4103 smull r4, r1, r1, r3
80008f0: 17db asrs r3, r3, #31
80008f2: ebc3 13a1 rsb r3, r3, r1, asr #6
80008f6: 8113 strh r3, [r2, #8]
for (int i = 0; i < CHANNELS; i++) {
80008f8: 3001 adds r0, #1
80008fa: 2801 cmp r0, #1
80008fc: dc28 bgt.n 8000950 <main+0x13c>
uint8_t T = 1000 / modes[i].f; // период следования импульсов
80008fe: eb00 0240 add.w r2, r0, r0, lsl #1
8000902: 4b2f ldr r3, [pc, #188] ; (80009c0 <main+0x1ac>)
8000904: eb03 0382 add.w r3, r3, r2, lsl #2
8000908: 791a ldrb r2, [r3, #4]
800090a: f44f 737a mov.w r3, #1000 ; 0x3e8
800090e: fb93 f3f2 sdiv r3, r3, r2
uint32_t freq_T_check = (F_CPU * T) / 100;
8000912: b2db uxtb r3, r3
8000914: 4a2d ldr r2, [pc, #180] ; (80009cc <main+0x1b8>)
8000916: fb03 f202 mul.w r2, r3, r2
if (freq_T_check >= MAX_PWM_FREQ) {
800091a: f64f 71fe movw r1, #65534 ; 0xfffe
800091e: 428a cmp r2, r1
8000920: d9ea bls.n 80008f8 <main+0xe4>
modes[i].coef = freq_T_check / MAX_PWM_FREQ; // предделитель
8000922: 492b ldr r1, [pc, #172] ; (80009d0 <main+0x1bc>)
8000924: fba1 4102 umull r4, r1, r1, r2
8000928: 0bcc lsrs r4, r1, #15
800092a: f3c1 31c7 ubfx r1, r1, #15, #8
800092e: eb00 0e40 add.w lr, r0, r0, lsl #1
8000932: 4d23 ldr r5, [pc, #140] ; (80009c0 <main+0x1ac>)
8000934: eb05 0c8e add.w ip, r5, lr, lsl #2
8000938: f88c 1006 strb.w r1, [ip, #6]
if (freq_T_check % MAX_PWM_FREQ != 0) {
800093c: ebc4 4404 rsb r4, r4, r4, lsl #16
8000940: 42a2 cmp r2, r4
8000942: d0c7 beq.n 80008d4 <main+0xc0>
modes[i].coef++;
8000944: 240c movs r4, #12
8000946: fb04 5200 mla r2, r4, r0, r5
800094a: 3101 adds r1, #1
800094c: 7191 strb r1, [r2, #6]
800094e: e7c1 b.n 80008d4 <main+0xc0>
modes[0].pwm_value_res = (modes[0].pwm_value * modes[0].freq_pwm_new) / MAX_PWM_FREQ; // пересчет скважности для 1 канала
8000950: 4a1b ldr r2, [pc, #108] ; (80009c0 <main+0x1ac>)
8000952: 8853 ldrh r3, [r2, #2]
8000954: 8911 ldrh r1, [r2, #8]
8000956: fb01 f303 mul.w r3, r1, r3
800095a: 491d ldr r1, [pc, #116] ; (80009d0 <main+0x1bc>)
800095c: fb81 4003 smull r4, r0, r1, r3
8000960: 4418 add r0, r3
8000962: 17db asrs r3, r3, #31
8000964: ebc3 33e0 rsb r3, r3, r0, asr #15
8000968: 8153 strh r3, [r2, #10]
modes[1].pwm_value_res = (modes[1].pwm_value * modes[1].freq_pwm_new) / MAX_PWM_FREQ; // пересчет скважности для 2 канала
800096a: 89d3 ldrh r3, [r2, #14]
800096c: 8a90 ldrh r0, [r2, #20]
800096e: fb00 f303 mul.w r3, r0, r3
8000972: fb81 0103 smull r0, r1, r1, r3
8000976: 4419 add r1, r3
8000978: 17db asrs r3, r3, #31
800097a: ebc3 33e1 rsb r3, r3, r1, asr #15
800097e: 82d3 strh r3, [r2, #22]
HAL_TIM_Base_Start_IT(&htim1);
8000980: 4814 ldr r0, [pc, #80] ; (80009d4 <main+0x1c0>)
8000982: f001 fe95 bl 80026b0 <HAL_TIM_Base_Start_IT>
8000986: e005 b.n 8000994 <main+0x180>
if (channel == 1 && settings_set == 0) {
8000988: 4a13 ldr r2, [pc, #76] ; (80009d8 <main+0x1c4>)
800098a: 6812 ldr r2, [r2, #0]
800098c: b932 cbnz r2, 800099c <main+0x188>
settings_set = 1; // канал 1 настроен
800098e: 4b12 ldr r3, [pc, #72] ; (80009d8 <main+0x1c4>)
8000990: 2201 movs r2, #1
8000992: 601a str r2, [r3, #0]
if (channel == 1 && settings_set == 0) {
8000994: 4b11 ldr r3, [pc, #68] ; (80009dc <main+0x1c8>)
8000996: 681b ldr r3, [r3, #0]
8000998: 2b01 cmp r3, #1
800099a: d0f5 beq.n 8000988 <main+0x174>
} else if (channel == 2 && settings_set == 0) {
800099c: 2b02 cmp r3, #2
800099e: d1f9 bne.n 8000994 <main+0x180>
80009a0: 4b0d ldr r3, [pc, #52] ; (80009d8 <main+0x1c4>)
80009a2: 681b ldr r3, [r3, #0]
80009a4: 2b00 cmp r3, #0
80009a6: d1f5 bne.n 8000994 <main+0x180>
settings_set = 1; // канал 2 настроен
80009a8: 4b0b ldr r3, [pc, #44] ; (80009d8 <main+0x1c4>)
80009aa: 2201 movs r2, #1
80009ac: 601a str r2, [r3, #0]
80009ae: e7f1 b.n 8000994 <main+0x180>
80009b0: 40023800 .word 0x40023800
80009b4: 40020000 .word 0x40020000
80009b8: 40020800 .word 0x40020800
80009bc: 2000002c .word 0x2000002c
80009c0: 20000118 .word 0x20000118
80009c4: 016e3600 .word 0x016e3600
80009c8: 10624dd3 .word 0x10624dd3
80009cc: 0003a980 .word 0x0003a980
80009d0: 80008001 .word 0x80008001
80009d4: 20000084 .word 0x20000084
80009d8: 20000130 .word 0x20000130
80009dc: 20000000 .word 0x20000000
080009e0 <PWMInit>:
void PWMInit(uint8_t prescaler, uint16_t period, uint16_t pwm_value) {
80009e0: b570 push {r4, r5, r6, lr}
80009e2: b08e sub sp, #56 ; 0x38
80009e4: 4604 mov r4, r0
80009e6: 4616 mov r6, r2
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80009e8: 2300 movs r3, #0
80009ea: 930a str r3, [sp, #40] ; 0x28
80009ec: 930b str r3, [sp, #44] ; 0x2c
80009ee: 930c str r3, [sp, #48] ; 0x30
80009f0: 930d str r3, [sp, #52] ; 0x34
TIM_MasterConfigTypeDef sMasterConfig = {0};
80009f2: 9308 str r3, [sp, #32]
80009f4: 9309 str r3, [sp, #36] ; 0x24
TIM_OC_InitTypeDef sConfigOC = {0};
80009f6: 9301 str r3, [sp, #4]
80009f8: 9302 str r3, [sp, #8]
80009fa: 9303 str r3, [sp, #12]
80009fc: 9304 str r3, [sp, #16]
80009fe: 9305 str r3, [sp, #20]
8000a00: 9306 str r3, [sp, #24]
8000a02: 9307 str r3, [sp, #28]
htim2.Instance = TIM2;
8000a04: 481f ldr r0, [pc, #124] ; (8000a84 <PWMInit+0xa4>)
8000a06: f04f 4580 mov.w r5, #1073741824 ; 0x40000000
8000a0a: 6005 str r5, [r0, #0]
htim2.Init.Prescaler = prescaler;
8000a0c: 6044 str r4, [r0, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8000a0e: 6083 str r3, [r0, #8]
htim2.Init.Period = period;
8000a10: 60c1 str r1, [r0, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000a12: 6103 str r3, [r0, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000a14: 6183 str r3, [r0, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
8000a16: f001 fdfb bl 8002610 <HAL_TIM_Base_Init>
8000a1a: bb40 cbnz r0, 8000a6e <PWMInit+0x8e>
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000a1c: f44f 5380 mov.w r3, #4096 ; 0x1000
8000a20: 930a str r3, [sp, #40] ; 0x28
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
8000a22: a90a add r1, sp, #40 ; 0x28
8000a24: 4817 ldr r0, [pc, #92] ; (8000a84 <PWMInit+0xa4>)
8000a26: f002 fac3 bl 8002fb0 <HAL_TIM_ConfigClockSource>
8000a2a: bb10 cbnz r0, 8000a72 <PWMInit+0x92>
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
8000a2c: 4815 ldr r0, [pc, #84] ; (8000a84 <PWMInit+0xa4>)
8000a2e: f001 ff08 bl 8002842 <HAL_TIM_PWM_Init>
8000a32: bb00 cbnz r0, 8000a76 <PWMInit+0x96>
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000a34: 2300 movs r3, #0
8000a36: 9308 str r3, [sp, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000a38: 9309 str r3, [sp, #36] ; 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000a3a: a908 add r1, sp, #32
8000a3c: 4811 ldr r0, [pc, #68] ; (8000a84 <PWMInit+0xa4>)
8000a3e: f002 fec1 bl 80037c4 <HAL_TIMEx_MasterConfigSynchronization>
8000a42: b9d0 cbnz r0, 8000a7a <PWMInit+0x9a>
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000a44: 2360 movs r3, #96 ; 0x60
8000a46: 9301 str r3, [sp, #4]
sConfigOC.Pulse = pwm_value;
8000a48: 9602 str r6, [sp, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000a4a: 2200 movs r2, #0
8000a4c: 9203 str r2, [sp, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000a4e: 9205 str r2, [sp, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000a50: a901 add r1, sp, #4
8000a52: 480c ldr r0, [pc, #48] ; (8000a84 <PWMInit+0xa4>)
8000a54: f002 f9ea bl 8002e2c <HAL_TIM_PWM_ConfigChannel>
8000a58: b988 cbnz r0, 8000a7e <PWMInit+0x9e>
HAL_TIM_MspPostInit(&htim2);
8000a5a: 4c0a ldr r4, [pc, #40] ; (8000a84 <PWMInit+0xa4>)
8000a5c: 4620 mov r0, r4
8000a5e: f000 f8e1 bl 8000c24 <HAL_TIM_MspPostInit>
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
8000a62: 2100 movs r1, #0
8000a64: 4620 mov r0, r4
8000a66: f001 ff45 bl 80028f4 <HAL_TIM_PWM_Start>
}
8000a6a: b00e add sp, #56 ; 0x38
8000a6c: bd70 pop {r4, r5, r6, pc}
Error_Handler();
8000a6e: f7ff fdb0 bl 80005d2 <Error_Handler>
Error_Handler();
8000a72: f7ff fdae bl 80005d2 <Error_Handler>
Error_Handler();
8000a76: f7ff fdac bl 80005d2 <Error_Handler>
Error_Handler();
8000a7a: f7ff fdaa bl 80005d2 <Error_Handler>
Error_Handler();
8000a7e: f7ff fda8 bl 80005d2 <Error_Handler>
8000a82: bf00 nop
8000a84: 200000cc .word 0x200000cc
08000a88 <ChannelSwap>:
void ChannelSwap(Mode *mode_ptr, int channel_new, int *channel_var, int settings_flag, int *settings_var) {
8000a88: b5f8 push {r3, r4, r5, r6, r7, lr}
8000a8a: 4604 mov r4, r0
8000a8c: 460f mov r7, r1
8000a8e: 4616 mov r6, r2
8000a90: 461d mov r5, r3
PWMInit(mode_ptr->coef-1, mode_ptr->freq_pwm_new-1, mode_ptr->pwm_value_res);
8000a92: 7980 ldrb r0, [r0, #6]
8000a94: 8921 ldrh r1, [r4, #8]
8000a96: 3901 subs r1, #1
8000a98: 3801 subs r0, #1
8000a9a: 8962 ldrh r2, [r4, #10]
8000a9c: b289 uxth r1, r1
8000a9e: b2c0 uxtb r0, r0
8000aa0: f7ff ff9e bl 80009e0 <PWMInit>
__HAL_TIM_SET_AUTORELOAD(&htim1, (mode_ptr->time_mode * F_CPU_TIM1 - 1));
8000aa4: 7820 ldrb r0, [r4, #0]
8000aa6: f44f 717a mov.w r1, #1000 ; 0x3e8
8000aaa: fb01 f000 mul.w r0, r1, r0
8000aae: 4b06 ldr r3, [pc, #24] ; (8000ac8 <ChannelSwap+0x40>)
8000ab0: 681a ldr r2, [r3, #0]
8000ab2: 3801 subs r0, #1
8000ab4: 62d0 str r0, [r2, #44] ; 0x2c
8000ab6: 7820 ldrb r0, [r4, #0]
8000ab8: fb01 f000 mul.w r0, r1, r0
8000abc: 3801 subs r0, #1
8000abe: 60d8 str r0, [r3, #12]
*channel_var = channel_new;
8000ac0: 6037 str r7, [r6, #0]
*settings_var = settings_flag;
8000ac2: 9b06 ldr r3, [sp, #24]
8000ac4: 601d str r5, [r3, #0]
}
8000ac6: bdf8 pop {r3, r4, r5, r6, r7, pc}
8000ac8: 20000084 .word 0x20000084
08000acc <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000acc: b480 push {r7}
8000ace: b083 sub sp, #12
8000ad0: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000ad2: 2300 movs r3, #0
8000ad4: 607b str r3, [r7, #4]
8000ad6: 4b10 ldr r3, [pc, #64] ; (8000b18 <HAL_MspInit+0x4c>)
8000ad8: 6c5b ldr r3, [r3, #68] ; 0x44
8000ada: 4a0f ldr r2, [pc, #60] ; (8000b18 <HAL_MspInit+0x4c>)
8000adc: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000ae0: 6453 str r3, [r2, #68] ; 0x44
8000ae2: 4b0d ldr r3, [pc, #52] ; (8000b18 <HAL_MspInit+0x4c>)
8000ae4: 6c5b ldr r3, [r3, #68] ; 0x44
8000ae6: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000aea: 607b str r3, [r7, #4]
8000aec: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000aee: 2300 movs r3, #0
8000af0: 603b str r3, [r7, #0]
8000af2: 4b09 ldr r3, [pc, #36] ; (8000b18 <HAL_MspInit+0x4c>)
8000af4: 6c1b ldr r3, [r3, #64] ; 0x40
8000af6: 4a08 ldr r2, [pc, #32] ; (8000b18 <HAL_MspInit+0x4c>)
8000af8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000afc: 6413 str r3, [r2, #64] ; 0x40
8000afe: 4b06 ldr r3, [pc, #24] ; (8000b18 <HAL_MspInit+0x4c>)
8000b00: 6c1b ldr r3, [r3, #64] ; 0x40
8000b02: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000b06: 603b str r3, [r7, #0]
8000b08: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000b0a: bf00 nop
8000b0c: 370c adds r7, #12
8000b0e: 46bd mov sp, r7
8000b10: f85d 7b04 ldr.w r7, [sp], #4
8000b14: 4770 bx lr
8000b16: bf00 nop
8000b18: 40023800 .word 0x40023800
08000b1c <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8000b1c: b580 push {r7, lr}
8000b1e: b08a sub sp, #40 ; 0x28
8000b20: af00 add r7, sp, #0
8000b22: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000b24: f107 0314 add.w r3, r7, #20
8000b28: 2200 movs r2, #0
8000b2a: 601a str r2, [r3, #0]
8000b2c: 605a str r2, [r3, #4]
8000b2e: 609a str r2, [r3, #8]
8000b30: 60da str r2, [r3, #12]
8000b32: 611a str r2, [r3, #16]
if(hspi->Instance==SPI1)
8000b34: 687b ldr r3, [r7, #4]
8000b36: 681b ldr r3, [r3, #0]
8000b38: 4a19 ldr r2, [pc, #100] ; (8000ba0 <HAL_SPI_MspInit+0x84>)
8000b3a: 4293 cmp r3, r2
8000b3c: d12b bne.n 8000b96 <HAL_SPI_MspInit+0x7a>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
8000b3e: 2300 movs r3, #0
8000b40: 613b str r3, [r7, #16]
8000b42: 4b18 ldr r3, [pc, #96] ; (8000ba4 <HAL_SPI_MspInit+0x88>)
8000b44: 6c5b ldr r3, [r3, #68] ; 0x44
8000b46: 4a17 ldr r2, [pc, #92] ; (8000ba4 <HAL_SPI_MspInit+0x88>)
8000b48: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8000b4c: 6453 str r3, [r2, #68] ; 0x44
8000b4e: 4b15 ldr r3, [pc, #84] ; (8000ba4 <HAL_SPI_MspInit+0x88>)
8000b50: 6c5b ldr r3, [r3, #68] ; 0x44
8000b52: f403 5380 and.w r3, r3, #4096 ; 0x1000
8000b56: 613b str r3, [r7, #16]
8000b58: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000b5a: 2300 movs r3, #0
8000b5c: 60fb str r3, [r7, #12]
8000b5e: 4b11 ldr r3, [pc, #68] ; (8000ba4 <HAL_SPI_MspInit+0x88>)
8000b60: 6b1b ldr r3, [r3, #48] ; 0x30
8000b62: 4a10 ldr r2, [pc, #64] ; (8000ba4 <HAL_SPI_MspInit+0x88>)
8000b64: f043 0301 orr.w r3, r3, #1
8000b68: 6313 str r3, [r2, #48] ; 0x30
8000b6a: 4b0e ldr r3, [pc, #56] ; (8000ba4 <HAL_SPI_MspInit+0x88>)
8000b6c: 6b1b ldr r3, [r3, #48] ; 0x30
8000b6e: f003 0301 and.w r3, r3, #1
8000b72: 60fb str r3, [r7, #12]
8000b74: 68fb ldr r3, [r7, #12]
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
8000b76: 23e0 movs r3, #224 ; 0xe0
8000b78: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b7a: 2302 movs r3, #2
8000b7c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b7e: 2300 movs r3, #0
8000b80: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000b82: 2303 movs r3, #3
8000b84: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8000b86: 2305 movs r3, #5
8000b88: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000b8a: f107 0314 add.w r3, r7, #20
8000b8e: 4619 mov r1, r3
8000b90: 4805 ldr r0, [pc, #20] ; (8000ba8 <HAL_SPI_MspInit+0x8c>)
8000b92: f000 faf7 bl 8001184 <HAL_GPIO_Init>
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
}
8000b96: bf00 nop
8000b98: 3728 adds r7, #40 ; 0x28
8000b9a: 46bd mov sp, r7
8000b9c: bd80 pop {r7, pc}
8000b9e: bf00 nop
8000ba0: 40013000 .word 0x40013000
8000ba4: 40023800 .word 0x40023800
8000ba8: 40020000 .word 0x40020000
08000bac <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8000bac: b580 push {r7, lr}
8000bae: b084 sub sp, #16
8000bb0: af00 add r7, sp, #0
8000bb2: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
8000bb4: 687b ldr r3, [r7, #4]
8000bb6: 681b ldr r3, [r3, #0]
8000bb8: 4a18 ldr r2, [pc, #96] ; (8000c1c <HAL_TIM_Base_MspInit+0x70>)
8000bba: 4293 cmp r3, r2
8000bbc: d116 bne.n 8000bec <HAL_TIM_Base_MspInit+0x40>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
8000bbe: 2300 movs r3, #0
8000bc0: 60fb str r3, [r7, #12]
8000bc2: 4b17 ldr r3, [pc, #92] ; (8000c20 <HAL_TIM_Base_MspInit+0x74>)
8000bc4: 6c5b ldr r3, [r3, #68] ; 0x44
8000bc6: 4a16 ldr r2, [pc, #88] ; (8000c20 <HAL_TIM_Base_MspInit+0x74>)
8000bc8: f043 0301 orr.w r3, r3, #1
8000bcc: 6453 str r3, [r2, #68] ; 0x44
8000bce: 4b14 ldr r3, [pc, #80] ; (8000c20 <HAL_TIM_Base_MspInit+0x74>)
8000bd0: 6c5b ldr r3, [r3, #68] ; 0x44
8000bd2: f003 0301 and.w r3, r3, #1
8000bd6: 60fb str r3, [r7, #12]
8000bd8: 68fb ldr r3, [r7, #12]
/* TIM1 interrupt Init */
HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 0, 0);
8000bda: 2200 movs r2, #0
8000bdc: 2100 movs r1, #0
8000bde: 2019 movs r0, #25
8000be0: f000 fa99 bl 8001116 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
8000be4: 2019 movs r0, #25
8000be6: f000 fab2 bl 800114e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM2_MspInit 1 */
/* USER CODE END TIM2_MspInit 1 */
}
}
8000bea: e012 b.n 8000c12 <HAL_TIM_Base_MspInit+0x66>
else if(htim_base->Instance==TIM2)
8000bec: 687b ldr r3, [r7, #4]
8000bee: 681b ldr r3, [r3, #0]
8000bf0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8000bf4: d10d bne.n 8000c12 <HAL_TIM_Base_MspInit+0x66>
__HAL_RCC_TIM2_CLK_ENABLE();
8000bf6: 2300 movs r3, #0
8000bf8: 60bb str r3, [r7, #8]
8000bfa: 4b09 ldr r3, [pc, #36] ; (8000c20 <HAL_TIM_Base_MspInit+0x74>)
8000bfc: 6c1b ldr r3, [r3, #64] ; 0x40
8000bfe: 4a08 ldr r2, [pc, #32] ; (8000c20 <HAL_TIM_Base_MspInit+0x74>)
8000c00: f043 0301 orr.w r3, r3, #1
8000c04: 6413 str r3, [r2, #64] ; 0x40
8000c06: 4b06 ldr r3, [pc, #24] ; (8000c20 <HAL_TIM_Base_MspInit+0x74>)
8000c08: 6c1b ldr r3, [r3, #64] ; 0x40
8000c0a: f003 0301 and.w r3, r3, #1
8000c0e: 60bb str r3, [r7, #8]
8000c10: 68bb ldr r3, [r7, #8]
}
8000c12: bf00 nop
8000c14: 3710 adds r7, #16
8000c16: 46bd mov sp, r7
8000c18: bd80 pop {r7, pc}
8000c1a: bf00 nop
8000c1c: 40010000 .word 0x40010000
8000c20: 40023800 .word 0x40023800
08000c24 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8000c24: b580 push {r7, lr}
8000c26: b08a sub sp, #40 ; 0x28
8000c28: af00 add r7, sp, #0
8000c2a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000c2c: f107 0314 add.w r3, r7, #20
8000c30: 2200 movs r2, #0
8000c32: 601a str r2, [r3, #0]
8000c34: 605a str r2, [r3, #4]
8000c36: 609a str r2, [r3, #8]
8000c38: 60da str r2, [r3, #12]
8000c3a: 611a str r2, [r3, #16]
if(htim->Instance==TIM1)
8000c3c: 687b ldr r3, [r7, #4]
8000c3e: 681b ldr r3, [r3, #0]
8000c40: 4a24 ldr r2, [pc, #144] ; (8000cd4 <HAL_TIM_MspPostInit+0xb0>)
8000c42: 4293 cmp r3, r2
8000c44: d11f bne.n 8000c86 <HAL_TIM_MspPostInit+0x62>
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOE_CLK_ENABLE();
8000c46: 2300 movs r3, #0
8000c48: 613b str r3, [r7, #16]
8000c4a: 4b23 ldr r3, [pc, #140] ; (8000cd8 <HAL_TIM_MspPostInit+0xb4>)
8000c4c: 6b1b ldr r3, [r3, #48] ; 0x30
8000c4e: 4a22 ldr r2, [pc, #136] ; (8000cd8 <HAL_TIM_MspPostInit+0xb4>)
8000c50: f043 0310 orr.w r3, r3, #16
8000c54: 6313 str r3, [r2, #48] ; 0x30
8000c56: 4b20 ldr r3, [pc, #128] ; (8000cd8 <HAL_TIM_MspPostInit+0xb4>)
8000c58: 6b1b ldr r3, [r3, #48] ; 0x30
8000c5a: f003 0310 and.w r3, r3, #16
8000c5e: 613b str r3, [r7, #16]
8000c60: 693b ldr r3, [r7, #16]
/**TIM1 GPIO Configuration
PE9 ------> TIM1_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
8000c62: f44f 7300 mov.w r3, #512 ; 0x200
8000c66: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c68: 2302 movs r3, #2
8000c6a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c6c: 2300 movs r3, #0
8000c6e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c70: 2300 movs r3, #0
8000c72: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
8000c74: 2301 movs r3, #1
8000c76: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000c78: f107 0314 add.w r3, r7, #20
8000c7c: 4619 mov r1, r3
8000c7e: 4817 ldr r0, [pc, #92] ; (8000cdc <HAL_TIM_MspPostInit+0xb8>)
8000c80: f000 fa80 bl 8001184 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM2_MspPostInit 1 */
/* USER CODE END TIM2_MspPostInit 1 */
}
}
8000c84: e022 b.n 8000ccc <HAL_TIM_MspPostInit+0xa8>
else if(htim->Instance==TIM2)
8000c86: 687b ldr r3, [r7, #4]
8000c88: 681b ldr r3, [r3, #0]
8000c8a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8000c8e: d11d bne.n 8000ccc <HAL_TIM_MspPostInit+0xa8>
__HAL_RCC_GPIOA_CLK_ENABLE();
8000c90: 2300 movs r3, #0
8000c92: 60fb str r3, [r7, #12]
8000c94: 4b10 ldr r3, [pc, #64] ; (8000cd8 <HAL_TIM_MspPostInit+0xb4>)
8000c96: 6b1b ldr r3, [r3, #48] ; 0x30
8000c98: 4a0f ldr r2, [pc, #60] ; (8000cd8 <HAL_TIM_MspPostInit+0xb4>)
8000c9a: f043 0301 orr.w r3, r3, #1
8000c9e: 6313 str r3, [r2, #48] ; 0x30
8000ca0: 4b0d ldr r3, [pc, #52] ; (8000cd8 <HAL_TIM_MspPostInit+0xb4>)
8000ca2: 6b1b ldr r3, [r3, #48] ; 0x30
8000ca4: f003 0301 and.w r3, r3, #1
8000ca8: 60fb str r3, [r7, #12]
8000caa: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_0;
8000cac: 2301 movs r3, #1
8000cae: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000cb0: 2302 movs r3, #2
8000cb2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
8000cb4: 2302 movs r3, #2
8000cb6: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000cb8: 2300 movs r3, #0
8000cba: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8000cbc: 2301 movs r3, #1
8000cbe: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000cc0: f107 0314 add.w r3, r7, #20
8000cc4: 4619 mov r1, r3
8000cc6: 4806 ldr r0, [pc, #24] ; (8000ce0 <HAL_TIM_MspPostInit+0xbc>)
8000cc8: f000 fa5c bl 8001184 <HAL_GPIO_Init>
}
8000ccc: bf00 nop
8000cce: 3728 adds r7, #40 ; 0x28
8000cd0: 46bd mov sp, r7
8000cd2: bd80 pop {r7, pc}
8000cd4: 40010000 .word 0x40010000
8000cd8: 40023800 .word 0x40023800
8000cdc: 40021000 .word 0x40021000
8000ce0: 40020000 .word 0x40020000
08000ce4 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000ce4: b480 push {r7}
8000ce6: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000ce8: e7fe b.n 8000ce8 <NMI_Handler+0x4>
08000cea <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000cea: b480 push {r7}
8000cec: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000cee: e7fe b.n 8000cee <HardFault_Handler+0x4>
08000cf0 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000cf0: b480 push {r7}
8000cf2: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000cf4: e7fe b.n 8000cf4 <MemManage_Handler+0x4>
08000cf6 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000cf6: b480 push {r7}
8000cf8: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000cfa: e7fe b.n 8000cfa <BusFault_Handler+0x4>
08000cfc <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000cfc: b480 push {r7}
8000cfe: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000d00: e7fe b.n 8000d00 <UsageFault_Handler+0x4>
08000d02 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000d02: b480 push {r7}
8000d04: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000d06: bf00 nop
8000d08: 46bd mov sp, r7
8000d0a: f85d 7b04 ldr.w r7, [sp], #4
8000d0e: 4770 bx lr
08000d10 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000d10: b480 push {r7}
8000d12: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000d14: bf00 nop
8000d16: 46bd mov sp, r7
8000d18: f85d 7b04 ldr.w r7, [sp], #4
8000d1c: 4770 bx lr
08000d1e <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000d1e: b480 push {r7}
8000d20: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000d22: bf00 nop
8000d24: 46bd mov sp, r7
8000d26: f85d 7b04 ldr.w r7, [sp], #4
8000d2a: 4770 bx lr
08000d2c <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000d2c: b580 push {r7, lr}
8000d2e: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000d30: f000 f8f6 bl 8000f20 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000d34: bf00 nop
8000d36: bd80 pop {r7, pc}
08000d38 <TIM1_UP_TIM10_IRQHandler>:
/**
* @brief This function handles TIM1 update interrupt and TIM10 global interrupt.
*/
void TIM1_UP_TIM10_IRQHandler(void)
{
8000d38: b580 push {r7, lr}
8000d3a: b082 sub sp, #8
8000d3c: af02 add r7, sp, #8
/* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */
HAL_TIM_PWM_Stop(&htim2, TIM_CHANNEL_1);
8000d3e: 2100 movs r1, #0
8000d40: 4817 ldr r0, [pc, #92] ; (8000da0 <TIM1_UP_TIM10_IRQHandler+0x68>)
8000d42: f001 fe9f bl 8002a84 <HAL_TIM_PWM_Stop>
if (channel == 1) { // сейчас канал 1
8000d46: 4b17 ldr r3, [pc, #92] ; (8000da4 <TIM1_UP_TIM10_IRQHandler+0x6c>)
8000d48: 681b ldr r3, [r3, #0]
8000d4a: 2b01 cmp r3, #1
8000d4c: d115 bne.n 8000d7a <TIM1_UP_TIM10_IRQHandler+0x42>
if (iter == 0) { // стартовая настройка
8000d4e: 4b16 ldr r3, [pc, #88] ; (8000da8 <TIM1_UP_TIM10_IRQHandler+0x70>)
8000d50: 681b ldr r3, [r3, #0]
8000d52: 2b00 cmp r3, #0
8000d54: d108 bne.n 8000d68 <TIM1_UP_TIM10_IRQHandler+0x30>
CommonChannelActions(&modes[0], 1, &channel, &iter, &settings_set);
8000d56: 4b15 ldr r3, [pc, #84] ; (8000dac <TIM1_UP_TIM10_IRQHandler+0x74>)
8000d58: 9300 str r3, [sp, #0]
8000d5a: 4b13 ldr r3, [pc, #76] ; (8000da8 <TIM1_UP_TIM10_IRQHandler+0x70>)
8000d5c: 4a11 ldr r2, [pc, #68] ; (8000da4 <TIM1_UP_TIM10_IRQHandler+0x6c>)
8000d5e: 2101 movs r1, #1
8000d60: 4813 ldr r0, [pc, #76] ; (8000db0 <TIM1_UP_TIM10_IRQHandler+0x78>)
8000d62: f000 f82b bl 8000dbc <CommonChannelActions>
8000d66: e014 b.n 8000d92 <TIM1_UP_TIM10_IRQHandler+0x5a>
} else {
CommonChannelActions(&modes[1], 2, &channel, &iter, &settings_set);
8000d68: 4b10 ldr r3, [pc, #64] ; (8000dac <TIM1_UP_TIM10_IRQHandler+0x74>)
8000d6a: 9300 str r3, [sp, #0]
8000d6c: 4b0e ldr r3, [pc, #56] ; (8000da8 <TIM1_UP_TIM10_IRQHandler+0x70>)
8000d6e: 4a0d ldr r2, [pc, #52] ; (8000da4 <TIM1_UP_TIM10_IRQHandler+0x6c>)
8000d70: 2102 movs r1, #2
8000d72: 4810 ldr r0, [pc, #64] ; (8000db4 <TIM1_UP_TIM10_IRQHandler+0x7c>)
8000d74: f000 f822 bl 8000dbc <CommonChannelActions>
8000d78: e00b b.n 8000d92 <TIM1_UP_TIM10_IRQHandler+0x5a>
}
} else if (channel == 2) { // сейчас канал 2
8000d7a: 4b0a ldr r3, [pc, #40] ; (8000da4 <TIM1_UP_TIM10_IRQHandler+0x6c>)
8000d7c: 681b ldr r3, [r3, #0]
8000d7e: 2b02 cmp r3, #2
8000d80: d107 bne.n 8000d92 <TIM1_UP_TIM10_IRQHandler+0x5a>
CommonChannelActions(&modes[0], 1, &channel, &iter, &settings_set);
8000d82: 4b0a ldr r3, [pc, #40] ; (8000dac <TIM1_UP_TIM10_IRQHandler+0x74>)
8000d84: 9300 str r3, [sp, #0]
8000d86: 4b08 ldr r3, [pc, #32] ; (8000da8 <TIM1_UP_TIM10_IRQHandler+0x70>)
8000d88: 4a06 ldr r2, [pc, #24] ; (8000da4 <TIM1_UP_TIM10_IRQHandler+0x6c>)
8000d8a: 2101 movs r1, #1
8000d8c: 4808 ldr r0, [pc, #32] ; (8000db0 <TIM1_UP_TIM10_IRQHandler+0x78>)
8000d8e: f000 f815 bl 8000dbc <CommonChannelActions>
}
//HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_1);
/* USER CODE END TIM1_UP_TIM10_IRQn 0 */
HAL_TIM_IRQHandler(&htim1);
8000d92: 4809 ldr r0, [pc, #36] ; (8000db8 <TIM1_UP_TIM10_IRQHandler+0x80>)
8000d94: f001 fee6 bl 8002b64 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */
/* USER CODE END TIM1_UP_TIM10_IRQn 1 */
}
8000d98: bf00 nop
8000d9a: 46bd mov sp, r7
8000d9c: bd80 pop {r7, pc}
8000d9e: bf00 nop
8000da0: 200000cc .word 0x200000cc
8000da4: 20000000 .word 0x20000000
8000da8: 20000114 .word 0x20000114
8000dac: 20000130 .word 0x20000130
8000db0: 20000118 .word 0x20000118
8000db4: 20000124 .word 0x20000124
8000db8: 20000084 .word 0x20000084
08000dbc <CommonChannelActions>:
/* USER CODE BEGIN 1 */
void CommonChannelActions(Mode *mode_ptr, int channel, int *channelPtr, int *iter, int *settings_set) {
8000dbc: b580 push {r7, lr}
8000dbe: b086 sub sp, #24
8000dc0: af02 add r7, sp, #8
8000dc2: 60f8 str r0, [r7, #12]
8000dc4: 60b9 str r1, [r7, #8]
8000dc6: 607a str r2, [r7, #4]
8000dc8: 603b str r3, [r7, #0]
ChannelSwap(mode_ptr, channel, channelPtr, (channel == 1) ? 1 : 0, settings_set);
8000dca: 68bb ldr r3, [r7, #8]
8000dcc: 2b01 cmp r3, #1
8000dce: bf0c ite eq
8000dd0: 2301 moveq r3, #1
8000dd2: 2300 movne r3, #0
8000dd4: b2db uxtb r3, r3
8000dd6: 461a mov r2, r3
8000dd8: 69bb ldr r3, [r7, #24]
8000dda: 9300 str r3, [sp, #0]
8000ddc: 4613 mov r3, r2
8000dde: 687a ldr r2, [r7, #4]
8000de0: 68b9 ldr r1, [r7, #8]
8000de2: 68f8 ldr r0, [r7, #12]
8000de4: f7ff fe50 bl 8000a88 <ChannelSwap>
SetInvert(mode_ptr);
8000de8: 68f8 ldr r0, [r7, #12]
8000dea: f7ff fbd3 bl 8000594 <SetInvert>
//SetIN_R1(mode_ptr);
if (channel == 1) *iter = 1;
8000dee: 68bb ldr r3, [r7, #8]
8000df0: 2b01 cmp r3, #1
8000df2: d102 bne.n 8000dfa <CommonChannelActions+0x3e>
8000df4: 683b ldr r3, [r7, #0]
8000df6: 2201 movs r2, #1
8000df8: 601a str r2, [r3, #0]
}
8000dfa: bf00 nop
8000dfc: 3710 adds r7, #16
8000dfe: 46bd mov sp, r7
8000e00: bd80 pop {r7, pc}
...
08000e04 <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
8000e04: b480 push {r7}
8000e06: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000e08: 4b06 ldr r3, [pc, #24] ; (8000e24 <SystemInit+0x20>)
8000e0a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8000e0e: 4a05 ldr r2, [pc, #20] ; (8000e24 <SystemInit+0x20>)
8000e10: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8000e14: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000e18: bf00 nop
8000e1a: 46bd mov sp, r7
8000e1c: f85d 7b04 ldr.w r7, [sp], #4
8000e20: 4770 bx lr
8000e22: bf00 nop
8000e24: e000ed00 .word 0xe000ed00
08000e28 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8000e28: f8df d034 ldr.w sp, [pc, #52] ; 8000e60 <LoopFillZerobss+0x12>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000e2c: 480d ldr r0, [pc, #52] ; (8000e64 <LoopFillZerobss+0x16>)
ldr r1, =_edata
8000e2e: 490e ldr r1, [pc, #56] ; (8000e68 <LoopFillZerobss+0x1a>)
ldr r2, =_sidata
8000e30: 4a0e ldr r2, [pc, #56] ; (8000e6c <LoopFillZerobss+0x1e>)
movs r3, #0
8000e32: 2300 movs r3, #0
b LoopCopyDataInit
8000e34: e002 b.n 8000e3c <LoopCopyDataInit>
08000e36 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000e36: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000e38: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000e3a: 3304 adds r3, #4
08000e3c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000e3c: 18c4 adds r4, r0, r3
cmp r4, r1
8000e3e: 428c cmp r4, r1
bcc CopyDataInit
8000e40: d3f9 bcc.n 8000e36 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000e42: 4a0b ldr r2, [pc, #44] ; (8000e70 <LoopFillZerobss+0x22>)
ldr r4, =_ebss
8000e44: 4c0b ldr r4, [pc, #44] ; (8000e74 <LoopFillZerobss+0x26>)
movs r3, #0
8000e46: 2300 movs r3, #0
b LoopFillZerobss
8000e48: e001 b.n 8000e4e <LoopFillZerobss>
08000e4a <FillZerobss>:
FillZerobss:
str r3, [r2]
8000e4a: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000e4c: 3204 adds r2, #4
08000e4e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000e4e: 42a2 cmp r2, r4
bcc FillZerobss
8000e50: d3fb bcc.n 8000e4a <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
8000e52: f7ff ffd7 bl 8000e04 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000e56: f002 fd9f bl 8003998 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000e5a: f7ff fcdb bl 8000814 <main>
bx lr
8000e5e: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8000e60: 20020000 .word 0x20020000
ldr r0, =_sdata
8000e64: 20000000 .word 0x20000000
ldr r1, =_edata
8000e68: 20000010 .word 0x20000010
ldr r2, =_sidata
8000e6c: 08003a18 .word 0x08003a18
ldr r2, =_sbss
8000e70: 20000010 .word 0x20000010
ldr r4, =_ebss
8000e74: 20000138 .word 0x20000138
08000e78 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000e78: e7fe b.n 8000e78 <ADC_IRQHandler>
...
08000e7c <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000e7c: b580 push {r7, lr}
8000e7e: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8000e80: 4b0e ldr r3, [pc, #56] ; (8000ebc <HAL_Init+0x40>)
8000e82: 681b ldr r3, [r3, #0]
8000e84: 4a0d ldr r2, [pc, #52] ; (8000ebc <HAL_Init+0x40>)
8000e86: f443 7300 orr.w r3, r3, #512 ; 0x200
8000e8a: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8000e8c: 4b0b ldr r3, [pc, #44] ; (8000ebc <HAL_Init+0x40>)
8000e8e: 681b ldr r3, [r3, #0]
8000e90: 4a0a ldr r2, [pc, #40] ; (8000ebc <HAL_Init+0x40>)
8000e92: f443 6380 orr.w r3, r3, #1024 ; 0x400
8000e96: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000e98: 4b08 ldr r3, [pc, #32] ; (8000ebc <HAL_Init+0x40>)
8000e9a: 681b ldr r3, [r3, #0]
8000e9c: 4a07 ldr r2, [pc, #28] ; (8000ebc <HAL_Init+0x40>)
8000e9e: f443 7380 orr.w r3, r3, #256 ; 0x100
8000ea2: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000ea4: 2003 movs r0, #3
8000ea6: f000 f92b bl 8001100 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000eaa: 200f movs r0, #15
8000eac: f000 f808 bl 8000ec0 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000eb0: f7ff fe0c bl 8000acc <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000eb4: 2300 movs r3, #0
}
8000eb6: 4618 mov r0, r3
8000eb8: bd80 pop {r7, pc}
8000eba: bf00 nop
8000ebc: 40023c00 .word 0x40023c00
08000ec0 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000ec0: b580 push {r7, lr}
8000ec2: b082 sub sp, #8
8000ec4: af00 add r7, sp, #0
8000ec6: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000ec8: 4b12 ldr r3, [pc, #72] ; (8000f14 <HAL_InitTick+0x54>)
8000eca: 681a ldr r2, [r3, #0]
8000ecc: 4b12 ldr r3, [pc, #72] ; (8000f18 <HAL_InitTick+0x58>)
8000ece: 781b ldrb r3, [r3, #0]
8000ed0: 4619 mov r1, r3
8000ed2: f44f 737a mov.w r3, #1000 ; 0x3e8
8000ed6: fbb3 f3f1 udiv r3, r3, r1
8000eda: fbb2 f3f3 udiv r3, r2, r3
8000ede: 4618 mov r0, r3
8000ee0: f000 f943 bl 800116a <HAL_SYSTICK_Config>
8000ee4: 4603 mov r3, r0
8000ee6: 2b00 cmp r3, #0
8000ee8: d001 beq.n 8000eee <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000eea: 2301 movs r3, #1
8000eec: e00e b.n 8000f0c <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000eee: 687b ldr r3, [r7, #4]
8000ef0: 2b0f cmp r3, #15
8000ef2: d80a bhi.n 8000f0a <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000ef4: 2200 movs r2, #0
8000ef6: 6879 ldr r1, [r7, #4]
8000ef8: f04f 30ff mov.w r0, #4294967295
8000efc: f000 f90b bl 8001116 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000f00: 4a06 ldr r2, [pc, #24] ; (8000f1c <HAL_InitTick+0x5c>)
8000f02: 687b ldr r3, [r7, #4]
8000f04: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000f06: 2300 movs r3, #0
8000f08: e000 b.n 8000f0c <HAL_InitTick+0x4c>
return HAL_ERROR;
8000f0a: 2301 movs r3, #1
}
8000f0c: 4618 mov r0, r3
8000f0e: 3708 adds r7, #8
8000f10: 46bd mov sp, r7
8000f12: bd80 pop {r7, pc}
8000f14: 20000004 .word 0x20000004
8000f18: 2000000c .word 0x2000000c
8000f1c: 20000008 .word 0x20000008
08000f20 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000f20: b480 push {r7}
8000f22: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000f24: 4b06 ldr r3, [pc, #24] ; (8000f40 <HAL_IncTick+0x20>)
8000f26: 781b ldrb r3, [r3, #0]
8000f28: 461a mov r2, r3
8000f2a: 4b06 ldr r3, [pc, #24] ; (8000f44 <HAL_IncTick+0x24>)
8000f2c: 681b ldr r3, [r3, #0]
8000f2e: 4413 add r3, r2
8000f30: 4a04 ldr r2, [pc, #16] ; (8000f44 <HAL_IncTick+0x24>)
8000f32: 6013 str r3, [r2, #0]
}
8000f34: bf00 nop
8000f36: 46bd mov sp, r7
8000f38: f85d 7b04 ldr.w r7, [sp], #4
8000f3c: 4770 bx lr
8000f3e: bf00 nop
8000f40: 2000000c .word 0x2000000c
8000f44: 20000134 .word 0x20000134
08000f48 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000f48: b480 push {r7}
8000f4a: af00 add r7, sp, #0
return uwTick;
8000f4c: 4b03 ldr r3, [pc, #12] ; (8000f5c <HAL_GetTick+0x14>)
8000f4e: 681b ldr r3, [r3, #0]
}
8000f50: 4618 mov r0, r3
8000f52: 46bd mov sp, r7
8000f54: f85d 7b04 ldr.w r7, [sp], #4
8000f58: 4770 bx lr
8000f5a: bf00 nop
8000f5c: 20000134 .word 0x20000134
08000f60 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000f60: b480 push {r7}
8000f62: b085 sub sp, #20
8000f64: af00 add r7, sp, #0
8000f66: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000f68: 687b ldr r3, [r7, #4]
8000f6a: f003 0307 and.w r3, r3, #7
8000f6e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000f70: 4b0c ldr r3, [pc, #48] ; (8000fa4 <__NVIC_SetPriorityGrouping+0x44>)
8000f72: 68db ldr r3, [r3, #12]
8000f74: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000f76: 68ba ldr r2, [r7, #8]
8000f78: f64f 03ff movw r3, #63743 ; 0xf8ff
8000f7c: 4013 ands r3, r2
8000f7e: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000f80: 68fb ldr r3, [r7, #12]
8000f82: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000f84: 68bb ldr r3, [r7, #8]
8000f86: 4313 orrs r3, r2
reg_value = (reg_value |
8000f88: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8000f8c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000f90: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000f92: 4a04 ldr r2, [pc, #16] ; (8000fa4 <__NVIC_SetPriorityGrouping+0x44>)
8000f94: 68bb ldr r3, [r7, #8]
8000f96: 60d3 str r3, [r2, #12]
}
8000f98: bf00 nop
8000f9a: 3714 adds r7, #20
8000f9c: 46bd mov sp, r7
8000f9e: f85d 7b04 ldr.w r7, [sp], #4
8000fa2: 4770 bx lr
8000fa4: e000ed00 .word 0xe000ed00
08000fa8 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000fa8: b480 push {r7}
8000faa: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000fac: 4b04 ldr r3, [pc, #16] ; (8000fc0 <__NVIC_GetPriorityGrouping+0x18>)
8000fae: 68db ldr r3, [r3, #12]
8000fb0: 0a1b lsrs r3, r3, #8
8000fb2: f003 0307 and.w r3, r3, #7
}
8000fb6: 4618 mov r0, r3
8000fb8: 46bd mov sp, r7
8000fba: f85d 7b04 ldr.w r7, [sp], #4
8000fbe: 4770 bx lr
8000fc0: e000ed00 .word 0xe000ed00
08000fc4 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000fc4: b480 push {r7}
8000fc6: b083 sub sp, #12
8000fc8: af00 add r7, sp, #0
8000fca: 4603 mov r3, r0
8000fcc: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000fce: f997 3007 ldrsb.w r3, [r7, #7]
8000fd2: 2b00 cmp r3, #0
8000fd4: db0b blt.n 8000fee <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8000fd6: 79fb ldrb r3, [r7, #7]
8000fd8: f003 021f and.w r2, r3, #31
8000fdc: 4907 ldr r1, [pc, #28] ; (8000ffc <__NVIC_EnableIRQ+0x38>)
8000fde: f997 3007 ldrsb.w r3, [r7, #7]
8000fe2: 095b lsrs r3, r3, #5
8000fe4: 2001 movs r0, #1
8000fe6: fa00 f202 lsl.w r2, r0, r2
8000fea: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8000fee: bf00 nop
8000ff0: 370c adds r7, #12
8000ff2: 46bd mov sp, r7
8000ff4: f85d 7b04 ldr.w r7, [sp], #4
8000ff8: 4770 bx lr
8000ffa: bf00 nop
8000ffc: e000e100 .word 0xe000e100
08001000 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001000: b480 push {r7}
8001002: b083 sub sp, #12
8001004: af00 add r7, sp, #0
8001006: 4603 mov r3, r0
8001008: 6039 str r1, [r7, #0]
800100a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800100c: f997 3007 ldrsb.w r3, [r7, #7]
8001010: 2b00 cmp r3, #0
8001012: db0a blt.n 800102a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001014: 683b ldr r3, [r7, #0]
8001016: b2da uxtb r2, r3
8001018: 490c ldr r1, [pc, #48] ; (800104c <__NVIC_SetPriority+0x4c>)
800101a: f997 3007 ldrsb.w r3, [r7, #7]
800101e: 0112 lsls r2, r2, #4
8001020: b2d2 uxtb r2, r2
8001022: 440b add r3, r1
8001024: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001028: e00a b.n 8001040 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800102a: 683b ldr r3, [r7, #0]
800102c: b2da uxtb r2, r3
800102e: 4908 ldr r1, [pc, #32] ; (8001050 <__NVIC_SetPriority+0x50>)
8001030: 79fb ldrb r3, [r7, #7]
8001032: f003 030f and.w r3, r3, #15
8001036: 3b04 subs r3, #4
8001038: 0112 lsls r2, r2, #4
800103a: b2d2 uxtb r2, r2
800103c: 440b add r3, r1
800103e: 761a strb r2, [r3, #24]
}
8001040: bf00 nop
8001042: 370c adds r7, #12
8001044: 46bd mov sp, r7
8001046: f85d 7b04 ldr.w r7, [sp], #4
800104a: 4770 bx lr
800104c: e000e100 .word 0xe000e100
8001050: e000ed00 .word 0xe000ed00
08001054 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001054: b480 push {r7}
8001056: b089 sub sp, #36 ; 0x24
8001058: af00 add r7, sp, #0
800105a: 60f8 str r0, [r7, #12]
800105c: 60b9 str r1, [r7, #8]
800105e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001060: 68fb ldr r3, [r7, #12]
8001062: f003 0307 and.w r3, r3, #7
8001066: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8001068: 69fb ldr r3, [r7, #28]
800106a: f1c3 0307 rsb r3, r3, #7
800106e: 2b04 cmp r3, #4
8001070: bf28 it cs
8001072: 2304 movcs r3, #4
8001074: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8001076: 69fb ldr r3, [r7, #28]
8001078: 3304 adds r3, #4
800107a: 2b06 cmp r3, #6
800107c: d902 bls.n 8001084 <NVIC_EncodePriority+0x30>
800107e: 69fb ldr r3, [r7, #28]
8001080: 3b03 subs r3, #3
8001082: e000 b.n 8001086 <NVIC_EncodePriority+0x32>
8001084: 2300 movs r3, #0
8001086: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001088: f04f 32ff mov.w r2, #4294967295
800108c: 69bb ldr r3, [r7, #24]
800108e: fa02 f303 lsl.w r3, r2, r3
8001092: 43da mvns r2, r3
8001094: 68bb ldr r3, [r7, #8]
8001096: 401a ands r2, r3
8001098: 697b ldr r3, [r7, #20]
800109a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
800109c: f04f 31ff mov.w r1, #4294967295
80010a0: 697b ldr r3, [r7, #20]
80010a2: fa01 f303 lsl.w r3, r1, r3
80010a6: 43d9 mvns r1, r3
80010a8: 687b ldr r3, [r7, #4]
80010aa: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80010ac: 4313 orrs r3, r2
);
}
80010ae: 4618 mov r0, r3
80010b0: 3724 adds r7, #36 ; 0x24
80010b2: 46bd mov sp, r7
80010b4: f85d 7b04 ldr.w r7, [sp], #4
80010b8: 4770 bx lr
...
080010bc <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80010bc: b580 push {r7, lr}
80010be: b082 sub sp, #8
80010c0: af00 add r7, sp, #0
80010c2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80010c4: 687b ldr r3, [r7, #4]
80010c6: 3b01 subs r3, #1
80010c8: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
80010cc: d301 bcc.n 80010d2 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80010ce: 2301 movs r3, #1
80010d0: e00f b.n 80010f2 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80010d2: 4a0a ldr r2, [pc, #40] ; (80010fc <SysTick_Config+0x40>)
80010d4: 687b ldr r3, [r7, #4]
80010d6: 3b01 subs r3, #1
80010d8: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80010da: 210f movs r1, #15
80010dc: f04f 30ff mov.w r0, #4294967295
80010e0: f7ff ff8e bl 8001000 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80010e4: 4b05 ldr r3, [pc, #20] ; (80010fc <SysTick_Config+0x40>)
80010e6: 2200 movs r2, #0
80010e8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80010ea: 4b04 ldr r3, [pc, #16] ; (80010fc <SysTick_Config+0x40>)
80010ec: 2207 movs r2, #7
80010ee: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80010f0: 2300 movs r3, #0
}
80010f2: 4618 mov r0, r3
80010f4: 3708 adds r7, #8
80010f6: 46bd mov sp, r7
80010f8: bd80 pop {r7, pc}
80010fa: bf00 nop
80010fc: e000e010 .word 0xe000e010
08001100 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001100: b580 push {r7, lr}
8001102: b082 sub sp, #8
8001104: af00 add r7, sp, #0
8001106: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001108: 6878 ldr r0, [r7, #4]
800110a: f7ff ff29 bl 8000f60 <__NVIC_SetPriorityGrouping>
}
800110e: bf00 nop
8001110: 3708 adds r7, #8
8001112: 46bd mov sp, r7
8001114: bd80 pop {r7, pc}
08001116 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001116: b580 push {r7, lr}
8001118: b086 sub sp, #24
800111a: af00 add r7, sp, #0
800111c: 4603 mov r3, r0
800111e: 60b9 str r1, [r7, #8]
8001120: 607a str r2, [r7, #4]
8001122: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8001124: 2300 movs r3, #0
8001126: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001128: f7ff ff3e bl 8000fa8 <__NVIC_GetPriorityGrouping>
800112c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800112e: 687a ldr r2, [r7, #4]
8001130: 68b9 ldr r1, [r7, #8]
8001132: 6978 ldr r0, [r7, #20]
8001134: f7ff ff8e bl 8001054 <NVIC_EncodePriority>
8001138: 4602 mov r2, r0
800113a: f997 300f ldrsb.w r3, [r7, #15]
800113e: 4611 mov r1, r2
8001140: 4618 mov r0, r3
8001142: f7ff ff5d bl 8001000 <__NVIC_SetPriority>
}
8001146: bf00 nop
8001148: 3718 adds r7, #24
800114a: 46bd mov sp, r7
800114c: bd80 pop {r7, pc}
0800114e <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800114e: b580 push {r7, lr}
8001150: b082 sub sp, #8
8001152: af00 add r7, sp, #0
8001154: 4603 mov r3, r0
8001156: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001158: f997 3007 ldrsb.w r3, [r7, #7]
800115c: 4618 mov r0, r3
800115e: f7ff ff31 bl 8000fc4 <__NVIC_EnableIRQ>
}
8001162: bf00 nop
8001164: 3708 adds r7, #8
8001166: 46bd mov sp, r7
8001168: bd80 pop {r7, pc}
0800116a <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800116a: b580 push {r7, lr}
800116c: b082 sub sp, #8
800116e: af00 add r7, sp, #0
8001170: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8001172: 6878 ldr r0, [r7, #4]
8001174: f7ff ffa2 bl 80010bc <SysTick_Config>
8001178: 4603 mov r3, r0
}
800117a: 4618 mov r0, r3
800117c: 3708 adds r7, #8
800117e: 46bd mov sp, r7
8001180: bd80 pop {r7, pc}
...
08001184 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001184: b480 push {r7}
8001186: b089 sub sp, #36 ; 0x24
8001188: af00 add r7, sp, #0
800118a: 6078 str r0, [r7, #4]
800118c: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
800118e: 2300 movs r3, #0
8001190: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
8001192: 2300 movs r3, #0
8001194: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8001196: 2300 movs r3, #0
8001198: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
800119a: 2300 movs r3, #0
800119c: 61fb str r3, [r7, #28]
800119e: e16b b.n 8001478 <HAL_GPIO_Init+0x2f4>
{
/* Get the IO position */
ioposition = 0x01U << position;
80011a0: 2201 movs r2, #1
80011a2: 69fb ldr r3, [r7, #28]
80011a4: fa02 f303 lsl.w r3, r2, r3
80011a8: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80011aa: 683b ldr r3, [r7, #0]
80011ac: 681b ldr r3, [r3, #0]
80011ae: 697a ldr r2, [r7, #20]
80011b0: 4013 ands r3, r2
80011b2: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
80011b4: 693a ldr r2, [r7, #16]
80011b6: 697b ldr r3, [r7, #20]
80011b8: 429a cmp r2, r3
80011ba: f040 815a bne.w 8001472 <HAL_GPIO_Init+0x2ee>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
80011be: 683b ldr r3, [r7, #0]
80011c0: 685b ldr r3, [r3, #4]
80011c2: f003 0303 and.w r3, r3, #3
80011c6: 2b01 cmp r3, #1
80011c8: d005 beq.n 80011d6 <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80011ca: 683b ldr r3, [r7, #0]
80011cc: 685b ldr r3, [r3, #4]
80011ce: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
80011d2: 2b02 cmp r3, #2
80011d4: d130 bne.n 8001238 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
80011d6: 687b ldr r3, [r7, #4]
80011d8: 689b ldr r3, [r3, #8]
80011da: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
80011dc: 69fb ldr r3, [r7, #28]
80011de: 005b lsls r3, r3, #1
80011e0: 2203 movs r2, #3
80011e2: fa02 f303 lsl.w r3, r2, r3
80011e6: 43db mvns r3, r3
80011e8: 69ba ldr r2, [r7, #24]
80011ea: 4013 ands r3, r2
80011ec: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
80011ee: 683b ldr r3, [r7, #0]
80011f0: 68da ldr r2, [r3, #12]
80011f2: 69fb ldr r3, [r7, #28]
80011f4: 005b lsls r3, r3, #1
80011f6: fa02 f303 lsl.w r3, r2, r3
80011fa: 69ba ldr r2, [r7, #24]
80011fc: 4313 orrs r3, r2
80011fe: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8001200: 687b ldr r3, [r7, #4]
8001202: 69ba ldr r2, [r7, #24]
8001204: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001206: 687b ldr r3, [r7, #4]
8001208: 685b ldr r3, [r3, #4]
800120a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
800120c: 2201 movs r2, #1
800120e: 69fb ldr r3, [r7, #28]
8001210: fa02 f303 lsl.w r3, r2, r3
8001214: 43db mvns r3, r3
8001216: 69ba ldr r2, [r7, #24]
8001218: 4013 ands r3, r2
800121a: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800121c: 683b ldr r3, [r7, #0]
800121e: 685b ldr r3, [r3, #4]
8001220: 091b lsrs r3, r3, #4
8001222: f003 0201 and.w r2, r3, #1
8001226: 69fb ldr r3, [r7, #28]
8001228: fa02 f303 lsl.w r3, r2, r3
800122c: 69ba ldr r2, [r7, #24]
800122e: 4313 orrs r3, r2
8001230: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8001232: 687b ldr r3, [r7, #4]
8001234: 69ba ldr r2, [r7, #24]
8001236: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001238: 683b ldr r3, [r7, #0]
800123a: 685b ldr r3, [r3, #4]
800123c: f003 0303 and.w r3, r3, #3
8001240: 2b03 cmp r3, #3
8001242: d017 beq.n 8001274 <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001244: 687b ldr r3, [r7, #4]
8001246: 68db ldr r3, [r3, #12]
8001248: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
800124a: 69fb ldr r3, [r7, #28]
800124c: 005b lsls r3, r3, #1
800124e: 2203 movs r2, #3
8001250: fa02 f303 lsl.w r3, r2, r3
8001254: 43db mvns r3, r3
8001256: 69ba ldr r2, [r7, #24]
8001258: 4013 ands r3, r2
800125a: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
800125c: 683b ldr r3, [r7, #0]
800125e: 689a ldr r2, [r3, #8]
8001260: 69fb ldr r3, [r7, #28]
8001262: 005b lsls r3, r3, #1
8001264: fa02 f303 lsl.w r3, r2, r3
8001268: 69ba ldr r2, [r7, #24]
800126a: 4313 orrs r3, r2
800126c: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
800126e: 687b ldr r3, [r7, #4]
8001270: 69ba ldr r2, [r7, #24]
8001272: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001274: 683b ldr r3, [r7, #0]
8001276: 685b ldr r3, [r3, #4]
8001278: f003 0303 and.w r3, r3, #3
800127c: 2b02 cmp r3, #2
800127e: d123 bne.n 80012c8 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8001280: 69fb ldr r3, [r7, #28]
8001282: 08da lsrs r2, r3, #3
8001284: 687b ldr r3, [r7, #4]
8001286: 3208 adds r2, #8
8001288: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800128c: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
800128e: 69fb ldr r3, [r7, #28]
8001290: f003 0307 and.w r3, r3, #7
8001294: 009b lsls r3, r3, #2
8001296: 220f movs r2, #15
8001298: fa02 f303 lsl.w r3, r2, r3
800129c: 43db mvns r3, r3
800129e: 69ba ldr r2, [r7, #24]
80012a0: 4013 ands r3, r2
80012a2: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
80012a4: 683b ldr r3, [r7, #0]
80012a6: 691a ldr r2, [r3, #16]
80012a8: 69fb ldr r3, [r7, #28]
80012aa: f003 0307 and.w r3, r3, #7
80012ae: 009b lsls r3, r3, #2
80012b0: fa02 f303 lsl.w r3, r2, r3
80012b4: 69ba ldr r2, [r7, #24]
80012b6: 4313 orrs r3, r2
80012b8: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
80012ba: 69fb ldr r3, [r7, #28]
80012bc: 08da lsrs r2, r3, #3
80012be: 687b ldr r3, [r7, #4]
80012c0: 3208 adds r2, #8
80012c2: 69b9 ldr r1, [r7, #24]
80012c4: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
80012c8: 687b ldr r3, [r7, #4]
80012ca: 681b ldr r3, [r3, #0]
80012cc: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
80012ce: 69fb ldr r3, [r7, #28]
80012d0: 005b lsls r3, r3, #1
80012d2: 2203 movs r2, #3
80012d4: fa02 f303 lsl.w r3, r2, r3
80012d8: 43db mvns r3, r3
80012da: 69ba ldr r2, [r7, #24]
80012dc: 4013 ands r3, r2
80012de: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
80012e0: 683b ldr r3, [r7, #0]
80012e2: 685b ldr r3, [r3, #4]
80012e4: f003 0203 and.w r2, r3, #3
80012e8: 69fb ldr r3, [r7, #28]
80012ea: 005b lsls r3, r3, #1
80012ec: fa02 f303 lsl.w r3, r2, r3
80012f0: 69ba ldr r2, [r7, #24]
80012f2: 4313 orrs r3, r2
80012f4: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
80012f6: 687b ldr r3, [r7, #4]
80012f8: 69ba ldr r2, [r7, #24]
80012fa: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
80012fc: 683b ldr r3, [r7, #0]
80012fe: 685b ldr r3, [r3, #4]
8001300: f403 3340 and.w r3, r3, #196608 ; 0x30000
8001304: 2b00 cmp r3, #0
8001306: f000 80b4 beq.w 8001472 <HAL_GPIO_Init+0x2ee>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800130a: 2300 movs r3, #0
800130c: 60fb str r3, [r7, #12]
800130e: 4b60 ldr r3, [pc, #384] ; (8001490 <HAL_GPIO_Init+0x30c>)
8001310: 6c5b ldr r3, [r3, #68] ; 0x44
8001312: 4a5f ldr r2, [pc, #380] ; (8001490 <HAL_GPIO_Init+0x30c>)
8001314: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8001318: 6453 str r3, [r2, #68] ; 0x44
800131a: 4b5d ldr r3, [pc, #372] ; (8001490 <HAL_GPIO_Init+0x30c>)
800131c: 6c5b ldr r3, [r3, #68] ; 0x44
800131e: f403 4380 and.w r3, r3, #16384 ; 0x4000
8001322: 60fb str r3, [r7, #12]
8001324: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8001326: 4a5b ldr r2, [pc, #364] ; (8001494 <HAL_GPIO_Init+0x310>)
8001328: 69fb ldr r3, [r7, #28]
800132a: 089b lsrs r3, r3, #2
800132c: 3302 adds r3, #2
800132e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001332: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8001334: 69fb ldr r3, [r7, #28]
8001336: f003 0303 and.w r3, r3, #3
800133a: 009b lsls r3, r3, #2
800133c: 220f movs r2, #15
800133e: fa02 f303 lsl.w r3, r2, r3
8001342: 43db mvns r3, r3
8001344: 69ba ldr r2, [r7, #24]
8001346: 4013 ands r3, r2
8001348: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
800134a: 687b ldr r3, [r7, #4]
800134c: 4a52 ldr r2, [pc, #328] ; (8001498 <HAL_GPIO_Init+0x314>)
800134e: 4293 cmp r3, r2
8001350: d02b beq.n 80013aa <HAL_GPIO_Init+0x226>
8001352: 687b ldr r3, [r7, #4]
8001354: 4a51 ldr r2, [pc, #324] ; (800149c <HAL_GPIO_Init+0x318>)
8001356: 4293 cmp r3, r2
8001358: d025 beq.n 80013a6 <HAL_GPIO_Init+0x222>
800135a: 687b ldr r3, [r7, #4]
800135c: 4a50 ldr r2, [pc, #320] ; (80014a0 <HAL_GPIO_Init+0x31c>)
800135e: 4293 cmp r3, r2
8001360: d01f beq.n 80013a2 <HAL_GPIO_Init+0x21e>
8001362: 687b ldr r3, [r7, #4]
8001364: 4a4f ldr r2, [pc, #316] ; (80014a4 <HAL_GPIO_Init+0x320>)
8001366: 4293 cmp r3, r2
8001368: d019 beq.n 800139e <HAL_GPIO_Init+0x21a>
800136a: 687b ldr r3, [r7, #4]
800136c: 4a4e ldr r2, [pc, #312] ; (80014a8 <HAL_GPIO_Init+0x324>)
800136e: 4293 cmp r3, r2
8001370: d013 beq.n 800139a <HAL_GPIO_Init+0x216>
8001372: 687b ldr r3, [r7, #4]
8001374: 4a4d ldr r2, [pc, #308] ; (80014ac <HAL_GPIO_Init+0x328>)
8001376: 4293 cmp r3, r2
8001378: d00d beq.n 8001396 <HAL_GPIO_Init+0x212>
800137a: 687b ldr r3, [r7, #4]
800137c: 4a4c ldr r2, [pc, #304] ; (80014b0 <HAL_GPIO_Init+0x32c>)
800137e: 4293 cmp r3, r2
8001380: d007 beq.n 8001392 <HAL_GPIO_Init+0x20e>
8001382: 687b ldr r3, [r7, #4]
8001384: 4a4b ldr r2, [pc, #300] ; (80014b4 <HAL_GPIO_Init+0x330>)
8001386: 4293 cmp r3, r2
8001388: d101 bne.n 800138e <HAL_GPIO_Init+0x20a>
800138a: 2307 movs r3, #7
800138c: e00e b.n 80013ac <HAL_GPIO_Init+0x228>
800138e: 2308 movs r3, #8
8001390: e00c b.n 80013ac <HAL_GPIO_Init+0x228>
8001392: 2306 movs r3, #6
8001394: e00a b.n 80013ac <HAL_GPIO_Init+0x228>
8001396: 2305 movs r3, #5
8001398: e008 b.n 80013ac <HAL_GPIO_Init+0x228>
800139a: 2304 movs r3, #4
800139c: e006 b.n 80013ac <HAL_GPIO_Init+0x228>
800139e: 2303 movs r3, #3
80013a0: e004 b.n 80013ac <HAL_GPIO_Init+0x228>
80013a2: 2302 movs r3, #2
80013a4: e002 b.n 80013ac <HAL_GPIO_Init+0x228>
80013a6: 2301 movs r3, #1
80013a8: e000 b.n 80013ac <HAL_GPIO_Init+0x228>
80013aa: 2300 movs r3, #0
80013ac: 69fa ldr r2, [r7, #28]
80013ae: f002 0203 and.w r2, r2, #3
80013b2: 0092 lsls r2, r2, #2
80013b4: 4093 lsls r3, r2
80013b6: 69ba ldr r2, [r7, #24]
80013b8: 4313 orrs r3, r2
80013ba: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
80013bc: 4935 ldr r1, [pc, #212] ; (8001494 <HAL_GPIO_Init+0x310>)
80013be: 69fb ldr r3, [r7, #28]
80013c0: 089b lsrs r3, r3, #2
80013c2: 3302 adds r3, #2
80013c4: 69ba ldr r2, [r7, #24]
80013c6: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80013ca: 4b3b ldr r3, [pc, #236] ; (80014b8 <HAL_GPIO_Init+0x334>)
80013cc: 689b ldr r3, [r3, #8]
80013ce: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80013d0: 693b ldr r3, [r7, #16]
80013d2: 43db mvns r3, r3
80013d4: 69ba ldr r2, [r7, #24]
80013d6: 4013 ands r3, r2
80013d8: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
80013da: 683b ldr r3, [r7, #0]
80013dc: 685b ldr r3, [r3, #4]
80013de: f403 1380 and.w r3, r3, #1048576 ; 0x100000
80013e2: 2b00 cmp r3, #0
80013e4: d003 beq.n 80013ee <HAL_GPIO_Init+0x26a>
{
temp |= iocurrent;
80013e6: 69ba ldr r2, [r7, #24]
80013e8: 693b ldr r3, [r7, #16]
80013ea: 4313 orrs r3, r2
80013ec: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
80013ee: 4a32 ldr r2, [pc, #200] ; (80014b8 <HAL_GPIO_Init+0x334>)
80013f0: 69bb ldr r3, [r7, #24]
80013f2: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
80013f4: 4b30 ldr r3, [pc, #192] ; (80014b8 <HAL_GPIO_Init+0x334>)
80013f6: 68db ldr r3, [r3, #12]
80013f8: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80013fa: 693b ldr r3, [r7, #16]
80013fc: 43db mvns r3, r3
80013fe: 69ba ldr r2, [r7, #24]
8001400: 4013 ands r3, r2
8001402: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8001404: 683b ldr r3, [r7, #0]
8001406: 685b ldr r3, [r3, #4]
8001408: f403 1300 and.w r3, r3, #2097152 ; 0x200000
800140c: 2b00 cmp r3, #0
800140e: d003 beq.n 8001418 <HAL_GPIO_Init+0x294>
{
temp |= iocurrent;
8001410: 69ba ldr r2, [r7, #24]
8001412: 693b ldr r3, [r7, #16]
8001414: 4313 orrs r3, r2
8001416: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8001418: 4a27 ldr r2, [pc, #156] ; (80014b8 <HAL_GPIO_Init+0x334>)
800141a: 69bb ldr r3, [r7, #24]
800141c: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
800141e: 4b26 ldr r3, [pc, #152] ; (80014b8 <HAL_GPIO_Init+0x334>)
8001420: 685b ldr r3, [r3, #4]
8001422: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001424: 693b ldr r3, [r7, #16]
8001426: 43db mvns r3, r3
8001428: 69ba ldr r2, [r7, #24]
800142a: 4013 ands r3, r2
800142c: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
800142e: 683b ldr r3, [r7, #0]
8001430: 685b ldr r3, [r3, #4]
8001432: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001436: 2b00 cmp r3, #0
8001438: d003 beq.n 8001442 <HAL_GPIO_Init+0x2be>
{
temp |= iocurrent;
800143a: 69ba ldr r2, [r7, #24]
800143c: 693b ldr r3, [r7, #16]
800143e: 4313 orrs r3, r2
8001440: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8001442: 4a1d ldr r2, [pc, #116] ; (80014b8 <HAL_GPIO_Init+0x334>)
8001444: 69bb ldr r3, [r7, #24]
8001446: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8001448: 4b1b ldr r3, [pc, #108] ; (80014b8 <HAL_GPIO_Init+0x334>)
800144a: 681b ldr r3, [r3, #0]
800144c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800144e: 693b ldr r3, [r7, #16]
8001450: 43db mvns r3, r3
8001452: 69ba ldr r2, [r7, #24]
8001454: 4013 ands r3, r2
8001456: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8001458: 683b ldr r3, [r7, #0]
800145a: 685b ldr r3, [r3, #4]
800145c: f403 3380 and.w r3, r3, #65536 ; 0x10000
8001460: 2b00 cmp r3, #0
8001462: d003 beq.n 800146c <HAL_GPIO_Init+0x2e8>
{
temp |= iocurrent;
8001464: 69ba ldr r2, [r7, #24]
8001466: 693b ldr r3, [r7, #16]
8001468: 4313 orrs r3, r2
800146a: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
800146c: 4a12 ldr r2, [pc, #72] ; (80014b8 <HAL_GPIO_Init+0x334>)
800146e: 69bb ldr r3, [r7, #24]
8001470: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
8001472: 69fb ldr r3, [r7, #28]
8001474: 3301 adds r3, #1
8001476: 61fb str r3, [r7, #28]
8001478: 69fb ldr r3, [r7, #28]
800147a: 2b0f cmp r3, #15
800147c: f67f ae90 bls.w 80011a0 <HAL_GPIO_Init+0x1c>
}
}
}
}
8001480: bf00 nop
8001482: bf00 nop
8001484: 3724 adds r7, #36 ; 0x24
8001486: 46bd mov sp, r7
8001488: f85d 7b04 ldr.w r7, [sp], #4
800148c: 4770 bx lr
800148e: bf00 nop
8001490: 40023800 .word 0x40023800
8001494: 40013800 .word 0x40013800
8001498: 40020000 .word 0x40020000
800149c: 40020400 .word 0x40020400
80014a0: 40020800 .word 0x40020800
80014a4: 40020c00 .word 0x40020c00
80014a8: 40021000 .word 0x40021000
80014ac: 40021400 .word 0x40021400
80014b0: 40021800 .word 0x40021800
80014b4: 40021c00 .word 0x40021c00
80014b8: 40013c00 .word 0x40013c00
080014bc <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80014bc: b480 push {r7}
80014be: b083 sub sp, #12
80014c0: af00 add r7, sp, #0
80014c2: 6078 str r0, [r7, #4]
80014c4: 460b mov r3, r1
80014c6: 807b strh r3, [r7, #2]
80014c8: 4613 mov r3, r2
80014ca: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
80014cc: 787b ldrb r3, [r7, #1]
80014ce: 2b00 cmp r3, #0
80014d0: d003 beq.n 80014da <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
80014d2: 887a ldrh r2, [r7, #2]
80014d4: 687b ldr r3, [r7, #4]
80014d6: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
80014d8: e003 b.n 80014e2 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
80014da: 887b ldrh r3, [r7, #2]
80014dc: 041a lsls r2, r3, #16
80014de: 687b ldr r3, [r7, #4]
80014e0: 619a str r2, [r3, #24]
}
80014e2: bf00 nop
80014e4: 370c adds r7, #12
80014e6: 46bd mov sp, r7
80014e8: f85d 7b04 ldr.w r7, [sp], #4
80014ec: 4770 bx lr
...
080014f0 <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80014f0: b580 push {r7, lr}
80014f2: b086 sub sp, #24
80014f4: af00 add r7, sp, #0
80014f6: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
80014f8: 687b ldr r3, [r7, #4]
80014fa: 2b00 cmp r3, #0
80014fc: d101 bne.n 8001502 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80014fe: 2301 movs r3, #1
8001500: e267 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001502: 687b ldr r3, [r7, #4]
8001504: 681b ldr r3, [r3, #0]
8001506: f003 0301 and.w r3, r3, #1
800150a: 2b00 cmp r3, #0
800150c: d075 beq.n 80015fa <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
800150e: 4b88 ldr r3, [pc, #544] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001510: 689b ldr r3, [r3, #8]
8001512: f003 030c and.w r3, r3, #12
8001516: 2b04 cmp r3, #4
8001518: d00c beq.n 8001534 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
800151a: 4b85 ldr r3, [pc, #532] ; (8001730 <HAL_RCC_OscConfig+0x240>)
800151c: 689b ldr r3, [r3, #8]
800151e: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8001522: 2b08 cmp r3, #8
8001524: d112 bne.n 800154c <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8001526: 4b82 ldr r3, [pc, #520] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001528: 685b ldr r3, [r3, #4]
800152a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800152e: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8001532: d10b bne.n 800154c <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001534: 4b7e ldr r3, [pc, #504] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001536: 681b ldr r3, [r3, #0]
8001538: f403 3300 and.w r3, r3, #131072 ; 0x20000
800153c: 2b00 cmp r3, #0
800153e: d05b beq.n 80015f8 <HAL_RCC_OscConfig+0x108>
8001540: 687b ldr r3, [r7, #4]
8001542: 685b ldr r3, [r3, #4]
8001544: 2b00 cmp r3, #0
8001546: d157 bne.n 80015f8 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8001548: 2301 movs r3, #1
800154a: e242 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800154c: 687b ldr r3, [r7, #4]
800154e: 685b ldr r3, [r3, #4]
8001550: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8001554: d106 bne.n 8001564 <HAL_RCC_OscConfig+0x74>
8001556: 4b76 ldr r3, [pc, #472] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001558: 681b ldr r3, [r3, #0]
800155a: 4a75 ldr r2, [pc, #468] ; (8001730 <HAL_RCC_OscConfig+0x240>)
800155c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001560: 6013 str r3, [r2, #0]
8001562: e01d b.n 80015a0 <HAL_RCC_OscConfig+0xb0>
8001564: 687b ldr r3, [r7, #4]
8001566: 685b ldr r3, [r3, #4]
8001568: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
800156c: d10c bne.n 8001588 <HAL_RCC_OscConfig+0x98>
800156e: 4b70 ldr r3, [pc, #448] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001570: 681b ldr r3, [r3, #0]
8001572: 4a6f ldr r2, [pc, #444] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001574: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8001578: 6013 str r3, [r2, #0]
800157a: 4b6d ldr r3, [pc, #436] ; (8001730 <HAL_RCC_OscConfig+0x240>)
800157c: 681b ldr r3, [r3, #0]
800157e: 4a6c ldr r2, [pc, #432] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001580: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001584: 6013 str r3, [r2, #0]
8001586: e00b b.n 80015a0 <HAL_RCC_OscConfig+0xb0>
8001588: 4b69 ldr r3, [pc, #420] ; (8001730 <HAL_RCC_OscConfig+0x240>)
800158a: 681b ldr r3, [r3, #0]
800158c: 4a68 ldr r2, [pc, #416] ; (8001730 <HAL_RCC_OscConfig+0x240>)
800158e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8001592: 6013 str r3, [r2, #0]
8001594: 4b66 ldr r3, [pc, #408] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001596: 681b ldr r3, [r3, #0]
8001598: 4a65 ldr r2, [pc, #404] ; (8001730 <HAL_RCC_OscConfig+0x240>)
800159a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800159e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
80015a0: 687b ldr r3, [r7, #4]
80015a2: 685b ldr r3, [r3, #4]
80015a4: 2b00 cmp r3, #0
80015a6: d013 beq.n 80015d0 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80015a8: f7ff fcce bl 8000f48 <HAL_GetTick>
80015ac: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80015ae: e008 b.n 80015c2 <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80015b0: f7ff fcca bl 8000f48 <HAL_GetTick>
80015b4: 4602 mov r2, r0
80015b6: 693b ldr r3, [r7, #16]
80015b8: 1ad3 subs r3, r2, r3
80015ba: 2b64 cmp r3, #100 ; 0x64
80015bc: d901 bls.n 80015c2 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
80015be: 2303 movs r3, #3
80015c0: e207 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80015c2: 4b5b ldr r3, [pc, #364] ; (8001730 <HAL_RCC_OscConfig+0x240>)
80015c4: 681b ldr r3, [r3, #0]
80015c6: f403 3300 and.w r3, r3, #131072 ; 0x20000
80015ca: 2b00 cmp r3, #0
80015cc: d0f0 beq.n 80015b0 <HAL_RCC_OscConfig+0xc0>
80015ce: e014 b.n 80015fa <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80015d0: f7ff fcba bl 8000f48 <HAL_GetTick>
80015d4: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80015d6: e008 b.n 80015ea <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80015d8: f7ff fcb6 bl 8000f48 <HAL_GetTick>
80015dc: 4602 mov r2, r0
80015de: 693b ldr r3, [r7, #16]
80015e0: 1ad3 subs r3, r2, r3
80015e2: 2b64 cmp r3, #100 ; 0x64
80015e4: d901 bls.n 80015ea <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
80015e6: 2303 movs r3, #3
80015e8: e1f3 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80015ea: 4b51 ldr r3, [pc, #324] ; (8001730 <HAL_RCC_OscConfig+0x240>)
80015ec: 681b ldr r3, [r3, #0]
80015ee: f403 3300 and.w r3, r3, #131072 ; 0x20000
80015f2: 2b00 cmp r3, #0
80015f4: d1f0 bne.n 80015d8 <HAL_RCC_OscConfig+0xe8>
80015f6: e000 b.n 80015fa <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80015f8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80015fa: 687b ldr r3, [r7, #4]
80015fc: 681b ldr r3, [r3, #0]
80015fe: f003 0302 and.w r3, r3, #2
8001602: 2b00 cmp r3, #0
8001604: d063 beq.n 80016ce <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8001606: 4b4a ldr r3, [pc, #296] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001608: 689b ldr r3, [r3, #8]
800160a: f003 030c and.w r3, r3, #12
800160e: 2b00 cmp r3, #0
8001610: d00b beq.n 800162a <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8001612: 4b47 ldr r3, [pc, #284] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001614: 689b ldr r3, [r3, #8]
8001616: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
800161a: 2b08 cmp r3, #8
800161c: d11c bne.n 8001658 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
800161e: 4b44 ldr r3, [pc, #272] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001620: 685b ldr r3, [r3, #4]
8001622: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8001626: 2b00 cmp r3, #0
8001628: d116 bne.n 8001658 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800162a: 4b41 ldr r3, [pc, #260] ; (8001730 <HAL_RCC_OscConfig+0x240>)
800162c: 681b ldr r3, [r3, #0]
800162e: f003 0302 and.w r3, r3, #2
8001632: 2b00 cmp r3, #0
8001634: d005 beq.n 8001642 <HAL_RCC_OscConfig+0x152>
8001636: 687b ldr r3, [r7, #4]
8001638: 68db ldr r3, [r3, #12]
800163a: 2b01 cmp r3, #1
800163c: d001 beq.n 8001642 <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
800163e: 2301 movs r3, #1
8001640: e1c7 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001642: 4b3b ldr r3, [pc, #236] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001644: 681b ldr r3, [r3, #0]
8001646: f023 02f8 bic.w r2, r3, #248 ; 0xf8
800164a: 687b ldr r3, [r7, #4]
800164c: 691b ldr r3, [r3, #16]
800164e: 00db lsls r3, r3, #3
8001650: 4937 ldr r1, [pc, #220] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001652: 4313 orrs r3, r2
8001654: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001656: e03a b.n 80016ce <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
8001658: 687b ldr r3, [r7, #4]
800165a: 68db ldr r3, [r3, #12]
800165c: 2b00 cmp r3, #0
800165e: d020 beq.n 80016a2 <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001660: 4b34 ldr r3, [pc, #208] ; (8001734 <HAL_RCC_OscConfig+0x244>)
8001662: 2201 movs r2, #1
8001664: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001666: f7ff fc6f bl 8000f48 <HAL_GetTick>
800166a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800166c: e008 b.n 8001680 <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800166e: f7ff fc6b bl 8000f48 <HAL_GetTick>
8001672: 4602 mov r2, r0
8001674: 693b ldr r3, [r7, #16]
8001676: 1ad3 subs r3, r2, r3
8001678: 2b02 cmp r3, #2
800167a: d901 bls.n 8001680 <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
800167c: 2303 movs r3, #3
800167e: e1a8 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001680: 4b2b ldr r3, [pc, #172] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001682: 681b ldr r3, [r3, #0]
8001684: f003 0302 and.w r3, r3, #2
8001688: 2b00 cmp r3, #0
800168a: d0f0 beq.n 800166e <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800168c: 4b28 ldr r3, [pc, #160] ; (8001730 <HAL_RCC_OscConfig+0x240>)
800168e: 681b ldr r3, [r3, #0]
8001690: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8001694: 687b ldr r3, [r7, #4]
8001696: 691b ldr r3, [r3, #16]
8001698: 00db lsls r3, r3, #3
800169a: 4925 ldr r1, [pc, #148] ; (8001730 <HAL_RCC_OscConfig+0x240>)
800169c: 4313 orrs r3, r2
800169e: 600b str r3, [r1, #0]
80016a0: e015 b.n 80016ce <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80016a2: 4b24 ldr r3, [pc, #144] ; (8001734 <HAL_RCC_OscConfig+0x244>)
80016a4: 2200 movs r2, #0
80016a6: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80016a8: f7ff fc4e bl 8000f48 <HAL_GetTick>
80016ac: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80016ae: e008 b.n 80016c2 <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80016b0: f7ff fc4a bl 8000f48 <HAL_GetTick>
80016b4: 4602 mov r2, r0
80016b6: 693b ldr r3, [r7, #16]
80016b8: 1ad3 subs r3, r2, r3
80016ba: 2b02 cmp r3, #2
80016bc: d901 bls.n 80016c2 <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
80016be: 2303 movs r3, #3
80016c0: e187 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80016c2: 4b1b ldr r3, [pc, #108] ; (8001730 <HAL_RCC_OscConfig+0x240>)
80016c4: 681b ldr r3, [r3, #0]
80016c6: f003 0302 and.w r3, r3, #2
80016ca: 2b00 cmp r3, #0
80016cc: d1f0 bne.n 80016b0 <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80016ce: 687b ldr r3, [r7, #4]
80016d0: 681b ldr r3, [r3, #0]
80016d2: f003 0308 and.w r3, r3, #8
80016d6: 2b00 cmp r3, #0
80016d8: d036 beq.n 8001748 <HAL_RCC_OscConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
80016da: 687b ldr r3, [r7, #4]
80016dc: 695b ldr r3, [r3, #20]
80016de: 2b00 cmp r3, #0
80016e0: d016 beq.n 8001710 <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80016e2: 4b15 ldr r3, [pc, #84] ; (8001738 <HAL_RCC_OscConfig+0x248>)
80016e4: 2201 movs r2, #1
80016e6: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80016e8: f7ff fc2e bl 8000f48 <HAL_GetTick>
80016ec: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80016ee: e008 b.n 8001702 <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80016f0: f7ff fc2a bl 8000f48 <HAL_GetTick>
80016f4: 4602 mov r2, r0
80016f6: 693b ldr r3, [r7, #16]
80016f8: 1ad3 subs r3, r2, r3
80016fa: 2b02 cmp r3, #2
80016fc: d901 bls.n 8001702 <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
80016fe: 2303 movs r3, #3
8001700: e167 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001702: 4b0b ldr r3, [pc, #44] ; (8001730 <HAL_RCC_OscConfig+0x240>)
8001704: 6f5b ldr r3, [r3, #116] ; 0x74
8001706: f003 0302 and.w r3, r3, #2
800170a: 2b00 cmp r3, #0
800170c: d0f0 beq.n 80016f0 <HAL_RCC_OscConfig+0x200>
800170e: e01b b.n 8001748 <HAL_RCC_OscConfig+0x258>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001710: 4b09 ldr r3, [pc, #36] ; (8001738 <HAL_RCC_OscConfig+0x248>)
8001712: 2200 movs r2, #0
8001714: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001716: f7ff fc17 bl 8000f48 <HAL_GetTick>
800171a: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800171c: e00e b.n 800173c <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800171e: f7ff fc13 bl 8000f48 <HAL_GetTick>
8001722: 4602 mov r2, r0
8001724: 693b ldr r3, [r7, #16]
8001726: 1ad3 subs r3, r2, r3
8001728: 2b02 cmp r3, #2
800172a: d907 bls.n 800173c <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
800172c: 2303 movs r3, #3
800172e: e150 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
8001730: 40023800 .word 0x40023800
8001734: 42470000 .word 0x42470000
8001738: 42470e80 .word 0x42470e80
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800173c: 4b88 ldr r3, [pc, #544] ; (8001960 <HAL_RCC_OscConfig+0x470>)
800173e: 6f5b ldr r3, [r3, #116] ; 0x74
8001740: f003 0302 and.w r3, r3, #2
8001744: 2b00 cmp r3, #0
8001746: d1ea bne.n 800171e <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001748: 687b ldr r3, [r7, #4]
800174a: 681b ldr r3, [r3, #0]
800174c: f003 0304 and.w r3, r3, #4
8001750: 2b00 cmp r3, #0
8001752: f000 8097 beq.w 8001884 <HAL_RCC_OscConfig+0x394>
{
FlagStatus pwrclkchanged = RESET;
8001756: 2300 movs r3, #0
8001758: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800175a: 4b81 ldr r3, [pc, #516] ; (8001960 <HAL_RCC_OscConfig+0x470>)
800175c: 6c1b ldr r3, [r3, #64] ; 0x40
800175e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001762: 2b00 cmp r3, #0
8001764: d10f bne.n 8001786 <HAL_RCC_OscConfig+0x296>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001766: 2300 movs r3, #0
8001768: 60bb str r3, [r7, #8]
800176a: 4b7d ldr r3, [pc, #500] ; (8001960 <HAL_RCC_OscConfig+0x470>)
800176c: 6c1b ldr r3, [r3, #64] ; 0x40
800176e: 4a7c ldr r2, [pc, #496] ; (8001960 <HAL_RCC_OscConfig+0x470>)
8001770: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001774: 6413 str r3, [r2, #64] ; 0x40
8001776: 4b7a ldr r3, [pc, #488] ; (8001960 <HAL_RCC_OscConfig+0x470>)
8001778: 6c1b ldr r3, [r3, #64] ; 0x40
800177a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800177e: 60bb str r3, [r7, #8]
8001780: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001782: 2301 movs r3, #1
8001784: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001786: 4b77 ldr r3, [pc, #476] ; (8001964 <HAL_RCC_OscConfig+0x474>)
8001788: 681b ldr r3, [r3, #0]
800178a: f403 7380 and.w r3, r3, #256 ; 0x100
800178e: 2b00 cmp r3, #0
8001790: d118 bne.n 80017c4 <HAL_RCC_OscConfig+0x2d4>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001792: 4b74 ldr r3, [pc, #464] ; (8001964 <HAL_RCC_OscConfig+0x474>)
8001794: 681b ldr r3, [r3, #0]
8001796: 4a73 ldr r2, [pc, #460] ; (8001964 <HAL_RCC_OscConfig+0x474>)
8001798: f443 7380 orr.w r3, r3, #256 ; 0x100
800179c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800179e: f7ff fbd3 bl 8000f48 <HAL_GetTick>
80017a2: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80017a4: e008 b.n 80017b8 <HAL_RCC_OscConfig+0x2c8>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80017a6: f7ff fbcf bl 8000f48 <HAL_GetTick>
80017aa: 4602 mov r2, r0
80017ac: 693b ldr r3, [r7, #16]
80017ae: 1ad3 subs r3, r2, r3
80017b0: 2b02 cmp r3, #2
80017b2: d901 bls.n 80017b8 <HAL_RCC_OscConfig+0x2c8>
{
return HAL_TIMEOUT;
80017b4: 2303 movs r3, #3
80017b6: e10c b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80017b8: 4b6a ldr r3, [pc, #424] ; (8001964 <HAL_RCC_OscConfig+0x474>)
80017ba: 681b ldr r3, [r3, #0]
80017bc: f403 7380 and.w r3, r3, #256 ; 0x100
80017c0: 2b00 cmp r3, #0
80017c2: d0f0 beq.n 80017a6 <HAL_RCC_OscConfig+0x2b6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80017c4: 687b ldr r3, [r7, #4]
80017c6: 689b ldr r3, [r3, #8]
80017c8: 2b01 cmp r3, #1
80017ca: d106 bne.n 80017da <HAL_RCC_OscConfig+0x2ea>
80017cc: 4b64 ldr r3, [pc, #400] ; (8001960 <HAL_RCC_OscConfig+0x470>)
80017ce: 6f1b ldr r3, [r3, #112] ; 0x70
80017d0: 4a63 ldr r2, [pc, #396] ; (8001960 <HAL_RCC_OscConfig+0x470>)
80017d2: f043 0301 orr.w r3, r3, #1
80017d6: 6713 str r3, [r2, #112] ; 0x70
80017d8: e01c b.n 8001814 <HAL_RCC_OscConfig+0x324>
80017da: 687b ldr r3, [r7, #4]
80017dc: 689b ldr r3, [r3, #8]
80017de: 2b05 cmp r3, #5
80017e0: d10c bne.n 80017fc <HAL_RCC_OscConfig+0x30c>
80017e2: 4b5f ldr r3, [pc, #380] ; (8001960 <HAL_RCC_OscConfig+0x470>)
80017e4: 6f1b ldr r3, [r3, #112] ; 0x70
80017e6: 4a5e ldr r2, [pc, #376] ; (8001960 <HAL_RCC_OscConfig+0x470>)
80017e8: f043 0304 orr.w r3, r3, #4
80017ec: 6713 str r3, [r2, #112] ; 0x70
80017ee: 4b5c ldr r3, [pc, #368] ; (8001960 <HAL_RCC_OscConfig+0x470>)
80017f0: 6f1b ldr r3, [r3, #112] ; 0x70
80017f2: 4a5b ldr r2, [pc, #364] ; (8001960 <HAL_RCC_OscConfig+0x470>)
80017f4: f043 0301 orr.w r3, r3, #1
80017f8: 6713 str r3, [r2, #112] ; 0x70
80017fa: e00b b.n 8001814 <HAL_RCC_OscConfig+0x324>
80017fc: 4b58 ldr r3, [pc, #352] ; (8001960 <HAL_RCC_OscConfig+0x470>)
80017fe: 6f1b ldr r3, [r3, #112] ; 0x70
8001800: 4a57 ldr r2, [pc, #348] ; (8001960 <HAL_RCC_OscConfig+0x470>)
8001802: f023 0301 bic.w r3, r3, #1
8001806: 6713 str r3, [r2, #112] ; 0x70
8001808: 4b55 ldr r3, [pc, #340] ; (8001960 <HAL_RCC_OscConfig+0x470>)
800180a: 6f1b ldr r3, [r3, #112] ; 0x70
800180c: 4a54 ldr r2, [pc, #336] ; (8001960 <HAL_RCC_OscConfig+0x470>)
800180e: f023 0304 bic.w r3, r3, #4
8001812: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8001814: 687b ldr r3, [r7, #4]
8001816: 689b ldr r3, [r3, #8]
8001818: 2b00 cmp r3, #0
800181a: d015 beq.n 8001848 <HAL_RCC_OscConfig+0x358>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800181c: f7ff fb94 bl 8000f48 <HAL_GetTick>
8001820: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001822: e00a b.n 800183a <HAL_RCC_OscConfig+0x34a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001824: f7ff fb90 bl 8000f48 <HAL_GetTick>
8001828: 4602 mov r2, r0
800182a: 693b ldr r3, [r7, #16]
800182c: 1ad3 subs r3, r2, r3
800182e: f241 3288 movw r2, #5000 ; 0x1388
8001832: 4293 cmp r3, r2
8001834: d901 bls.n 800183a <HAL_RCC_OscConfig+0x34a>
{
return HAL_TIMEOUT;
8001836: 2303 movs r3, #3
8001838: e0cb b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800183a: 4b49 ldr r3, [pc, #292] ; (8001960 <HAL_RCC_OscConfig+0x470>)
800183c: 6f1b ldr r3, [r3, #112] ; 0x70
800183e: f003 0302 and.w r3, r3, #2
8001842: 2b00 cmp r3, #0
8001844: d0ee beq.n 8001824 <HAL_RCC_OscConfig+0x334>
8001846: e014 b.n 8001872 <HAL_RCC_OscConfig+0x382>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001848: f7ff fb7e bl 8000f48 <HAL_GetTick>
800184c: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800184e: e00a b.n 8001866 <HAL_RCC_OscConfig+0x376>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001850: f7ff fb7a bl 8000f48 <HAL_GetTick>
8001854: 4602 mov r2, r0
8001856: 693b ldr r3, [r7, #16]
8001858: 1ad3 subs r3, r2, r3
800185a: f241 3288 movw r2, #5000 ; 0x1388
800185e: 4293 cmp r3, r2
8001860: d901 bls.n 8001866 <HAL_RCC_OscConfig+0x376>
{
return HAL_TIMEOUT;
8001862: 2303 movs r3, #3
8001864: e0b5 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001866: 4b3e ldr r3, [pc, #248] ; (8001960 <HAL_RCC_OscConfig+0x470>)
8001868: 6f1b ldr r3, [r3, #112] ; 0x70
800186a: f003 0302 and.w r3, r3, #2
800186e: 2b00 cmp r3, #0
8001870: d1ee bne.n 8001850 <HAL_RCC_OscConfig+0x360>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8001872: 7dfb ldrb r3, [r7, #23]
8001874: 2b01 cmp r3, #1
8001876: d105 bne.n 8001884 <HAL_RCC_OscConfig+0x394>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001878: 4b39 ldr r3, [pc, #228] ; (8001960 <HAL_RCC_OscConfig+0x470>)
800187a: 6c1b ldr r3, [r3, #64] ; 0x40
800187c: 4a38 ldr r2, [pc, #224] ; (8001960 <HAL_RCC_OscConfig+0x470>)
800187e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8001882: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001884: 687b ldr r3, [r7, #4]
8001886: 699b ldr r3, [r3, #24]
8001888: 2b00 cmp r3, #0
800188a: f000 80a1 beq.w 80019d0 <HAL_RCC_OscConfig+0x4e0>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
800188e: 4b34 ldr r3, [pc, #208] ; (8001960 <HAL_RCC_OscConfig+0x470>)
8001890: 689b ldr r3, [r3, #8]
8001892: f003 030c and.w r3, r3, #12
8001896: 2b08 cmp r3, #8
8001898: d05c beq.n 8001954 <HAL_RCC_OscConfig+0x464>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
800189a: 687b ldr r3, [r7, #4]
800189c: 699b ldr r3, [r3, #24]
800189e: 2b02 cmp r3, #2
80018a0: d141 bne.n 8001926 <HAL_RCC_OscConfig+0x436>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80018a2: 4b31 ldr r3, [pc, #196] ; (8001968 <HAL_RCC_OscConfig+0x478>)
80018a4: 2200 movs r2, #0
80018a6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80018a8: f7ff fb4e bl 8000f48 <HAL_GetTick>
80018ac: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80018ae: e008 b.n 80018c2 <HAL_RCC_OscConfig+0x3d2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80018b0: f7ff fb4a bl 8000f48 <HAL_GetTick>
80018b4: 4602 mov r2, r0
80018b6: 693b ldr r3, [r7, #16]
80018b8: 1ad3 subs r3, r2, r3
80018ba: 2b02 cmp r3, #2
80018bc: d901 bls.n 80018c2 <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
80018be: 2303 movs r3, #3
80018c0: e087 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80018c2: 4b27 ldr r3, [pc, #156] ; (8001960 <HAL_RCC_OscConfig+0x470>)
80018c4: 681b ldr r3, [r3, #0]
80018c6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80018ca: 2b00 cmp r3, #0
80018cc: d1f0 bne.n 80018b0 <HAL_RCC_OscConfig+0x3c0>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
80018ce: 687b ldr r3, [r7, #4]
80018d0: 69da ldr r2, [r3, #28]
80018d2: 687b ldr r3, [r7, #4]
80018d4: 6a1b ldr r3, [r3, #32]
80018d6: 431a orrs r2, r3
80018d8: 687b ldr r3, [r7, #4]
80018da: 6a5b ldr r3, [r3, #36] ; 0x24
80018dc: 019b lsls r3, r3, #6
80018de: 431a orrs r2, r3
80018e0: 687b ldr r3, [r7, #4]
80018e2: 6a9b ldr r3, [r3, #40] ; 0x28
80018e4: 085b lsrs r3, r3, #1
80018e6: 3b01 subs r3, #1
80018e8: 041b lsls r3, r3, #16
80018ea: 431a orrs r2, r3
80018ec: 687b ldr r3, [r7, #4]
80018ee: 6adb ldr r3, [r3, #44] ; 0x2c
80018f0: 061b lsls r3, r3, #24
80018f2: 491b ldr r1, [pc, #108] ; (8001960 <HAL_RCC_OscConfig+0x470>)
80018f4: 4313 orrs r3, r2
80018f6: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80018f8: 4b1b ldr r3, [pc, #108] ; (8001968 <HAL_RCC_OscConfig+0x478>)
80018fa: 2201 movs r2, #1
80018fc: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80018fe: f7ff fb23 bl 8000f48 <HAL_GetTick>
8001902: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001904: e008 b.n 8001918 <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001906: f7ff fb1f bl 8000f48 <HAL_GetTick>
800190a: 4602 mov r2, r0
800190c: 693b ldr r3, [r7, #16]
800190e: 1ad3 subs r3, r2, r3
8001910: 2b02 cmp r3, #2
8001912: d901 bls.n 8001918 <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
8001914: 2303 movs r3, #3
8001916: e05c b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001918: 4b11 ldr r3, [pc, #68] ; (8001960 <HAL_RCC_OscConfig+0x470>)
800191a: 681b ldr r3, [r3, #0]
800191c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001920: 2b00 cmp r3, #0
8001922: d0f0 beq.n 8001906 <HAL_RCC_OscConfig+0x416>
8001924: e054 b.n 80019d0 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001926: 4b10 ldr r3, [pc, #64] ; (8001968 <HAL_RCC_OscConfig+0x478>)
8001928: 2200 movs r2, #0
800192a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800192c: f7ff fb0c bl 8000f48 <HAL_GetTick>
8001930: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001932: e008 b.n 8001946 <HAL_RCC_OscConfig+0x456>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001934: f7ff fb08 bl 8000f48 <HAL_GetTick>
8001938: 4602 mov r2, r0
800193a: 693b ldr r3, [r7, #16]
800193c: 1ad3 subs r3, r2, r3
800193e: 2b02 cmp r3, #2
8001940: d901 bls.n 8001946 <HAL_RCC_OscConfig+0x456>
{
return HAL_TIMEOUT;
8001942: 2303 movs r3, #3
8001944: e045 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001946: 4b06 ldr r3, [pc, #24] ; (8001960 <HAL_RCC_OscConfig+0x470>)
8001948: 681b ldr r3, [r3, #0]
800194a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800194e: 2b00 cmp r3, #0
8001950: d1f0 bne.n 8001934 <HAL_RCC_OscConfig+0x444>
8001952: e03d b.n 80019d0 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001954: 687b ldr r3, [r7, #4]
8001956: 699b ldr r3, [r3, #24]
8001958: 2b01 cmp r3, #1
800195a: d107 bne.n 800196c <HAL_RCC_OscConfig+0x47c>
{
return HAL_ERROR;
800195c: 2301 movs r3, #1
800195e: e038 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
8001960: 40023800 .word 0x40023800
8001964: 40007000 .word 0x40007000
8001968: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
800196c: 4b1b ldr r3, [pc, #108] ; (80019dc <HAL_RCC_OscConfig+0x4ec>)
800196e: 685b ldr r3, [r3, #4]
8001970: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001972: 687b ldr r3, [r7, #4]
8001974: 699b ldr r3, [r3, #24]
8001976: 2b01 cmp r3, #1
8001978: d028 beq.n 80019cc <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800197a: 68fb ldr r3, [r7, #12]
800197c: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8001980: 687b ldr r3, [r7, #4]
8001982: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001984: 429a cmp r2, r3
8001986: d121 bne.n 80019cc <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001988: 68fb ldr r3, [r7, #12]
800198a: f003 023f and.w r2, r3, #63 ; 0x3f
800198e: 687b ldr r3, [r7, #4]
8001990: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001992: 429a cmp r2, r3
8001994: d11a bne.n 80019cc <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8001996: 68fa ldr r2, [r7, #12]
8001998: f647 73c0 movw r3, #32704 ; 0x7fc0
800199c: 4013 ands r3, r2
800199e: 687a ldr r2, [r7, #4]
80019a0: 6a52 ldr r2, [r2, #36] ; 0x24
80019a2: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
80019a4: 4293 cmp r3, r2
80019a6: d111 bne.n 80019cc <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
80019a8: 68fb ldr r3, [r7, #12]
80019aa: f403 3240 and.w r2, r3, #196608 ; 0x30000
80019ae: 687b ldr r3, [r7, #4]
80019b0: 6a9b ldr r3, [r3, #40] ; 0x28
80019b2: 085b lsrs r3, r3, #1
80019b4: 3b01 subs r3, #1
80019b6: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
80019b8: 429a cmp r2, r3
80019ba: d107 bne.n 80019cc <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
80019bc: 68fb ldr r3, [r7, #12]
80019be: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
80019c2: 687b ldr r3, [r7, #4]
80019c4: 6adb ldr r3, [r3, #44] ; 0x2c
80019c6: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
80019c8: 429a cmp r2, r3
80019ca: d001 beq.n 80019d0 <HAL_RCC_OscConfig+0x4e0>
#endif
{
return HAL_ERROR;
80019cc: 2301 movs r3, #1
80019ce: e000 b.n 80019d2 <HAL_RCC_OscConfig+0x4e2>
}
}
}
}
return HAL_OK;
80019d0: 2300 movs r3, #0
}
80019d2: 4618 mov r0, r3
80019d4: 3718 adds r7, #24
80019d6: 46bd mov sp, r7
80019d8: bd80 pop {r7, pc}
80019da: bf00 nop
80019dc: 40023800 .word 0x40023800
080019e0 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80019e0: b580 push {r7, lr}
80019e2: b084 sub sp, #16
80019e4: af00 add r7, sp, #0
80019e6: 6078 str r0, [r7, #4]
80019e8: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
80019ea: 687b ldr r3, [r7, #4]
80019ec: 2b00 cmp r3, #0
80019ee: d101 bne.n 80019f4 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80019f0: 2301 movs r3, #1
80019f2: e0cc b.n 8001b8e <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80019f4: 4b68 ldr r3, [pc, #416] ; (8001b98 <HAL_RCC_ClockConfig+0x1b8>)
80019f6: 681b ldr r3, [r3, #0]
80019f8: f003 0307 and.w r3, r3, #7
80019fc: 683a ldr r2, [r7, #0]
80019fe: 429a cmp r2, r3
8001a00: d90c bls.n 8001a1c <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001a02: 4b65 ldr r3, [pc, #404] ; (8001b98 <HAL_RCC_ClockConfig+0x1b8>)
8001a04: 683a ldr r2, [r7, #0]
8001a06: b2d2 uxtb r2, r2
8001a08: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001a0a: 4b63 ldr r3, [pc, #396] ; (8001b98 <HAL_RCC_ClockConfig+0x1b8>)
8001a0c: 681b ldr r3, [r3, #0]
8001a0e: f003 0307 and.w r3, r3, #7
8001a12: 683a ldr r2, [r7, #0]
8001a14: 429a cmp r2, r3
8001a16: d001 beq.n 8001a1c <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
8001a18: 2301 movs r3, #1
8001a1a: e0b8 b.n 8001b8e <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001a1c: 687b ldr r3, [r7, #4]
8001a1e: 681b ldr r3, [r3, #0]
8001a20: f003 0302 and.w r3, r3, #2
8001a24: 2b00 cmp r3, #0
8001a26: d020 beq.n 8001a6a <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001a28: 687b ldr r3, [r7, #4]
8001a2a: 681b ldr r3, [r3, #0]
8001a2c: f003 0304 and.w r3, r3, #4
8001a30: 2b00 cmp r3, #0
8001a32: d005 beq.n 8001a40 <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8001a34: 4b59 ldr r3, [pc, #356] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001a36: 689b ldr r3, [r3, #8]
8001a38: 4a58 ldr r2, [pc, #352] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001a3a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
8001a3e: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001a40: 687b ldr r3, [r7, #4]
8001a42: 681b ldr r3, [r3, #0]
8001a44: f003 0308 and.w r3, r3, #8
8001a48: 2b00 cmp r3, #0
8001a4a: d005 beq.n 8001a58 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8001a4c: 4b53 ldr r3, [pc, #332] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001a4e: 689b ldr r3, [r3, #8]
8001a50: 4a52 ldr r2, [pc, #328] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001a52: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8001a56: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001a58: 4b50 ldr r3, [pc, #320] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001a5a: 689b ldr r3, [r3, #8]
8001a5c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8001a60: 687b ldr r3, [r7, #4]
8001a62: 689b ldr r3, [r3, #8]
8001a64: 494d ldr r1, [pc, #308] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001a66: 4313 orrs r3, r2
8001a68: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001a6a: 687b ldr r3, [r7, #4]
8001a6c: 681b ldr r3, [r3, #0]
8001a6e: f003 0301 and.w r3, r3, #1
8001a72: 2b00 cmp r3, #0
8001a74: d044 beq.n 8001b00 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001a76: 687b ldr r3, [r7, #4]
8001a78: 685b ldr r3, [r3, #4]
8001a7a: 2b01 cmp r3, #1
8001a7c: d107 bne.n 8001a8e <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001a7e: 4b47 ldr r3, [pc, #284] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001a80: 681b ldr r3, [r3, #0]
8001a82: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001a86: 2b00 cmp r3, #0
8001a88: d119 bne.n 8001abe <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001a8a: 2301 movs r3, #1
8001a8c: e07f b.n 8001b8e <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8001a8e: 687b ldr r3, [r7, #4]
8001a90: 685b ldr r3, [r3, #4]
8001a92: 2b02 cmp r3, #2
8001a94: d003 beq.n 8001a9e <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
8001a96: 687b ldr r3, [r7, #4]
8001a98: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8001a9a: 2b03 cmp r3, #3
8001a9c: d107 bne.n 8001aae <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001a9e: 4b3f ldr r3, [pc, #252] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001aa0: 681b ldr r3, [r3, #0]
8001aa2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001aa6: 2b00 cmp r3, #0
8001aa8: d109 bne.n 8001abe <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001aaa: 2301 movs r3, #1
8001aac: e06f b.n 8001b8e <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001aae: 4b3b ldr r3, [pc, #236] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001ab0: 681b ldr r3, [r3, #0]
8001ab2: f003 0302 and.w r3, r3, #2
8001ab6: 2b00 cmp r3, #0
8001ab8: d101 bne.n 8001abe <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001aba: 2301 movs r3, #1
8001abc: e067 b.n 8001b8e <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8001abe: 4b37 ldr r3, [pc, #220] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001ac0: 689b ldr r3, [r3, #8]
8001ac2: f023 0203 bic.w r2, r3, #3
8001ac6: 687b ldr r3, [r7, #4]
8001ac8: 685b ldr r3, [r3, #4]
8001aca: 4934 ldr r1, [pc, #208] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001acc: 4313 orrs r3, r2
8001ace: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001ad0: f7ff fa3a bl 8000f48 <HAL_GetTick>
8001ad4: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001ad6: e00a b.n 8001aee <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001ad8: f7ff fa36 bl 8000f48 <HAL_GetTick>
8001adc: 4602 mov r2, r0
8001ade: 68fb ldr r3, [r7, #12]
8001ae0: 1ad3 subs r3, r2, r3
8001ae2: f241 3288 movw r2, #5000 ; 0x1388
8001ae6: 4293 cmp r3, r2
8001ae8: d901 bls.n 8001aee <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8001aea: 2303 movs r3, #3
8001aec: e04f b.n 8001b8e <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001aee: 4b2b ldr r3, [pc, #172] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001af0: 689b ldr r3, [r3, #8]
8001af2: f003 020c and.w r2, r3, #12
8001af6: 687b ldr r3, [r7, #4]
8001af8: 685b ldr r3, [r3, #4]
8001afa: 009b lsls r3, r3, #2
8001afc: 429a cmp r2, r3
8001afe: d1eb bne.n 8001ad8 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001b00: 4b25 ldr r3, [pc, #148] ; (8001b98 <HAL_RCC_ClockConfig+0x1b8>)
8001b02: 681b ldr r3, [r3, #0]
8001b04: f003 0307 and.w r3, r3, #7
8001b08: 683a ldr r2, [r7, #0]
8001b0a: 429a cmp r2, r3
8001b0c: d20c bcs.n 8001b28 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001b0e: 4b22 ldr r3, [pc, #136] ; (8001b98 <HAL_RCC_ClockConfig+0x1b8>)
8001b10: 683a ldr r2, [r7, #0]
8001b12: b2d2 uxtb r2, r2
8001b14: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001b16: 4b20 ldr r3, [pc, #128] ; (8001b98 <HAL_RCC_ClockConfig+0x1b8>)
8001b18: 681b ldr r3, [r3, #0]
8001b1a: f003 0307 and.w r3, r3, #7
8001b1e: 683a ldr r2, [r7, #0]
8001b20: 429a cmp r2, r3
8001b22: d001 beq.n 8001b28 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
8001b24: 2301 movs r3, #1
8001b26: e032 b.n 8001b8e <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001b28: 687b ldr r3, [r7, #4]
8001b2a: 681b ldr r3, [r3, #0]
8001b2c: f003 0304 and.w r3, r3, #4
8001b30: 2b00 cmp r3, #0
8001b32: d008 beq.n 8001b46 <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001b34: 4b19 ldr r3, [pc, #100] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001b36: 689b ldr r3, [r3, #8]
8001b38: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
8001b3c: 687b ldr r3, [r7, #4]
8001b3e: 68db ldr r3, [r3, #12]
8001b40: 4916 ldr r1, [pc, #88] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001b42: 4313 orrs r3, r2
8001b44: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001b46: 687b ldr r3, [r7, #4]
8001b48: 681b ldr r3, [r3, #0]
8001b4a: f003 0308 and.w r3, r3, #8
8001b4e: 2b00 cmp r3, #0
8001b50: d009 beq.n 8001b66 <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8001b52: 4b12 ldr r3, [pc, #72] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001b54: 689b ldr r3, [r3, #8]
8001b56: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8001b5a: 687b ldr r3, [r7, #4]
8001b5c: 691b ldr r3, [r3, #16]
8001b5e: 00db lsls r3, r3, #3
8001b60: 490e ldr r1, [pc, #56] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001b62: 4313 orrs r3, r2
8001b64: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8001b66: f000 f821 bl 8001bac <HAL_RCC_GetSysClockFreq>
8001b6a: 4602 mov r2, r0
8001b6c: 4b0b ldr r3, [pc, #44] ; (8001b9c <HAL_RCC_ClockConfig+0x1bc>)
8001b6e: 689b ldr r3, [r3, #8]
8001b70: 091b lsrs r3, r3, #4
8001b72: f003 030f and.w r3, r3, #15
8001b76: 490a ldr r1, [pc, #40] ; (8001ba0 <HAL_RCC_ClockConfig+0x1c0>)
8001b78: 5ccb ldrb r3, [r1, r3]
8001b7a: fa22 f303 lsr.w r3, r2, r3
8001b7e: 4a09 ldr r2, [pc, #36] ; (8001ba4 <HAL_RCC_ClockConfig+0x1c4>)
8001b80: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
8001b82: 4b09 ldr r3, [pc, #36] ; (8001ba8 <HAL_RCC_ClockConfig+0x1c8>)
8001b84: 681b ldr r3, [r3, #0]
8001b86: 4618 mov r0, r3
8001b88: f7ff f99a bl 8000ec0 <HAL_InitTick>
return HAL_OK;
8001b8c: 2300 movs r3, #0
}
8001b8e: 4618 mov r0, r3
8001b90: 3710 adds r7, #16
8001b92: 46bd mov sp, r7
8001b94: bd80 pop {r7, pc}
8001b96: bf00 nop
8001b98: 40023c00 .word 0x40023c00
8001b9c: 40023800 .word 0x40023800
8001ba0: 080039f8 .word 0x080039f8
8001ba4: 20000004 .word 0x20000004
8001ba8: 20000008 .word 0x20000008
08001bac <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001bac: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001bb0: b090 sub sp, #64 ; 0x40
8001bb2: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
8001bb4: 2300 movs r3, #0
8001bb6: 637b str r3, [r7, #52] ; 0x34
8001bb8: 2300 movs r3, #0
8001bba: 63fb str r3, [r7, #60] ; 0x3c
8001bbc: 2300 movs r3, #0
8001bbe: 633b str r3, [r7, #48] ; 0x30
uint32_t sysclockfreq = 0U;
8001bc0: 2300 movs r3, #0
8001bc2: 63bb str r3, [r7, #56] ; 0x38
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8001bc4: 4b59 ldr r3, [pc, #356] ; (8001d2c <HAL_RCC_GetSysClockFreq+0x180>)
8001bc6: 689b ldr r3, [r3, #8]
8001bc8: f003 030c and.w r3, r3, #12
8001bcc: 2b08 cmp r3, #8
8001bce: d00d beq.n 8001bec <HAL_RCC_GetSysClockFreq+0x40>
8001bd0: 2b08 cmp r3, #8
8001bd2: f200 80a1 bhi.w 8001d18 <HAL_RCC_GetSysClockFreq+0x16c>
8001bd6: 2b00 cmp r3, #0
8001bd8: d002 beq.n 8001be0 <HAL_RCC_GetSysClockFreq+0x34>
8001bda: 2b04 cmp r3, #4
8001bdc: d003 beq.n 8001be6 <HAL_RCC_GetSysClockFreq+0x3a>
8001bde: e09b b.n 8001d18 <HAL_RCC_GetSysClockFreq+0x16c>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8001be0: 4b53 ldr r3, [pc, #332] ; (8001d30 <HAL_RCC_GetSysClockFreq+0x184>)
8001be2: 63bb str r3, [r7, #56] ; 0x38
break;
8001be4: e09b b.n 8001d1e <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8001be6: 4b53 ldr r3, [pc, #332] ; (8001d34 <HAL_RCC_GetSysClockFreq+0x188>)
8001be8: 63bb str r3, [r7, #56] ; 0x38
break;
8001bea: e098 b.n 8001d1e <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8001bec: 4b4f ldr r3, [pc, #316] ; (8001d2c <HAL_RCC_GetSysClockFreq+0x180>)
8001bee: 685b ldr r3, [r3, #4]
8001bf0: f003 033f and.w r3, r3, #63 ; 0x3f
8001bf4: 637b str r3, [r7, #52] ; 0x34
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8001bf6: 4b4d ldr r3, [pc, #308] ; (8001d2c <HAL_RCC_GetSysClockFreq+0x180>)
8001bf8: 685b ldr r3, [r3, #4]
8001bfa: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8001bfe: 2b00 cmp r3, #0
8001c00: d028 beq.n 8001c54 <HAL_RCC_GetSysClockFreq+0xa8>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8001c02: 4b4a ldr r3, [pc, #296] ; (8001d2c <HAL_RCC_GetSysClockFreq+0x180>)
8001c04: 685b ldr r3, [r3, #4]
8001c06: 099b lsrs r3, r3, #6
8001c08: 2200 movs r2, #0
8001c0a: 623b str r3, [r7, #32]
8001c0c: 627a str r2, [r7, #36] ; 0x24
8001c0e: 6a3b ldr r3, [r7, #32]
8001c10: f3c3 0008 ubfx r0, r3, #0, #9
8001c14: 2100 movs r1, #0
8001c16: 4b47 ldr r3, [pc, #284] ; (8001d34 <HAL_RCC_GetSysClockFreq+0x188>)
8001c18: fb03 f201 mul.w r2, r3, r1
8001c1c: 2300 movs r3, #0
8001c1e: fb00 f303 mul.w r3, r0, r3
8001c22: 4413 add r3, r2
8001c24: 4a43 ldr r2, [pc, #268] ; (8001d34 <HAL_RCC_GetSysClockFreq+0x188>)
8001c26: fba0 1202 umull r1, r2, r0, r2
8001c2a: 62fa str r2, [r7, #44] ; 0x2c
8001c2c: 460a mov r2, r1
8001c2e: 62ba str r2, [r7, #40] ; 0x28
8001c30: 6afa ldr r2, [r7, #44] ; 0x2c
8001c32: 4413 add r3, r2
8001c34: 62fb str r3, [r7, #44] ; 0x2c
8001c36: 6b7b ldr r3, [r7, #52] ; 0x34
8001c38: 2200 movs r2, #0
8001c3a: 61bb str r3, [r7, #24]
8001c3c: 61fa str r2, [r7, #28]
8001c3e: e9d7 2306 ldrd r2, r3, [r7, #24]
8001c42: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28
8001c46: f7fe fabf bl 80001c8 <__aeabi_uldivmod>
8001c4a: 4602 mov r2, r0
8001c4c: 460b mov r3, r1
8001c4e: 4613 mov r3, r2
8001c50: 63fb str r3, [r7, #60] ; 0x3c
8001c52: e053 b.n 8001cfc <HAL_RCC_GetSysClockFreq+0x150>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8001c54: 4b35 ldr r3, [pc, #212] ; (8001d2c <HAL_RCC_GetSysClockFreq+0x180>)
8001c56: 685b ldr r3, [r3, #4]
8001c58: 099b lsrs r3, r3, #6
8001c5a: 2200 movs r2, #0
8001c5c: 613b str r3, [r7, #16]
8001c5e: 617a str r2, [r7, #20]
8001c60: 693b ldr r3, [r7, #16]
8001c62: f3c3 0a08 ubfx sl, r3, #0, #9
8001c66: f04f 0b00 mov.w fp, #0
8001c6a: 4652 mov r2, sl
8001c6c: 465b mov r3, fp
8001c6e: f04f 0000 mov.w r0, #0
8001c72: f04f 0100 mov.w r1, #0
8001c76: 0159 lsls r1, r3, #5
8001c78: ea41 61d2 orr.w r1, r1, r2, lsr #27
8001c7c: 0150 lsls r0, r2, #5
8001c7e: 4602 mov r2, r0
8001c80: 460b mov r3, r1
8001c82: ebb2 080a subs.w r8, r2, sl
8001c86: eb63 090b sbc.w r9, r3, fp
8001c8a: f04f 0200 mov.w r2, #0
8001c8e: f04f 0300 mov.w r3, #0
8001c92: ea4f 1389 mov.w r3, r9, lsl #6
8001c96: ea43 6398 orr.w r3, r3, r8, lsr #26
8001c9a: ea4f 1288 mov.w r2, r8, lsl #6
8001c9e: ebb2 0408 subs.w r4, r2, r8
8001ca2: eb63 0509 sbc.w r5, r3, r9
8001ca6: f04f 0200 mov.w r2, #0
8001caa: f04f 0300 mov.w r3, #0
8001cae: 00eb lsls r3, r5, #3
8001cb0: ea43 7354 orr.w r3, r3, r4, lsr #29
8001cb4: 00e2 lsls r2, r4, #3
8001cb6: 4614 mov r4, r2
8001cb8: 461d mov r5, r3
8001cba: eb14 030a adds.w r3, r4, sl
8001cbe: 603b str r3, [r7, #0]
8001cc0: eb45 030b adc.w r3, r5, fp
8001cc4: 607b str r3, [r7, #4]
8001cc6: f04f 0200 mov.w r2, #0
8001cca: f04f 0300 mov.w r3, #0
8001cce: e9d7 4500 ldrd r4, r5, [r7]
8001cd2: 4629 mov r1, r5
8001cd4: 028b lsls r3, r1, #10
8001cd6: 4621 mov r1, r4
8001cd8: ea43 5391 orr.w r3, r3, r1, lsr #22
8001cdc: 4621 mov r1, r4
8001cde: 028a lsls r2, r1, #10
8001ce0: 4610 mov r0, r2
8001ce2: 4619 mov r1, r3
8001ce4: 6b7b ldr r3, [r7, #52] ; 0x34
8001ce6: 2200 movs r2, #0
8001ce8: 60bb str r3, [r7, #8]
8001cea: 60fa str r2, [r7, #12]
8001cec: e9d7 2302 ldrd r2, r3, [r7, #8]
8001cf0: f7fe fa6a bl 80001c8 <__aeabi_uldivmod>
8001cf4: 4602 mov r2, r0
8001cf6: 460b mov r3, r1
8001cf8: 4613 mov r3, r2
8001cfa: 63fb str r3, [r7, #60] ; 0x3c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
8001cfc: 4b0b ldr r3, [pc, #44] ; (8001d2c <HAL_RCC_GetSysClockFreq+0x180>)
8001cfe: 685b ldr r3, [r3, #4]
8001d00: 0c1b lsrs r3, r3, #16
8001d02: f003 0303 and.w r3, r3, #3
8001d06: 3301 adds r3, #1
8001d08: 005b lsls r3, r3, #1
8001d0a: 633b str r3, [r7, #48] ; 0x30
sysclockfreq = pllvco/pllp;
8001d0c: 6bfa ldr r2, [r7, #60] ; 0x3c
8001d0e: 6b3b ldr r3, [r7, #48] ; 0x30
8001d10: fbb2 f3f3 udiv r3, r2, r3
8001d14: 63bb str r3, [r7, #56] ; 0x38
break;
8001d16: e002 b.n 8001d1e <HAL_RCC_GetSysClockFreq+0x172>
}
default:
{
sysclockfreq = HSI_VALUE;
8001d18: 4b05 ldr r3, [pc, #20] ; (8001d30 <HAL_RCC_GetSysClockFreq+0x184>)
8001d1a: 63bb str r3, [r7, #56] ; 0x38
break;
8001d1c: bf00 nop
}
}
return sysclockfreq;
8001d1e: 6bbb ldr r3, [r7, #56] ; 0x38
}
8001d20: 4618 mov r0, r3
8001d22: 3740 adds r7, #64 ; 0x40
8001d24: 46bd mov sp, r7
8001d26: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8001d2a: bf00 nop
8001d2c: 40023800 .word 0x40023800
8001d30: 00f42400 .word 0x00f42400
8001d34: 016e3600 .word 0x016e3600
08001d38 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8001d38: b580 push {r7, lr}
8001d3a: b082 sub sp, #8
8001d3c: af00 add r7, sp, #0
8001d3e: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
8001d40: 687b ldr r3, [r7, #4]
8001d42: 2b00 cmp r3, #0
8001d44: d101 bne.n 8001d4a <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8001d46: 2301 movs r3, #1
8001d48: e07b b.n 8001e42 <HAL_SPI_Init+0x10a>
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
8001d4a: 687b ldr r3, [r7, #4]
8001d4c: 6a5b ldr r3, [r3, #36] ; 0x24
8001d4e: 2b00 cmp r3, #0
8001d50: d108 bne.n 8001d64 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
8001d52: 687b ldr r3, [r7, #4]
8001d54: 685b ldr r3, [r3, #4]
8001d56: f5b3 7f82 cmp.w r3, #260 ; 0x104
8001d5a: d009 beq.n 8001d70 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8001d5c: 687b ldr r3, [r7, #4]
8001d5e: 2200 movs r2, #0
8001d60: 61da str r2, [r3, #28]
8001d62: e005 b.n 8001d70 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
8001d64: 687b ldr r3, [r7, #4]
8001d66: 2200 movs r2, #0
8001d68: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8001d6a: 687b ldr r3, [r7, #4]
8001d6c: 2200 movs r2, #0
8001d6e: 615a str r2, [r3, #20]
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8001d70: 687b ldr r3, [r7, #4]
8001d72: 2200 movs r2, #0
8001d74: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
8001d76: 687b ldr r3, [r7, #4]
8001d78: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
8001d7c: b2db uxtb r3, r3
8001d7e: 2b00 cmp r3, #0
8001d80: d106 bne.n 8001d90 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8001d82: 687b ldr r3, [r7, #4]
8001d84: 2200 movs r2, #0
8001d86: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8001d8a: 6878 ldr r0, [r7, #4]
8001d8c: f7fe fec6 bl 8000b1c <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8001d90: 687b ldr r3, [r7, #4]
8001d92: 2202 movs r2, #2
8001d94: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8001d98: 687b ldr r3, [r7, #4]
8001d9a: 681b ldr r3, [r3, #0]
8001d9c: 681a ldr r2, [r3, #0]
8001d9e: 687b ldr r3, [r7, #4]
8001da0: 681b ldr r3, [r3, #0]
8001da2: f022 0240 bic.w r2, r2, #64 ; 0x40
8001da6: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
8001da8: 687b ldr r3, [r7, #4]
8001daa: 685b ldr r3, [r3, #4]
8001dac: f403 7282 and.w r2, r3, #260 ; 0x104
8001db0: 687b ldr r3, [r7, #4]
8001db2: 689b ldr r3, [r3, #8]
8001db4: f403 4304 and.w r3, r3, #33792 ; 0x8400
8001db8: 431a orrs r2, r3
8001dba: 687b ldr r3, [r7, #4]
8001dbc: 68db ldr r3, [r3, #12]
8001dbe: f403 6300 and.w r3, r3, #2048 ; 0x800
8001dc2: 431a orrs r2, r3
8001dc4: 687b ldr r3, [r7, #4]
8001dc6: 691b ldr r3, [r3, #16]
8001dc8: f003 0302 and.w r3, r3, #2
8001dcc: 431a orrs r2, r3
8001dce: 687b ldr r3, [r7, #4]
8001dd0: 695b ldr r3, [r3, #20]
8001dd2: f003 0301 and.w r3, r3, #1
8001dd6: 431a orrs r2, r3
8001dd8: 687b ldr r3, [r7, #4]
8001dda: 699b ldr r3, [r3, #24]
8001ddc: f403 7300 and.w r3, r3, #512 ; 0x200
8001de0: 431a orrs r2, r3
8001de2: 687b ldr r3, [r7, #4]
8001de4: 69db ldr r3, [r3, #28]
8001de6: f003 0338 and.w r3, r3, #56 ; 0x38
8001dea: 431a orrs r2, r3
8001dec: 687b ldr r3, [r7, #4]
8001dee: 6a1b ldr r3, [r3, #32]
8001df0: f003 0380 and.w r3, r3, #128 ; 0x80
8001df4: ea42 0103 orr.w r1, r2, r3
8001df8: 687b ldr r3, [r7, #4]
8001dfa: 6a9b ldr r3, [r3, #40] ; 0x28
8001dfc: f403 5200 and.w r2, r3, #8192 ; 0x2000
8001e00: 687b ldr r3, [r7, #4]
8001e02: 681b ldr r3, [r3, #0]
8001e04: 430a orrs r2, r1
8001e06: 601a str r2, [r3, #0]
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
/* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
8001e08: 687b ldr r3, [r7, #4]
8001e0a: 699b ldr r3, [r3, #24]
8001e0c: 0c1b lsrs r3, r3, #16
8001e0e: f003 0104 and.w r1, r3, #4
8001e12: 687b ldr r3, [r7, #4]
8001e14: 6a5b ldr r3, [r3, #36] ; 0x24
8001e16: f003 0210 and.w r2, r3, #16
8001e1a: 687b ldr r3, [r7, #4]
8001e1c: 681b ldr r3, [r3, #0]
8001e1e: 430a orrs r2, r1
8001e20: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8001e22: 687b ldr r3, [r7, #4]
8001e24: 681b ldr r3, [r3, #0]
8001e26: 69da ldr r2, [r3, #28]
8001e28: 687b ldr r3, [r7, #4]
8001e2a: 681b ldr r3, [r3, #0]
8001e2c: f422 6200 bic.w r2, r2, #2048 ; 0x800
8001e30: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8001e32: 687b ldr r3, [r7, #4]
8001e34: 2200 movs r2, #0
8001e36: 655a str r2, [r3, #84] ; 0x54
hspi->State = HAL_SPI_STATE_READY;
8001e38: 687b ldr r3, [r7, #4]
8001e3a: 2201 movs r2, #1
8001e3c: f883 2051 strb.w r2, [r3, #81] ; 0x51
return HAL_OK;
8001e40: 2300 movs r3, #0
}
8001e42: 4618 mov r0, r3
8001e44: 3708 adds r7, #8
8001e46: 46bd mov sp, r7
8001e48: bd80 pop {r7, pc}
08001e4a <HAL_SPI_Receive>:
* @param Size amount of data to be received
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8001e4a: b580 push {r7, lr}
8001e4c: b088 sub sp, #32
8001e4e: af02 add r7, sp, #8
8001e50: 60f8 str r0, [r7, #12]
8001e52: 60b9 str r1, [r7, #8]
8001e54: 603b str r3, [r7, #0]
8001e56: 4613 mov r3, r2
8001e58: 80fb strh r3, [r7, #6]
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
8001e5a: 2300 movs r3, #0
8001e5c: 75fb strb r3, [r7, #23]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
8001e5e: 68fb ldr r3, [r7, #12]
8001e60: 685b ldr r3, [r3, #4]
8001e62: f5b3 7f82 cmp.w r3, #260 ; 0x104
8001e66: d112 bne.n 8001e8e <HAL_SPI_Receive+0x44>
8001e68: 68fb ldr r3, [r7, #12]
8001e6a: 689b ldr r3, [r3, #8]
8001e6c: 2b00 cmp r3, #0
8001e6e: d10e bne.n 8001e8e <HAL_SPI_Receive+0x44>
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
8001e70: 68fb ldr r3, [r7, #12]
8001e72: 2204 movs r2, #4
8001e74: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
8001e78: 88fa ldrh r2, [r7, #6]
8001e7a: 683b ldr r3, [r7, #0]
8001e7c: 9300 str r3, [sp, #0]
8001e7e: 4613 mov r3, r2
8001e80: 68ba ldr r2, [r7, #8]
8001e82: 68b9 ldr r1, [r7, #8]
8001e84: 68f8 ldr r0, [r7, #12]
8001e86: f000 f8f1 bl 800206c <HAL_SPI_TransmitReceive>
8001e8a: 4603 mov r3, r0
8001e8c: e0ea b.n 8002064 <HAL_SPI_Receive+0x21a>
}
/* Process Locked */
__HAL_LOCK(hspi);
8001e8e: 68fb ldr r3, [r7, #12]
8001e90: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
8001e94: 2b01 cmp r3, #1
8001e96: d101 bne.n 8001e9c <HAL_SPI_Receive+0x52>
8001e98: 2302 movs r3, #2
8001e9a: e0e3 b.n 8002064 <HAL_SPI_Receive+0x21a>
8001e9c: 68fb ldr r3, [r7, #12]
8001e9e: 2201 movs r2, #1
8001ea0: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8001ea4: f7ff f850 bl 8000f48 <HAL_GetTick>
8001ea8: 6138 str r0, [r7, #16]
if (hspi->State != HAL_SPI_STATE_READY)
8001eaa: 68fb ldr r3, [r7, #12]
8001eac: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
8001eb0: b2db uxtb r3, r3
8001eb2: 2b01 cmp r3, #1
8001eb4: d002 beq.n 8001ebc <HAL_SPI_Receive+0x72>
{
errorcode = HAL_BUSY;
8001eb6: 2302 movs r3, #2
8001eb8: 75fb strb r3, [r7, #23]
goto error;
8001eba: e0ca b.n 8002052 <HAL_SPI_Receive+0x208>
}
if ((pData == NULL) || (Size == 0U))
8001ebc: 68bb ldr r3, [r7, #8]
8001ebe: 2b00 cmp r3, #0
8001ec0: d002 beq.n 8001ec8 <HAL_SPI_Receive+0x7e>
8001ec2: 88fb ldrh r3, [r7, #6]
8001ec4: 2b00 cmp r3, #0
8001ec6: d102 bne.n 8001ece <HAL_SPI_Receive+0x84>
{
errorcode = HAL_ERROR;
8001ec8: 2301 movs r3, #1
8001eca: 75fb strb r3, [r7, #23]
goto error;
8001ecc: e0c1 b.n 8002052 <HAL_SPI_Receive+0x208>
}
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
8001ece: 68fb ldr r3, [r7, #12]
8001ed0: 2204 movs r2, #4
8001ed2: f883 2051 strb.w r2, [r3, #81] ; 0x51
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8001ed6: 68fb ldr r3, [r7, #12]
8001ed8: 2200 movs r2, #0
8001eda: 655a str r2, [r3, #84] ; 0x54
hspi->pRxBuffPtr = (uint8_t *)pData;
8001edc: 68fb ldr r3, [r7, #12]
8001ede: 68ba ldr r2, [r7, #8]
8001ee0: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferSize = Size;
8001ee2: 68fb ldr r3, [r7, #12]
8001ee4: 88fa ldrh r2, [r7, #6]
8001ee6: 879a strh r2, [r3, #60] ; 0x3c
hspi->RxXferCount = Size;
8001ee8: 68fb ldr r3, [r7, #12]
8001eea: 88fa ldrh r2, [r7, #6]
8001eec: 87da strh r2, [r3, #62] ; 0x3e
/*Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
8001eee: 68fb ldr r3, [r7, #12]
8001ef0: 2200 movs r2, #0
8001ef2: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferSize = 0U;
8001ef4: 68fb ldr r3, [r7, #12]
8001ef6: 2200 movs r2, #0
8001ef8: 869a strh r2, [r3, #52] ; 0x34
hspi->TxXferCount = 0U;
8001efa: 68fb ldr r3, [r7, #12]
8001efc: 2200 movs r2, #0
8001efe: 86da strh r2, [r3, #54] ; 0x36
hspi->RxISR = NULL;
8001f00: 68fb ldr r3, [r7, #12]
8001f02: 2200 movs r2, #0
8001f04: 641a str r2, [r3, #64] ; 0x40
hspi->TxISR = NULL;
8001f06: 68fb ldr r3, [r7, #12]
8001f08: 2200 movs r2, #0
8001f0a: 645a str r2, [r3, #68] ; 0x44
hspi->RxXferCount--;
}
#endif /* USE_SPI_CRC */
/* Configure communication direction: 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
8001f0c: 68fb ldr r3, [r7, #12]
8001f0e: 689b ldr r3, [r3, #8]
8001f10: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8001f14: d10f bne.n 8001f36 <HAL_SPI_Receive+0xec>
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
8001f16: 68fb ldr r3, [r7, #12]
8001f18: 681b ldr r3, [r3, #0]
8001f1a: 681a ldr r2, [r3, #0]
8001f1c: 68fb ldr r3, [r7, #12]
8001f1e: 681b ldr r3, [r3, #0]
8001f20: f022 0240 bic.w r2, r2, #64 ; 0x40
8001f24: 601a str r2, [r3, #0]
SPI_1LINE_RX(hspi);
8001f26: 68fb ldr r3, [r7, #12]
8001f28: 681b ldr r3, [r3, #0]
8001f2a: 681a ldr r2, [r3, #0]
8001f2c: 68fb ldr r3, [r7, #12]
8001f2e: 681b ldr r3, [r3, #0]
8001f30: f422 4280 bic.w r2, r2, #16384 ; 0x4000
8001f34: 601a str r2, [r3, #0]
}
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
8001f36: 68fb ldr r3, [r7, #12]
8001f38: 681b ldr r3, [r3, #0]
8001f3a: 681b ldr r3, [r3, #0]
8001f3c: f003 0340 and.w r3, r3, #64 ; 0x40
8001f40: 2b40 cmp r3, #64 ; 0x40
8001f42: d007 beq.n 8001f54 <HAL_SPI_Receive+0x10a>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
8001f44: 68fb ldr r3, [r7, #12]
8001f46: 681b ldr r3, [r3, #0]
8001f48: 681a ldr r2, [r3, #0]
8001f4a: 68fb ldr r3, [r7, #12]
8001f4c: 681b ldr r3, [r3, #0]
8001f4e: f042 0240 orr.w r2, r2, #64 ; 0x40
8001f52: 601a str r2, [r3, #0]
}
/* Receive data in 8 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
8001f54: 68fb ldr r3, [r7, #12]
8001f56: 68db ldr r3, [r3, #12]
8001f58: 2b00 cmp r3, #0
8001f5a: d162 bne.n 8002022 <HAL_SPI_Receive+0x1d8>
{
/* Transfer loop */
while (hspi->RxXferCount > 0U)
8001f5c: e02e b.n 8001fbc <HAL_SPI_Receive+0x172>
{
/* Check the RXNE flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
8001f5e: 68fb ldr r3, [r7, #12]
8001f60: 681b ldr r3, [r3, #0]
8001f62: 689b ldr r3, [r3, #8]
8001f64: f003 0301 and.w r3, r3, #1
8001f68: 2b01 cmp r3, #1
8001f6a: d115 bne.n 8001f98 <HAL_SPI_Receive+0x14e>
{
/* read the received data */
(* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
8001f6c: 68fb ldr r3, [r7, #12]
8001f6e: 681b ldr r3, [r3, #0]
8001f70: f103 020c add.w r2, r3, #12
8001f74: 68fb ldr r3, [r7, #12]
8001f76: 6b9b ldr r3, [r3, #56] ; 0x38
8001f78: 7812 ldrb r2, [r2, #0]
8001f7a: b2d2 uxtb r2, r2
8001f7c: 701a strb r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint8_t);
8001f7e: 68fb ldr r3, [r7, #12]
8001f80: 6b9b ldr r3, [r3, #56] ; 0x38
8001f82: 1c5a adds r2, r3, #1
8001f84: 68fb ldr r3, [r7, #12]
8001f86: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount--;
8001f88: 68fb ldr r3, [r7, #12]
8001f8a: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001f8c: b29b uxth r3, r3
8001f8e: 3b01 subs r3, #1
8001f90: b29a uxth r2, r3
8001f92: 68fb ldr r3, [r7, #12]
8001f94: 87da strh r2, [r3, #62] ; 0x3e
8001f96: e011 b.n 8001fbc <HAL_SPI_Receive+0x172>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
8001f98: f7fe ffd6 bl 8000f48 <HAL_GetTick>
8001f9c: 4602 mov r2, r0
8001f9e: 693b ldr r3, [r7, #16]
8001fa0: 1ad3 subs r3, r2, r3
8001fa2: 683a ldr r2, [r7, #0]
8001fa4: 429a cmp r2, r3
8001fa6: d803 bhi.n 8001fb0 <HAL_SPI_Receive+0x166>
8001fa8: 683b ldr r3, [r7, #0]
8001faa: f1b3 3fff cmp.w r3, #4294967295
8001fae: d102 bne.n 8001fb6 <HAL_SPI_Receive+0x16c>
8001fb0: 683b ldr r3, [r7, #0]
8001fb2: 2b00 cmp r3, #0
8001fb4: d102 bne.n 8001fbc <HAL_SPI_Receive+0x172>
{
errorcode = HAL_TIMEOUT;
8001fb6: 2303 movs r3, #3
8001fb8: 75fb strb r3, [r7, #23]
goto error;
8001fba: e04a b.n 8002052 <HAL_SPI_Receive+0x208>
while (hspi->RxXferCount > 0U)
8001fbc: 68fb ldr r3, [r7, #12]
8001fbe: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001fc0: b29b uxth r3, r3
8001fc2: 2b00 cmp r3, #0
8001fc4: d1cb bne.n 8001f5e <HAL_SPI_Receive+0x114>
8001fc6: e031 b.n 800202c <HAL_SPI_Receive+0x1e2>
{
/* Transfer loop */
while (hspi->RxXferCount > 0U)
{
/* Check the RXNE flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
8001fc8: 68fb ldr r3, [r7, #12]
8001fca: 681b ldr r3, [r3, #0]
8001fcc: 689b ldr r3, [r3, #8]
8001fce: f003 0301 and.w r3, r3, #1
8001fd2: 2b01 cmp r3, #1
8001fd4: d113 bne.n 8001ffe <HAL_SPI_Receive+0x1b4>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
8001fd6: 68fb ldr r3, [r7, #12]
8001fd8: 681b ldr r3, [r3, #0]
8001fda: 68da ldr r2, [r3, #12]
8001fdc: 68fb ldr r3, [r7, #12]
8001fde: 6b9b ldr r3, [r3, #56] ; 0x38
8001fe0: b292 uxth r2, r2
8001fe2: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
8001fe4: 68fb ldr r3, [r7, #12]
8001fe6: 6b9b ldr r3, [r3, #56] ; 0x38
8001fe8: 1c9a adds r2, r3, #2
8001fea: 68fb ldr r3, [r7, #12]
8001fec: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount--;
8001fee: 68fb ldr r3, [r7, #12]
8001ff0: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001ff2: b29b uxth r3, r3
8001ff4: 3b01 subs r3, #1
8001ff6: b29a uxth r2, r3
8001ff8: 68fb ldr r3, [r7, #12]
8001ffa: 87da strh r2, [r3, #62] ; 0x3e
8001ffc: e011 b.n 8002022 <HAL_SPI_Receive+0x1d8>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
8001ffe: f7fe ffa3 bl 8000f48 <HAL_GetTick>
8002002: 4602 mov r2, r0
8002004: 693b ldr r3, [r7, #16]
8002006: 1ad3 subs r3, r2, r3
8002008: 683a ldr r2, [r7, #0]
800200a: 429a cmp r2, r3
800200c: d803 bhi.n 8002016 <HAL_SPI_Receive+0x1cc>
800200e: 683b ldr r3, [r7, #0]
8002010: f1b3 3fff cmp.w r3, #4294967295
8002014: d102 bne.n 800201c <HAL_SPI_Receive+0x1d2>
8002016: 683b ldr r3, [r7, #0]
8002018: 2b00 cmp r3, #0
800201a: d102 bne.n 8002022 <HAL_SPI_Receive+0x1d8>
{
errorcode = HAL_TIMEOUT;
800201c: 2303 movs r3, #3
800201e: 75fb strb r3, [r7, #23]
goto error;
8002020: e017 b.n 8002052 <HAL_SPI_Receive+0x208>
while (hspi->RxXferCount > 0U)
8002022: 68fb ldr r3, [r7, #12]
8002024: 8fdb ldrh r3, [r3, #62] ; 0x3e
8002026: b29b uxth r3, r3
8002028: 2b00 cmp r3, #0
800202a: d1cd bne.n 8001fc8 <HAL_SPI_Receive+0x17e>
UNUSED(tmpreg);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
800202c: 693a ldr r2, [r7, #16]
800202e: 6839 ldr r1, [r7, #0]
8002030: 68f8 ldr r0, [r7, #12]
8002032: f000 fa45 bl 80024c0 <SPI_EndRxTransaction>
8002036: 4603 mov r3, r0
8002038: 2b00 cmp r3, #0
800203a: d002 beq.n 8002042 <HAL_SPI_Receive+0x1f8>
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
800203c: 68fb ldr r3, [r7, #12]
800203e: 2220 movs r2, #32
8002040: 655a str r2, [r3, #84] ; 0x54
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
#endif /* USE_SPI_CRC */
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
8002042: 68fb ldr r3, [r7, #12]
8002044: 6d5b ldr r3, [r3, #84] ; 0x54
8002046: 2b00 cmp r3, #0
8002048: d002 beq.n 8002050 <HAL_SPI_Receive+0x206>
{
errorcode = HAL_ERROR;
800204a: 2301 movs r3, #1
800204c: 75fb strb r3, [r7, #23]
800204e: e000 b.n 8002052 <HAL_SPI_Receive+0x208>
}
error :
8002050: bf00 nop
hspi->State = HAL_SPI_STATE_READY;
8002052: 68fb ldr r3, [r7, #12]
8002054: 2201 movs r2, #1
8002056: f883 2051 strb.w r2, [r3, #81] ; 0x51
__HAL_UNLOCK(hspi);
800205a: 68fb ldr r3, [r7, #12]
800205c: 2200 movs r2, #0
800205e: f883 2050 strb.w r2, [r3, #80] ; 0x50
return errorcode;
8002062: 7dfb ldrb r3, [r7, #23]
}
8002064: 4618 mov r0, r3
8002066: 3718 adds r7, #24
8002068: 46bd mov sp, r7
800206a: bd80 pop {r7, pc}
0800206c <HAL_SPI_TransmitReceive>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout)
{
800206c: b580 push {r7, lr}
800206e: b08c sub sp, #48 ; 0x30
8002070: af00 add r7, sp, #0
8002072: 60f8 str r0, [r7, #12]
8002074: 60b9 str r1, [r7, #8]
8002076: 607a str r2, [r7, #4]
8002078: 807b strh r3, [r7, #2]
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
800207a: 2301 movs r3, #1
800207c: 62fb str r3, [r7, #44] ; 0x2c
HAL_StatusTypeDef errorcode = HAL_OK;
800207e: 2300 movs r3, #0
8002080: f887 302b strb.w r3, [r7, #43] ; 0x2b
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
8002084: 68fb ldr r3, [r7, #12]
8002086: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
800208a: 2b01 cmp r3, #1
800208c: d101 bne.n 8002092 <HAL_SPI_TransmitReceive+0x26>
800208e: 2302 movs r3, #2
8002090: e18a b.n 80023a8 <HAL_SPI_TransmitReceive+0x33c>
8002092: 68fb ldr r3, [r7, #12]
8002094: 2201 movs r2, #1
8002096: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
800209a: f7fe ff55 bl 8000f48 <HAL_GetTick>
800209e: 6278 str r0, [r7, #36] ; 0x24
/* Init temporary variables */
tmp_state = hspi->State;
80020a0: 68fb ldr r3, [r7, #12]
80020a2: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
80020a6: f887 3023 strb.w r3, [r7, #35] ; 0x23
tmp_mode = hspi->Init.Mode;
80020aa: 68fb ldr r3, [r7, #12]
80020ac: 685b ldr r3, [r3, #4]
80020ae: 61fb str r3, [r7, #28]
initial_TxXferCount = Size;
80020b0: 887b ldrh r3, [r7, #2]
80020b2: 837b strh r3, [r7, #26]
if (!((tmp_state == HAL_SPI_STATE_READY) || \
80020b4: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
80020b8: 2b01 cmp r3, #1
80020ba: d00f beq.n 80020dc <HAL_SPI_TransmitReceive+0x70>
80020bc: 69fb ldr r3, [r7, #28]
80020be: f5b3 7f82 cmp.w r3, #260 ; 0x104
80020c2: d107 bne.n 80020d4 <HAL_SPI_TransmitReceive+0x68>
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
80020c4: 68fb ldr r3, [r7, #12]
80020c6: 689b ldr r3, [r3, #8]
80020c8: 2b00 cmp r3, #0
80020ca: d103 bne.n 80020d4 <HAL_SPI_TransmitReceive+0x68>
80020cc: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
80020d0: 2b04 cmp r3, #4
80020d2: d003 beq.n 80020dc <HAL_SPI_TransmitReceive+0x70>
{
errorcode = HAL_BUSY;
80020d4: 2302 movs r3, #2
80020d6: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
80020da: e15b b.n 8002394 <HAL_SPI_TransmitReceive+0x328>
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
80020dc: 68bb ldr r3, [r7, #8]
80020de: 2b00 cmp r3, #0
80020e0: d005 beq.n 80020ee <HAL_SPI_TransmitReceive+0x82>
80020e2: 687b ldr r3, [r7, #4]
80020e4: 2b00 cmp r3, #0
80020e6: d002 beq.n 80020ee <HAL_SPI_TransmitReceive+0x82>
80020e8: 887b ldrh r3, [r7, #2]
80020ea: 2b00 cmp r3, #0
80020ec: d103 bne.n 80020f6 <HAL_SPI_TransmitReceive+0x8a>
{
errorcode = HAL_ERROR;
80020ee: 2301 movs r3, #1
80020f0: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
80020f4: e14e b.n 8002394 <HAL_SPI_TransmitReceive+0x328>
}
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
80020f6: 68fb ldr r3, [r7, #12]
80020f8: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
80020fc: b2db uxtb r3, r3
80020fe: 2b04 cmp r3, #4
8002100: d003 beq.n 800210a <HAL_SPI_TransmitReceive+0x9e>
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
8002102: 68fb ldr r3, [r7, #12]
8002104: 2205 movs r2, #5
8002106: f883 2051 strb.w r2, [r3, #81] ; 0x51
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
800210a: 68fb ldr r3, [r7, #12]
800210c: 2200 movs r2, #0
800210e: 655a str r2, [r3, #84] ; 0x54
hspi->pRxBuffPtr = (uint8_t *)pRxData;
8002110: 68fb ldr r3, [r7, #12]
8002112: 687a ldr r2, [r7, #4]
8002114: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount = Size;
8002116: 68fb ldr r3, [r7, #12]
8002118: 887a ldrh r2, [r7, #2]
800211a: 87da strh r2, [r3, #62] ; 0x3e
hspi->RxXferSize = Size;
800211c: 68fb ldr r3, [r7, #12]
800211e: 887a ldrh r2, [r7, #2]
8002120: 879a strh r2, [r3, #60] ; 0x3c
hspi->pTxBuffPtr = (uint8_t *)pTxData;
8002122: 68fb ldr r3, [r7, #12]
8002124: 68ba ldr r2, [r7, #8]
8002126: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount = Size;
8002128: 68fb ldr r3, [r7, #12]
800212a: 887a ldrh r2, [r7, #2]
800212c: 86da strh r2, [r3, #54] ; 0x36
hspi->TxXferSize = Size;
800212e: 68fb ldr r3, [r7, #12]
8002130: 887a ldrh r2, [r7, #2]
8002132: 869a strh r2, [r3, #52] ; 0x34
/*Init field not used in handle to zero */
hspi->RxISR = NULL;
8002134: 68fb ldr r3, [r7, #12]
8002136: 2200 movs r2, #0
8002138: 641a str r2, [r3, #64] ; 0x40
hspi->TxISR = NULL;
800213a: 68fb ldr r3, [r7, #12]
800213c: 2200 movs r2, #0
800213e: 645a str r2, [r3, #68] ; 0x44
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
8002140: 68fb ldr r3, [r7, #12]
8002142: 681b ldr r3, [r3, #0]
8002144: 681b ldr r3, [r3, #0]
8002146: f003 0340 and.w r3, r3, #64 ; 0x40
800214a: 2b40 cmp r3, #64 ; 0x40
800214c: d007 beq.n 800215e <HAL_SPI_TransmitReceive+0xf2>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
800214e: 68fb ldr r3, [r7, #12]
8002150: 681b ldr r3, [r3, #0]
8002152: 681a ldr r2, [r3, #0]
8002154: 68fb ldr r3, [r7, #12]
8002156: 681b ldr r3, [r3, #0]
8002158: f042 0240 orr.w r2, r2, #64 ; 0x40
800215c: 601a str r2, [r3, #0]
}
/* Transmit and Receive data in 16 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
800215e: 68fb ldr r3, [r7, #12]
8002160: 68db ldr r3, [r3, #12]
8002162: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8002166: d178 bne.n 800225a <HAL_SPI_TransmitReceive+0x1ee>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8002168: 68fb ldr r3, [r7, #12]
800216a: 685b ldr r3, [r3, #4]
800216c: 2b00 cmp r3, #0
800216e: d002 beq.n 8002176 <HAL_SPI_TransmitReceive+0x10a>
8002170: 8b7b ldrh r3, [r7, #26]
8002172: 2b01 cmp r3, #1
8002174: d166 bne.n 8002244 <HAL_SPI_TransmitReceive+0x1d8>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8002176: 68fb ldr r3, [r7, #12]
8002178: 6b1b ldr r3, [r3, #48] ; 0x30
800217a: 881a ldrh r2, [r3, #0]
800217c: 68fb ldr r3, [r7, #12]
800217e: 681b ldr r3, [r3, #0]
8002180: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8002182: 68fb ldr r3, [r7, #12]
8002184: 6b1b ldr r3, [r3, #48] ; 0x30
8002186: 1c9a adds r2, r3, #2
8002188: 68fb ldr r3, [r7, #12]
800218a: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
800218c: 68fb ldr r3, [r7, #12]
800218e: 8edb ldrh r3, [r3, #54] ; 0x36
8002190: b29b uxth r3, r3
8002192: 3b01 subs r3, #1
8002194: b29a uxth r2, r3
8002196: 68fb ldr r3, [r7, #12]
8002198: 86da strh r2, [r3, #54] ; 0x36
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
800219a: e053 b.n 8002244 <HAL_SPI_TransmitReceive+0x1d8>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
800219c: 68fb ldr r3, [r7, #12]
800219e: 681b ldr r3, [r3, #0]
80021a0: 689b ldr r3, [r3, #8]
80021a2: f003 0302 and.w r3, r3, #2
80021a6: 2b02 cmp r3, #2
80021a8: d11b bne.n 80021e2 <HAL_SPI_TransmitReceive+0x176>
80021aa: 68fb ldr r3, [r7, #12]
80021ac: 8edb ldrh r3, [r3, #54] ; 0x36
80021ae: b29b uxth r3, r3
80021b0: 2b00 cmp r3, #0
80021b2: d016 beq.n 80021e2 <HAL_SPI_TransmitReceive+0x176>
80021b4: 6afb ldr r3, [r7, #44] ; 0x2c
80021b6: 2b01 cmp r3, #1
80021b8: d113 bne.n 80021e2 <HAL_SPI_TransmitReceive+0x176>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
80021ba: 68fb ldr r3, [r7, #12]
80021bc: 6b1b ldr r3, [r3, #48] ; 0x30
80021be: 881a ldrh r2, [r3, #0]
80021c0: 68fb ldr r3, [r7, #12]
80021c2: 681b ldr r3, [r3, #0]
80021c4: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
80021c6: 68fb ldr r3, [r7, #12]
80021c8: 6b1b ldr r3, [r3, #48] ; 0x30
80021ca: 1c9a adds r2, r3, #2
80021cc: 68fb ldr r3, [r7, #12]
80021ce: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
80021d0: 68fb ldr r3, [r7, #12]
80021d2: 8edb ldrh r3, [r3, #54] ; 0x36
80021d4: b29b uxth r3, r3
80021d6: 3b01 subs r3, #1
80021d8: b29a uxth r2, r3
80021da: 68fb ldr r3, [r7, #12]
80021dc: 86da strh r2, [r3, #54] ; 0x36
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
80021de: 2300 movs r3, #0
80021e0: 62fb str r3, [r7, #44] ; 0x2c
}
#endif /* USE_SPI_CRC */
}
/* Check RXNE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
80021e2: 68fb ldr r3, [r7, #12]
80021e4: 681b ldr r3, [r3, #0]
80021e6: 689b ldr r3, [r3, #8]
80021e8: f003 0301 and.w r3, r3, #1
80021ec: 2b01 cmp r3, #1
80021ee: d119 bne.n 8002224 <HAL_SPI_TransmitReceive+0x1b8>
80021f0: 68fb ldr r3, [r7, #12]
80021f2: 8fdb ldrh r3, [r3, #62] ; 0x3e
80021f4: b29b uxth r3, r3
80021f6: 2b00 cmp r3, #0
80021f8: d014 beq.n 8002224 <HAL_SPI_TransmitReceive+0x1b8>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
80021fa: 68fb ldr r3, [r7, #12]
80021fc: 681b ldr r3, [r3, #0]
80021fe: 68da ldr r2, [r3, #12]
8002200: 68fb ldr r3, [r7, #12]
8002202: 6b9b ldr r3, [r3, #56] ; 0x38
8002204: b292 uxth r2, r2
8002206: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
8002208: 68fb ldr r3, [r7, #12]
800220a: 6b9b ldr r3, [r3, #56] ; 0x38
800220c: 1c9a adds r2, r3, #2
800220e: 68fb ldr r3, [r7, #12]
8002210: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount--;
8002212: 68fb ldr r3, [r7, #12]
8002214: 8fdb ldrh r3, [r3, #62] ; 0x3e
8002216: b29b uxth r3, r3
8002218: 3b01 subs r3, #1
800221a: b29a uxth r2, r3
800221c: 68fb ldr r3, [r7, #12]
800221e: 87da strh r2, [r3, #62] ; 0x3e
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
8002220: 2301 movs r3, #1
8002222: 62fb str r3, [r7, #44] ; 0x2c
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
8002224: f7fe fe90 bl 8000f48 <HAL_GetTick>
8002228: 4602 mov r2, r0
800222a: 6a7b ldr r3, [r7, #36] ; 0x24
800222c: 1ad3 subs r3, r2, r3
800222e: 6bba ldr r2, [r7, #56] ; 0x38
8002230: 429a cmp r2, r3
8002232: d807 bhi.n 8002244 <HAL_SPI_TransmitReceive+0x1d8>
8002234: 6bbb ldr r3, [r7, #56] ; 0x38
8002236: f1b3 3fff cmp.w r3, #4294967295
800223a: d003 beq.n 8002244 <HAL_SPI_TransmitReceive+0x1d8>
{
errorcode = HAL_TIMEOUT;
800223c: 2303 movs r3, #3
800223e: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
8002242: e0a7 b.n 8002394 <HAL_SPI_TransmitReceive+0x328>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8002244: 68fb ldr r3, [r7, #12]
8002246: 8edb ldrh r3, [r3, #54] ; 0x36
8002248: b29b uxth r3, r3
800224a: 2b00 cmp r3, #0
800224c: d1a6 bne.n 800219c <HAL_SPI_TransmitReceive+0x130>
800224e: 68fb ldr r3, [r7, #12]
8002250: 8fdb ldrh r3, [r3, #62] ; 0x3e
8002252: b29b uxth r3, r3
8002254: 2b00 cmp r3, #0
8002256: d1a1 bne.n 800219c <HAL_SPI_TransmitReceive+0x130>
8002258: e07c b.n 8002354 <HAL_SPI_TransmitReceive+0x2e8>
}
}
/* Transmit and Receive data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
800225a: 68fb ldr r3, [r7, #12]
800225c: 685b ldr r3, [r3, #4]
800225e: 2b00 cmp r3, #0
8002260: d002 beq.n 8002268 <HAL_SPI_TransmitReceive+0x1fc>
8002262: 8b7b ldrh r3, [r7, #26]
8002264: 2b01 cmp r3, #1
8002266: d16b bne.n 8002340 <HAL_SPI_TransmitReceive+0x2d4>
{
*((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
8002268: 68fb ldr r3, [r7, #12]
800226a: 6b1a ldr r2, [r3, #48] ; 0x30
800226c: 68fb ldr r3, [r7, #12]
800226e: 681b ldr r3, [r3, #0]
8002270: 330c adds r3, #12
8002272: 7812 ldrb r2, [r2, #0]
8002274: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
8002276: 68fb ldr r3, [r7, #12]
8002278: 6b1b ldr r3, [r3, #48] ; 0x30
800227a: 1c5a adds r2, r3, #1
800227c: 68fb ldr r3, [r7, #12]
800227e: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8002280: 68fb ldr r3, [r7, #12]
8002282: 8edb ldrh r3, [r3, #54] ; 0x36
8002284: b29b uxth r3, r3
8002286: 3b01 subs r3, #1
8002288: b29a uxth r2, r3
800228a: 68fb ldr r3, [r7, #12]
800228c: 86da strh r2, [r3, #54] ; 0x36
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
800228e: e057 b.n 8002340 <HAL_SPI_TransmitReceive+0x2d4>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
8002290: 68fb ldr r3, [r7, #12]
8002292: 681b ldr r3, [r3, #0]
8002294: 689b ldr r3, [r3, #8]
8002296: f003 0302 and.w r3, r3, #2
800229a: 2b02 cmp r3, #2
800229c: d11c bne.n 80022d8 <HAL_SPI_TransmitReceive+0x26c>
800229e: 68fb ldr r3, [r7, #12]
80022a0: 8edb ldrh r3, [r3, #54] ; 0x36
80022a2: b29b uxth r3, r3
80022a4: 2b00 cmp r3, #0
80022a6: d017 beq.n 80022d8 <HAL_SPI_TransmitReceive+0x26c>
80022a8: 6afb ldr r3, [r7, #44] ; 0x2c
80022aa: 2b01 cmp r3, #1
80022ac: d114 bne.n 80022d8 <HAL_SPI_TransmitReceive+0x26c>
{
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
80022ae: 68fb ldr r3, [r7, #12]
80022b0: 6b1a ldr r2, [r3, #48] ; 0x30
80022b2: 68fb ldr r3, [r7, #12]
80022b4: 681b ldr r3, [r3, #0]
80022b6: 330c adds r3, #12
80022b8: 7812 ldrb r2, [r2, #0]
80022ba: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
80022bc: 68fb ldr r3, [r7, #12]
80022be: 6b1b ldr r3, [r3, #48] ; 0x30
80022c0: 1c5a adds r2, r3, #1
80022c2: 68fb ldr r3, [r7, #12]
80022c4: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
80022c6: 68fb ldr r3, [r7, #12]
80022c8: 8edb ldrh r3, [r3, #54] ; 0x36
80022ca: b29b uxth r3, r3
80022cc: 3b01 subs r3, #1
80022ce: b29a uxth r2, r3
80022d0: 68fb ldr r3, [r7, #12]
80022d2: 86da strh r2, [r3, #54] ; 0x36
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
80022d4: 2300 movs r3, #0
80022d6: 62fb str r3, [r7, #44] ; 0x2c
}
#endif /* USE_SPI_CRC */
}
/* Wait until RXNE flag is reset */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
80022d8: 68fb ldr r3, [r7, #12]
80022da: 681b ldr r3, [r3, #0]
80022dc: 689b ldr r3, [r3, #8]
80022de: f003 0301 and.w r3, r3, #1
80022e2: 2b01 cmp r3, #1
80022e4: d119 bne.n 800231a <HAL_SPI_TransmitReceive+0x2ae>
80022e6: 68fb ldr r3, [r7, #12]
80022e8: 8fdb ldrh r3, [r3, #62] ; 0x3e
80022ea: b29b uxth r3, r3
80022ec: 2b00 cmp r3, #0
80022ee: d014 beq.n 800231a <HAL_SPI_TransmitReceive+0x2ae>
{
(*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
80022f0: 68fb ldr r3, [r7, #12]
80022f2: 681b ldr r3, [r3, #0]
80022f4: 68da ldr r2, [r3, #12]
80022f6: 68fb ldr r3, [r7, #12]
80022f8: 6b9b ldr r3, [r3, #56] ; 0x38
80022fa: b2d2 uxtb r2, r2
80022fc: 701a strb r2, [r3, #0]
hspi->pRxBuffPtr++;
80022fe: 68fb ldr r3, [r7, #12]
8002300: 6b9b ldr r3, [r3, #56] ; 0x38
8002302: 1c5a adds r2, r3, #1
8002304: 68fb ldr r3, [r7, #12]
8002306: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount--;
8002308: 68fb ldr r3, [r7, #12]
800230a: 8fdb ldrh r3, [r3, #62] ; 0x3e
800230c: b29b uxth r3, r3
800230e: 3b01 subs r3, #1
8002310: b29a uxth r2, r3
8002312: 68fb ldr r3, [r7, #12]
8002314: 87da strh r2, [r3, #62] ; 0x3e
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
8002316: 2301 movs r3, #1
8002318: 62fb str r3, [r7, #44] ; 0x2c
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
800231a: f7fe fe15 bl 8000f48 <HAL_GetTick>
800231e: 4602 mov r2, r0
8002320: 6a7b ldr r3, [r7, #36] ; 0x24
8002322: 1ad3 subs r3, r2, r3
8002324: 6bba ldr r2, [r7, #56] ; 0x38
8002326: 429a cmp r2, r3
8002328: d803 bhi.n 8002332 <HAL_SPI_TransmitReceive+0x2c6>
800232a: 6bbb ldr r3, [r7, #56] ; 0x38
800232c: f1b3 3fff cmp.w r3, #4294967295
8002330: d102 bne.n 8002338 <HAL_SPI_TransmitReceive+0x2cc>
8002332: 6bbb ldr r3, [r7, #56] ; 0x38
8002334: 2b00 cmp r3, #0
8002336: d103 bne.n 8002340 <HAL_SPI_TransmitReceive+0x2d4>
{
errorcode = HAL_TIMEOUT;
8002338: 2303 movs r3, #3
800233a: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
800233e: e029 b.n 8002394 <HAL_SPI_TransmitReceive+0x328>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8002340: 68fb ldr r3, [r7, #12]
8002342: 8edb ldrh r3, [r3, #54] ; 0x36
8002344: b29b uxth r3, r3
8002346: 2b00 cmp r3, #0
8002348: d1a2 bne.n 8002290 <HAL_SPI_TransmitReceive+0x224>
800234a: 68fb ldr r3, [r7, #12]
800234c: 8fdb ldrh r3, [r3, #62] ; 0x3e
800234e: b29b uxth r3, r3
8002350: 2b00 cmp r3, #0
8002352: d19d bne.n 8002290 <HAL_SPI_TransmitReceive+0x224>
errorcode = HAL_ERROR;
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
8002354: 6a7a ldr r2, [r7, #36] ; 0x24
8002356: 6bb9 ldr r1, [r7, #56] ; 0x38
8002358: 68f8 ldr r0, [r7, #12]
800235a: f000 f917 bl 800258c <SPI_EndRxTxTransaction>
800235e: 4603 mov r3, r0
8002360: 2b00 cmp r3, #0
8002362: d006 beq.n 8002372 <HAL_SPI_TransmitReceive+0x306>
{
errorcode = HAL_ERROR;
8002364: 2301 movs r3, #1
8002366: f887 302b strb.w r3, [r7, #43] ; 0x2b
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
800236a: 68fb ldr r3, [r7, #12]
800236c: 2220 movs r2, #32
800236e: 655a str r2, [r3, #84] ; 0x54
goto error;
8002370: e010 b.n 8002394 <HAL_SPI_TransmitReceive+0x328>
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
8002372: 68fb ldr r3, [r7, #12]
8002374: 689b ldr r3, [r3, #8]
8002376: 2b00 cmp r3, #0
8002378: d10b bne.n 8002392 <HAL_SPI_TransmitReceive+0x326>
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
800237a: 2300 movs r3, #0
800237c: 617b str r3, [r7, #20]
800237e: 68fb ldr r3, [r7, #12]
8002380: 681b ldr r3, [r3, #0]
8002382: 68db ldr r3, [r3, #12]
8002384: 617b str r3, [r7, #20]
8002386: 68fb ldr r3, [r7, #12]
8002388: 681b ldr r3, [r3, #0]
800238a: 689b ldr r3, [r3, #8]
800238c: 617b str r3, [r7, #20]
800238e: 697b ldr r3, [r7, #20]
8002390: e000 b.n 8002394 <HAL_SPI_TransmitReceive+0x328>
}
error :
8002392: bf00 nop
hspi->State = HAL_SPI_STATE_READY;
8002394: 68fb ldr r3, [r7, #12]
8002396: 2201 movs r2, #1
8002398: f883 2051 strb.w r2, [r3, #81] ; 0x51
__HAL_UNLOCK(hspi);
800239c: 68fb ldr r3, [r7, #12]
800239e: 2200 movs r2, #0
80023a0: f883 2050 strb.w r2, [r3, #80] ; 0x50
return errorcode;
80023a4: f897 302b ldrb.w r3, [r7, #43] ; 0x2b
}
80023a8: 4618 mov r0, r3
80023aa: 3730 adds r7, #48 ; 0x30
80023ac: 46bd mov sp, r7
80023ae: bd80 pop {r7, pc}
080023b0 <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
80023b0: b580 push {r7, lr}
80023b2: b088 sub sp, #32
80023b4: af00 add r7, sp, #0
80023b6: 60f8 str r0, [r7, #12]
80023b8: 60b9 str r1, [r7, #8]
80023ba: 603b str r3, [r7, #0]
80023bc: 4613 mov r3, r2
80023be: 71fb strb r3, [r7, #7]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
80023c0: f7fe fdc2 bl 8000f48 <HAL_GetTick>
80023c4: 4602 mov r2, r0
80023c6: 6abb ldr r3, [r7, #40] ; 0x28
80023c8: 1a9b subs r3, r3, r2
80023ca: 683a ldr r2, [r7, #0]
80023cc: 4413 add r3, r2
80023ce: 61fb str r3, [r7, #28]
tmp_tickstart = HAL_GetTick();
80023d0: f7fe fdba bl 8000f48 <HAL_GetTick>
80023d4: 61b8 str r0, [r7, #24]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
80023d6: 4b39 ldr r3, [pc, #228] ; (80024bc <SPI_WaitFlagStateUntilTimeout+0x10c>)
80023d8: 681b ldr r3, [r3, #0]
80023da: 015b lsls r3, r3, #5
80023dc: 0d1b lsrs r3, r3, #20
80023de: 69fa ldr r2, [r7, #28]
80023e0: fb02 f303 mul.w r3, r2, r3
80023e4: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
80023e6: e054 b.n 8002492 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (Timeout != HAL_MAX_DELAY)
80023e8: 683b ldr r3, [r7, #0]
80023ea: f1b3 3fff cmp.w r3, #4294967295
80023ee: d050 beq.n 8002492 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
80023f0: f7fe fdaa bl 8000f48 <HAL_GetTick>
80023f4: 4602 mov r2, r0
80023f6: 69bb ldr r3, [r7, #24]
80023f8: 1ad3 subs r3, r2, r3
80023fa: 69fa ldr r2, [r7, #28]
80023fc: 429a cmp r2, r3
80023fe: d902 bls.n 8002406 <SPI_WaitFlagStateUntilTimeout+0x56>
8002400: 69fb ldr r3, [r7, #28]
8002402: 2b00 cmp r3, #0
8002404: d13d bne.n 8002482 <SPI_WaitFlagStateUntilTimeout+0xd2>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
8002406: 68fb ldr r3, [r7, #12]
8002408: 681b ldr r3, [r3, #0]
800240a: 685a ldr r2, [r3, #4]
800240c: 68fb ldr r3, [r7, #12]
800240e: 681b ldr r3, [r3, #0]
8002410: f022 02e0 bic.w r2, r2, #224 ; 0xe0
8002414: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
8002416: 68fb ldr r3, [r7, #12]
8002418: 685b ldr r3, [r3, #4]
800241a: f5b3 7f82 cmp.w r3, #260 ; 0x104
800241e: d111 bne.n 8002444 <SPI_WaitFlagStateUntilTimeout+0x94>
8002420: 68fb ldr r3, [r7, #12]
8002422: 689b ldr r3, [r3, #8]
8002424: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8002428: d004 beq.n 8002434 <SPI_WaitFlagStateUntilTimeout+0x84>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
800242a: 68fb ldr r3, [r7, #12]
800242c: 689b ldr r3, [r3, #8]
800242e: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8002432: d107 bne.n 8002444 <SPI_WaitFlagStateUntilTimeout+0x94>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8002434: 68fb ldr r3, [r7, #12]
8002436: 681b ldr r3, [r3, #0]
8002438: 681a ldr r2, [r3, #0]
800243a: 68fb ldr r3, [r7, #12]
800243c: 681b ldr r3, [r3, #0]
800243e: f022 0240 bic.w r2, r2, #64 ; 0x40
8002442: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
8002444: 68fb ldr r3, [r7, #12]
8002446: 6a9b ldr r3, [r3, #40] ; 0x28
8002448: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800244c: d10f bne.n 800246e <SPI_WaitFlagStateUntilTimeout+0xbe>
{
SPI_RESET_CRC(hspi);
800244e: 68fb ldr r3, [r7, #12]
8002450: 681b ldr r3, [r3, #0]
8002452: 681a ldr r2, [r3, #0]
8002454: 68fb ldr r3, [r7, #12]
8002456: 681b ldr r3, [r3, #0]
8002458: f422 5200 bic.w r2, r2, #8192 ; 0x2000
800245c: 601a str r2, [r3, #0]
800245e: 68fb ldr r3, [r7, #12]
8002460: 681b ldr r3, [r3, #0]
8002462: 681a ldr r2, [r3, #0]
8002464: 68fb ldr r3, [r7, #12]
8002466: 681b ldr r3, [r3, #0]
8002468: f442 5200 orr.w r2, r2, #8192 ; 0x2000
800246c: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
800246e: 68fb ldr r3, [r7, #12]
8002470: 2201 movs r2, #1
8002472: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
8002476: 68fb ldr r3, [r7, #12]
8002478: 2200 movs r2, #0
800247a: f883 2050 strb.w r2, [r3, #80] ; 0x50
return HAL_TIMEOUT;
800247e: 2303 movs r3, #3
8002480: e017 b.n 80024b2 <SPI_WaitFlagStateUntilTimeout+0x102>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
8002482: 697b ldr r3, [r7, #20]
8002484: 2b00 cmp r3, #0
8002486: d101 bne.n 800248c <SPI_WaitFlagStateUntilTimeout+0xdc>
{
tmp_timeout = 0U;
8002488: 2300 movs r3, #0
800248a: 61fb str r3, [r7, #28]
}
count--;
800248c: 697b ldr r3, [r7, #20]
800248e: 3b01 subs r3, #1
8002490: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8002492: 68fb ldr r3, [r7, #12]
8002494: 681b ldr r3, [r3, #0]
8002496: 689a ldr r2, [r3, #8]
8002498: 68bb ldr r3, [r7, #8]
800249a: 4013 ands r3, r2
800249c: 68ba ldr r2, [r7, #8]
800249e: 429a cmp r2, r3
80024a0: bf0c ite eq
80024a2: 2301 moveq r3, #1
80024a4: 2300 movne r3, #0
80024a6: b2db uxtb r3, r3
80024a8: 461a mov r2, r3
80024aa: 79fb ldrb r3, [r7, #7]
80024ac: 429a cmp r2, r3
80024ae: d19b bne.n 80023e8 <SPI_WaitFlagStateUntilTimeout+0x38>
}
}
return HAL_OK;
80024b0: 2300 movs r3, #0
}
80024b2: 4618 mov r0, r3
80024b4: 3720 adds r7, #32
80024b6: 46bd mov sp, r7
80024b8: bd80 pop {r7, pc}
80024ba: bf00 nop
80024bc: 20000004 .word 0x20000004
080024c0 <SPI_EndRxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
80024c0: b580 push {r7, lr}
80024c2: b086 sub sp, #24
80024c4: af02 add r7, sp, #8
80024c6: 60f8 str r0, [r7, #12]
80024c8: 60b9 str r1, [r7, #8]
80024ca: 607a str r2, [r7, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
80024cc: 68fb ldr r3, [r7, #12]
80024ce: 685b ldr r3, [r3, #4]
80024d0: f5b3 7f82 cmp.w r3, #260 ; 0x104
80024d4: d111 bne.n 80024fa <SPI_EndRxTransaction+0x3a>
80024d6: 68fb ldr r3, [r7, #12]
80024d8: 689b ldr r3, [r3, #8]
80024da: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80024de: d004 beq.n 80024ea <SPI_EndRxTransaction+0x2a>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
80024e0: 68fb ldr r3, [r7, #12]
80024e2: 689b ldr r3, [r3, #8]
80024e4: f5b3 6f80 cmp.w r3, #1024 ; 0x400
80024e8: d107 bne.n 80024fa <SPI_EndRxTransaction+0x3a>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80024ea: 68fb ldr r3, [r7, #12]
80024ec: 681b ldr r3, [r3, #0]
80024ee: 681a ldr r2, [r3, #0]
80024f0: 68fb ldr r3, [r7, #12]
80024f2: 681b ldr r3, [r3, #0]
80024f4: f022 0240 bic.w r2, r2, #64 ; 0x40
80024f8: 601a str r2, [r3, #0]
}
/* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
if (hspi->Init.Mode == SPI_MODE_MASTER)
80024fa: 68fb ldr r3, [r7, #12]
80024fc: 685b ldr r3, [r3, #4]
80024fe: f5b3 7f82 cmp.w r3, #260 ; 0x104
8002502: d12a bne.n 800255a <SPI_EndRxTransaction+0x9a>
{
if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY)
8002504: 68fb ldr r3, [r7, #12]
8002506: 689b ldr r3, [r3, #8]
8002508: f5b3 6f80 cmp.w r3, #1024 ; 0x400
800250c: d012 beq.n 8002534 <SPI_EndRxTransaction+0x74>
{
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
800250e: 687b ldr r3, [r7, #4]
8002510: 9300 str r3, [sp, #0]
8002512: 68bb ldr r3, [r7, #8]
8002514: 2200 movs r2, #0
8002516: 2180 movs r1, #128 ; 0x80
8002518: 68f8 ldr r0, [r7, #12]
800251a: f7ff ff49 bl 80023b0 <SPI_WaitFlagStateUntilTimeout>
800251e: 4603 mov r3, r0
8002520: 2b00 cmp r3, #0
8002522: d02d beq.n 8002580 <SPI_EndRxTransaction+0xc0>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8002524: 68fb ldr r3, [r7, #12]
8002526: 6d5b ldr r3, [r3, #84] ; 0x54
8002528: f043 0220 orr.w r2, r3, #32
800252c: 68fb ldr r3, [r7, #12]
800252e: 655a str r2, [r3, #84] ; 0x54
return HAL_TIMEOUT;
8002530: 2303 movs r3, #3
8002532: e026 b.n 8002582 <SPI_EndRxTransaction+0xc2>
}
}
else
{
/* Wait the RXNE reset */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
8002534: 687b ldr r3, [r7, #4]
8002536: 9300 str r3, [sp, #0]
8002538: 68bb ldr r3, [r7, #8]
800253a: 2200 movs r2, #0
800253c: 2101 movs r1, #1
800253e: 68f8 ldr r0, [r7, #12]
8002540: f7ff ff36 bl 80023b0 <SPI_WaitFlagStateUntilTimeout>
8002544: 4603 mov r3, r0
8002546: 2b00 cmp r3, #0
8002548: d01a beq.n 8002580 <SPI_EndRxTransaction+0xc0>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800254a: 68fb ldr r3, [r7, #12]
800254c: 6d5b ldr r3, [r3, #84] ; 0x54
800254e: f043 0220 orr.w r2, r3, #32
8002552: 68fb ldr r3, [r7, #12]
8002554: 655a str r2, [r3, #84] ; 0x54
return HAL_TIMEOUT;
8002556: 2303 movs r3, #3
8002558: e013 b.n 8002582 <SPI_EndRxTransaction+0xc2>
}
}
else
{
/* Wait the RXNE reset */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
800255a: 687b ldr r3, [r7, #4]
800255c: 9300 str r3, [sp, #0]
800255e: 68bb ldr r3, [r7, #8]
8002560: 2200 movs r2, #0
8002562: 2101 movs r1, #1
8002564: 68f8 ldr r0, [r7, #12]
8002566: f7ff ff23 bl 80023b0 <SPI_WaitFlagStateUntilTimeout>
800256a: 4603 mov r3, r0
800256c: 2b00 cmp r3, #0
800256e: d007 beq.n 8002580 <SPI_EndRxTransaction+0xc0>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8002570: 68fb ldr r3, [r7, #12]
8002572: 6d5b ldr r3, [r3, #84] ; 0x54
8002574: f043 0220 orr.w r2, r3, #32
8002578: 68fb ldr r3, [r7, #12]
800257a: 655a str r2, [r3, #84] ; 0x54
return HAL_TIMEOUT;
800257c: 2303 movs r3, #3
800257e: e000 b.n 8002582 <SPI_EndRxTransaction+0xc2>
}
}
return HAL_OK;
8002580: 2300 movs r3, #0
}
8002582: 4618 mov r0, r3
8002584: 3710 adds r7, #16
8002586: 46bd mov sp, r7
8002588: bd80 pop {r7, pc}
...
0800258c <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
800258c: b580 push {r7, lr}
800258e: b088 sub sp, #32
8002590: af02 add r7, sp, #8
8002592: 60f8 str r0, [r7, #12]
8002594: 60b9 str r1, [r7, #8]
8002596: 607a str r2, [r7, #4]
/* Timeout in µs */
__IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
8002598: 4b1b ldr r3, [pc, #108] ; (8002608 <SPI_EndRxTxTransaction+0x7c>)
800259a: 681b ldr r3, [r3, #0]
800259c: 4a1b ldr r2, [pc, #108] ; (800260c <SPI_EndRxTxTransaction+0x80>)
800259e: fba2 2303 umull r2, r3, r2, r3
80025a2: 0d5b lsrs r3, r3, #21
80025a4: f44f 727a mov.w r2, #1000 ; 0x3e8
80025a8: fb02 f303 mul.w r3, r2, r3
80025ac: 617b str r3, [r7, #20]
/* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
if (hspi->Init.Mode == SPI_MODE_MASTER)
80025ae: 68fb ldr r3, [r7, #12]
80025b0: 685b ldr r3, [r3, #4]
80025b2: f5b3 7f82 cmp.w r3, #260 ; 0x104
80025b6: d112 bne.n 80025de <SPI_EndRxTxTransaction+0x52>
{
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
80025b8: 687b ldr r3, [r7, #4]
80025ba: 9300 str r3, [sp, #0]
80025bc: 68bb ldr r3, [r7, #8]
80025be: 2200 movs r2, #0
80025c0: 2180 movs r1, #128 ; 0x80
80025c2: 68f8 ldr r0, [r7, #12]
80025c4: f7ff fef4 bl 80023b0 <SPI_WaitFlagStateUntilTimeout>
80025c8: 4603 mov r3, r0
80025ca: 2b00 cmp r3, #0
80025cc: d016 beq.n 80025fc <SPI_EndRxTxTransaction+0x70>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
80025ce: 68fb ldr r3, [r7, #12]
80025d0: 6d5b ldr r3, [r3, #84] ; 0x54
80025d2: f043 0220 orr.w r2, r3, #32
80025d6: 68fb ldr r3, [r7, #12]
80025d8: 655a str r2, [r3, #84] ; 0x54
return HAL_TIMEOUT;
80025da: 2303 movs r3, #3
80025dc: e00f b.n 80025fe <SPI_EndRxTxTransaction+0x72>
* User have to calculate the timeout value to fit with the time of 1 byte transfer.
* This time is directly link with the SPI clock from Master device.
*/
do
{
if (count == 0U)
80025de: 697b ldr r3, [r7, #20]
80025e0: 2b00 cmp r3, #0
80025e2: d00a beq.n 80025fa <SPI_EndRxTxTransaction+0x6e>
{
break;
}
count--;
80025e4: 697b ldr r3, [r7, #20]
80025e6: 3b01 subs r3, #1
80025e8: 617b str r3, [r7, #20]
} while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
80025ea: 68fb ldr r3, [r7, #12]
80025ec: 681b ldr r3, [r3, #0]
80025ee: 689b ldr r3, [r3, #8]
80025f0: f003 0380 and.w r3, r3, #128 ; 0x80
80025f4: 2b80 cmp r3, #128 ; 0x80
80025f6: d0f2 beq.n 80025de <SPI_EndRxTxTransaction+0x52>
80025f8: e000 b.n 80025fc <SPI_EndRxTxTransaction+0x70>
break;
80025fa: bf00 nop
}
return HAL_OK;
80025fc: 2300 movs r3, #0
}
80025fe: 4618 mov r0, r3
8002600: 3718 adds r7, #24
8002602: 46bd mov sp, r7
8002604: bd80 pop {r7, pc}
8002606: bf00 nop
8002608: 20000004 .word 0x20000004
800260c: 165e9f81 .word 0x165e9f81
08002610 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8002610: b580 push {r7, lr}
8002612: b082 sub sp, #8
8002614: af00 add r7, sp, #0
8002616: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8002618: 687b ldr r3, [r7, #4]
800261a: 2b00 cmp r3, #0
800261c: d101 bne.n 8002622 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
800261e: 2301 movs r3, #1
8002620: e041 b.n 80026a6 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002622: 687b ldr r3, [r7, #4]
8002624: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8002628: b2db uxtb r3, r3
800262a: 2b00 cmp r3, #0
800262c: d106 bne.n 800263c <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
800262e: 687b ldr r3, [r7, #4]
8002630: 2200 movs r2, #0
8002632: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8002636: 6878 ldr r0, [r7, #4]
8002638: f7fe fab8 bl 8000bac <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800263c: 687b ldr r3, [r7, #4]
800263e: 2202 movs r2, #2
8002640: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002644: 687b ldr r3, [r7, #4]
8002646: 681a ldr r2, [r3, #0]
8002648: 687b ldr r3, [r7, #4]
800264a: 3304 adds r3, #4
800264c: 4619 mov r1, r3
800264e: 4610 mov r0, r2
8002650: f000 fda8 bl 80031a4 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002654: 687b ldr r3, [r7, #4]
8002656: 2201 movs r2, #1
8002658: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800265c: 687b ldr r3, [r7, #4]
800265e: 2201 movs r2, #1
8002660: f883 203e strb.w r2, [r3, #62] ; 0x3e
8002664: 687b ldr r3, [r7, #4]
8002666: 2201 movs r2, #1
8002668: f883 203f strb.w r2, [r3, #63] ; 0x3f
800266c: 687b ldr r3, [r7, #4]
800266e: 2201 movs r2, #1
8002670: f883 2040 strb.w r2, [r3, #64] ; 0x40
8002674: 687b ldr r3, [r7, #4]
8002676: 2201 movs r2, #1
8002678: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800267c: 687b ldr r3, [r7, #4]
800267e: 2201 movs r2, #1
8002680: f883 2042 strb.w r2, [r3, #66] ; 0x42
8002684: 687b ldr r3, [r7, #4]
8002686: 2201 movs r2, #1
8002688: f883 2043 strb.w r2, [r3, #67] ; 0x43
800268c: 687b ldr r3, [r7, #4]
800268e: 2201 movs r2, #1
8002690: f883 2044 strb.w r2, [r3, #68] ; 0x44
8002694: 687b ldr r3, [r7, #4]
8002696: 2201 movs r2, #1
8002698: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
800269c: 687b ldr r3, [r7, #4]
800269e: 2201 movs r2, #1
80026a0: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
80026a4: 2300 movs r3, #0
}
80026a6: 4618 mov r0, r3
80026a8: 3708 adds r7, #8
80026aa: 46bd mov sp, r7
80026ac: bd80 pop {r7, pc}
...
080026b0 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
80026b0: b480 push {r7}
80026b2: b085 sub sp, #20
80026b4: af00 add r7, sp, #0
80026b6: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
80026b8: 687b ldr r3, [r7, #4]
80026ba: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80026be: b2db uxtb r3, r3
80026c0: 2b01 cmp r3, #1
80026c2: d001 beq.n 80026c8 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
80026c4: 2301 movs r3, #1
80026c6: e04e b.n 8002766 <HAL_TIM_Base_Start_IT+0xb6>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80026c8: 687b ldr r3, [r7, #4]
80026ca: 2202 movs r2, #2
80026cc: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
80026d0: 687b ldr r3, [r7, #4]
80026d2: 681b ldr r3, [r3, #0]
80026d4: 68da ldr r2, [r3, #12]
80026d6: 687b ldr r3, [r7, #4]
80026d8: 681b ldr r3, [r3, #0]
80026da: f042 0201 orr.w r2, r2, #1
80026de: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80026e0: 687b ldr r3, [r7, #4]
80026e2: 681b ldr r3, [r3, #0]
80026e4: 4a23 ldr r2, [pc, #140] ; (8002774 <HAL_TIM_Base_Start_IT+0xc4>)
80026e6: 4293 cmp r3, r2
80026e8: d022 beq.n 8002730 <HAL_TIM_Base_Start_IT+0x80>
80026ea: 687b ldr r3, [r7, #4]
80026ec: 681b ldr r3, [r3, #0]
80026ee: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80026f2: d01d beq.n 8002730 <HAL_TIM_Base_Start_IT+0x80>
80026f4: 687b ldr r3, [r7, #4]
80026f6: 681b ldr r3, [r3, #0]
80026f8: 4a1f ldr r2, [pc, #124] ; (8002778 <HAL_TIM_Base_Start_IT+0xc8>)
80026fa: 4293 cmp r3, r2
80026fc: d018 beq.n 8002730 <HAL_TIM_Base_Start_IT+0x80>
80026fe: 687b ldr r3, [r7, #4]
8002700: 681b ldr r3, [r3, #0]
8002702: 4a1e ldr r2, [pc, #120] ; (800277c <HAL_TIM_Base_Start_IT+0xcc>)
8002704: 4293 cmp r3, r2
8002706: d013 beq.n 8002730 <HAL_TIM_Base_Start_IT+0x80>
8002708: 687b ldr r3, [r7, #4]
800270a: 681b ldr r3, [r3, #0]
800270c: 4a1c ldr r2, [pc, #112] ; (8002780 <HAL_TIM_Base_Start_IT+0xd0>)
800270e: 4293 cmp r3, r2
8002710: d00e beq.n 8002730 <HAL_TIM_Base_Start_IT+0x80>
8002712: 687b ldr r3, [r7, #4]
8002714: 681b ldr r3, [r3, #0]
8002716: 4a1b ldr r2, [pc, #108] ; (8002784 <HAL_TIM_Base_Start_IT+0xd4>)
8002718: 4293 cmp r3, r2
800271a: d009 beq.n 8002730 <HAL_TIM_Base_Start_IT+0x80>
800271c: 687b ldr r3, [r7, #4]
800271e: 681b ldr r3, [r3, #0]
8002720: 4a19 ldr r2, [pc, #100] ; (8002788 <HAL_TIM_Base_Start_IT+0xd8>)
8002722: 4293 cmp r3, r2
8002724: d004 beq.n 8002730 <HAL_TIM_Base_Start_IT+0x80>
8002726: 687b ldr r3, [r7, #4]
8002728: 681b ldr r3, [r3, #0]
800272a: 4a18 ldr r2, [pc, #96] ; (800278c <HAL_TIM_Base_Start_IT+0xdc>)
800272c: 4293 cmp r3, r2
800272e: d111 bne.n 8002754 <HAL_TIM_Base_Start_IT+0xa4>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8002730: 687b ldr r3, [r7, #4]
8002732: 681b ldr r3, [r3, #0]
8002734: 689b ldr r3, [r3, #8]
8002736: f003 0307 and.w r3, r3, #7
800273a: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800273c: 68fb ldr r3, [r7, #12]
800273e: 2b06 cmp r3, #6
8002740: d010 beq.n 8002764 <HAL_TIM_Base_Start_IT+0xb4>
{
__HAL_TIM_ENABLE(htim);
8002742: 687b ldr r3, [r7, #4]
8002744: 681b ldr r3, [r3, #0]
8002746: 681a ldr r2, [r3, #0]
8002748: 687b ldr r3, [r7, #4]
800274a: 681b ldr r3, [r3, #0]
800274c: f042 0201 orr.w r2, r2, #1
8002750: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002752: e007 b.n 8002764 <HAL_TIM_Base_Start_IT+0xb4>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8002754: 687b ldr r3, [r7, #4]
8002756: 681b ldr r3, [r3, #0]
8002758: 681a ldr r2, [r3, #0]
800275a: 687b ldr r3, [r7, #4]
800275c: 681b ldr r3, [r3, #0]
800275e: f042 0201 orr.w r2, r2, #1
8002762: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8002764: 2300 movs r3, #0
}
8002766: 4618 mov r0, r3
8002768: 3714 adds r7, #20
800276a: 46bd mov sp, r7
800276c: f85d 7b04 ldr.w r7, [sp], #4
8002770: 4770 bx lr
8002772: bf00 nop
8002774: 40010000 .word 0x40010000
8002778: 40000400 .word 0x40000400
800277c: 40000800 .word 0x40000800
8002780: 40000c00 .word 0x40000c00
8002784: 40010400 .word 0x40010400
8002788: 40014000 .word 0x40014000
800278c: 40001800 .word 0x40001800
08002790 <HAL_TIM_OC_Init>:
* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
* @param htim TIM Output Compare handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
{
8002790: b580 push {r7, lr}
8002792: b082 sub sp, #8
8002794: af00 add r7, sp, #0
8002796: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8002798: 687b ldr r3, [r7, #4]
800279a: 2b00 cmp r3, #0
800279c: d101 bne.n 80027a2 <HAL_TIM_OC_Init+0x12>
{
return HAL_ERROR;
800279e: 2301 movs r3, #1
80027a0: e041 b.n 8002826 <HAL_TIM_OC_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80027a2: 687b ldr r3, [r7, #4]
80027a4: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80027a8: b2db uxtb r3, r3
80027aa: 2b00 cmp r3, #0
80027ac: d106 bne.n 80027bc <HAL_TIM_OC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80027ae: 687b ldr r3, [r7, #4]
80027b0: 2200 movs r2, #0
80027b2: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->OC_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
80027b6: 6878 ldr r0, [r7, #4]
80027b8: f000 f839 bl 800282e <HAL_TIM_OC_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80027bc: 687b ldr r3, [r7, #4]
80027be: 2202 movs r2, #2
80027c0: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80027c4: 687b ldr r3, [r7, #4]
80027c6: 681a ldr r2, [r3, #0]
80027c8: 687b ldr r3, [r7, #4]
80027ca: 3304 adds r3, #4
80027cc: 4619 mov r1, r3
80027ce: 4610 mov r0, r2
80027d0: f000 fce8 bl 80031a4 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80027d4: 687b ldr r3, [r7, #4]
80027d6: 2201 movs r2, #1
80027d8: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80027dc: 687b ldr r3, [r7, #4]
80027de: 2201 movs r2, #1
80027e0: f883 203e strb.w r2, [r3, #62] ; 0x3e
80027e4: 687b ldr r3, [r7, #4]
80027e6: 2201 movs r2, #1
80027e8: f883 203f strb.w r2, [r3, #63] ; 0x3f
80027ec: 687b ldr r3, [r7, #4]
80027ee: 2201 movs r2, #1
80027f0: f883 2040 strb.w r2, [r3, #64] ; 0x40
80027f4: 687b ldr r3, [r7, #4]
80027f6: 2201 movs r2, #1
80027f8: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80027fc: 687b ldr r3, [r7, #4]
80027fe: 2201 movs r2, #1
8002800: f883 2042 strb.w r2, [r3, #66] ; 0x42
8002804: 687b ldr r3, [r7, #4]
8002806: 2201 movs r2, #1
8002808: f883 2043 strb.w r2, [r3, #67] ; 0x43
800280c: 687b ldr r3, [r7, #4]
800280e: 2201 movs r2, #1
8002810: f883 2044 strb.w r2, [r3, #68] ; 0x44
8002814: 687b ldr r3, [r7, #4]
8002816: 2201 movs r2, #1
8002818: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
800281c: 687b ldr r3, [r7, #4]
800281e: 2201 movs r2, #1
8002820: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8002824: 2300 movs r3, #0
}
8002826: 4618 mov r0, r3
8002828: 3708 adds r7, #8
800282a: 46bd mov sp, r7
800282c: bd80 pop {r7, pc}
0800282e <HAL_TIM_OC_MspInit>:
* @brief Initializes the TIM Output Compare MSP.
* @param htim TIM Output Compare handle
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
{
800282e: b480 push {r7}
8002830: b083 sub sp, #12
8002832: af00 add r7, sp, #0
8002834: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_MspInit could be implemented in the user file
*/
}
8002836: bf00 nop
8002838: 370c adds r7, #12
800283a: 46bd mov sp, r7
800283c: f85d 7b04 ldr.w r7, [sp], #4
8002840: 4770 bx lr
08002842 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8002842: b580 push {r7, lr}
8002844: b082 sub sp, #8
8002846: af00 add r7, sp, #0
8002848: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800284a: 687b ldr r3, [r7, #4]
800284c: 2b00 cmp r3, #0
800284e: d101 bne.n 8002854 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8002850: 2301 movs r3, #1
8002852: e041 b.n 80028d8 <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002854: 687b ldr r3, [r7, #4]
8002856: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
800285a: b2db uxtb r3, r3
800285c: 2b00 cmp r3, #0
800285e: d106 bne.n 800286e <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002860: 687b ldr r3, [r7, #4]
8002862: 2200 movs r2, #0
8002864: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8002868: 6878 ldr r0, [r7, #4]
800286a: f000 f839 bl 80028e0 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800286e: 687b ldr r3, [r7, #4]
8002870: 2202 movs r2, #2
8002872: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002876: 687b ldr r3, [r7, #4]
8002878: 681a ldr r2, [r3, #0]
800287a: 687b ldr r3, [r7, #4]
800287c: 3304 adds r3, #4
800287e: 4619 mov r1, r3
8002880: 4610 mov r0, r2
8002882: f000 fc8f bl 80031a4 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002886: 687b ldr r3, [r7, #4]
8002888: 2201 movs r2, #1
800288a: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800288e: 687b ldr r3, [r7, #4]
8002890: 2201 movs r2, #1
8002892: f883 203e strb.w r2, [r3, #62] ; 0x3e
8002896: 687b ldr r3, [r7, #4]
8002898: 2201 movs r2, #1
800289a: f883 203f strb.w r2, [r3, #63] ; 0x3f
800289e: 687b ldr r3, [r7, #4]
80028a0: 2201 movs r2, #1
80028a2: f883 2040 strb.w r2, [r3, #64] ; 0x40
80028a6: 687b ldr r3, [r7, #4]
80028a8: 2201 movs r2, #1
80028aa: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80028ae: 687b ldr r3, [r7, #4]
80028b0: 2201 movs r2, #1
80028b2: f883 2042 strb.w r2, [r3, #66] ; 0x42
80028b6: 687b ldr r3, [r7, #4]
80028b8: 2201 movs r2, #1
80028ba: f883 2043 strb.w r2, [r3, #67] ; 0x43
80028be: 687b ldr r3, [r7, #4]
80028c0: 2201 movs r2, #1
80028c2: f883 2044 strb.w r2, [r3, #68] ; 0x44
80028c6: 687b ldr r3, [r7, #4]
80028c8: 2201 movs r2, #1
80028ca: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80028ce: 687b ldr r3, [r7, #4]
80028d0: 2201 movs r2, #1
80028d2: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
80028d6: 2300 movs r3, #0
}
80028d8: 4618 mov r0, r3
80028da: 3708 adds r7, #8
80028dc: 46bd mov sp, r7
80028de: bd80 pop {r7, pc}
080028e0 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
80028e0: b480 push {r7}
80028e2: b083 sub sp, #12
80028e4: af00 add r7, sp, #0
80028e6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
80028e8: bf00 nop
80028ea: 370c adds r7, #12
80028ec: 46bd mov sp, r7
80028ee: f85d 7b04 ldr.w r7, [sp], #4
80028f2: 4770 bx lr
080028f4 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
80028f4: b580 push {r7, lr}
80028f6: b084 sub sp, #16
80028f8: af00 add r7, sp, #0
80028fa: 6078 str r0, [r7, #4]
80028fc: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
80028fe: 683b ldr r3, [r7, #0]
8002900: 2b00 cmp r3, #0
8002902: d109 bne.n 8002918 <HAL_TIM_PWM_Start+0x24>
8002904: 687b ldr r3, [r7, #4]
8002906: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
800290a: b2db uxtb r3, r3
800290c: 2b01 cmp r3, #1
800290e: bf14 ite ne
8002910: 2301 movne r3, #1
8002912: 2300 moveq r3, #0
8002914: b2db uxtb r3, r3
8002916: e022 b.n 800295e <HAL_TIM_PWM_Start+0x6a>
8002918: 683b ldr r3, [r7, #0]
800291a: 2b04 cmp r3, #4
800291c: d109 bne.n 8002932 <HAL_TIM_PWM_Start+0x3e>
800291e: 687b ldr r3, [r7, #4]
8002920: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
8002924: b2db uxtb r3, r3
8002926: 2b01 cmp r3, #1
8002928: bf14 ite ne
800292a: 2301 movne r3, #1
800292c: 2300 moveq r3, #0
800292e: b2db uxtb r3, r3
8002930: e015 b.n 800295e <HAL_TIM_PWM_Start+0x6a>
8002932: 683b ldr r3, [r7, #0]
8002934: 2b08 cmp r3, #8
8002936: d109 bne.n 800294c <HAL_TIM_PWM_Start+0x58>
8002938: 687b ldr r3, [r7, #4]
800293a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
800293e: b2db uxtb r3, r3
8002940: 2b01 cmp r3, #1
8002942: bf14 ite ne
8002944: 2301 movne r3, #1
8002946: 2300 moveq r3, #0
8002948: b2db uxtb r3, r3
800294a: e008 b.n 800295e <HAL_TIM_PWM_Start+0x6a>
800294c: 687b ldr r3, [r7, #4]
800294e: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8002952: b2db uxtb r3, r3
8002954: 2b01 cmp r3, #1
8002956: bf14 ite ne
8002958: 2301 movne r3, #1
800295a: 2300 moveq r3, #0
800295c: b2db uxtb r3, r3
800295e: 2b00 cmp r3, #0
8002960: d001 beq.n 8002966 <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
8002962: 2301 movs r3, #1
8002964: e07c b.n 8002a60 <HAL_TIM_PWM_Start+0x16c>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8002966: 683b ldr r3, [r7, #0]
8002968: 2b00 cmp r3, #0
800296a: d104 bne.n 8002976 <HAL_TIM_PWM_Start+0x82>
800296c: 687b ldr r3, [r7, #4]
800296e: 2202 movs r2, #2
8002970: f883 203e strb.w r2, [r3, #62] ; 0x3e
8002974: e013 b.n 800299e <HAL_TIM_PWM_Start+0xaa>
8002976: 683b ldr r3, [r7, #0]
8002978: 2b04 cmp r3, #4
800297a: d104 bne.n 8002986 <HAL_TIM_PWM_Start+0x92>
800297c: 687b ldr r3, [r7, #4]
800297e: 2202 movs r2, #2
8002980: f883 203f strb.w r2, [r3, #63] ; 0x3f
8002984: e00b b.n 800299e <HAL_TIM_PWM_Start+0xaa>
8002986: 683b ldr r3, [r7, #0]
8002988: 2b08 cmp r3, #8
800298a: d104 bne.n 8002996 <HAL_TIM_PWM_Start+0xa2>
800298c: 687b ldr r3, [r7, #4]
800298e: 2202 movs r2, #2
8002990: f883 2040 strb.w r2, [r3, #64] ; 0x40
8002994: e003 b.n 800299e <HAL_TIM_PWM_Start+0xaa>
8002996: 687b ldr r3, [r7, #4]
8002998: 2202 movs r2, #2
800299a: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
800299e: 687b ldr r3, [r7, #4]
80029a0: 681b ldr r3, [r3, #0]
80029a2: 2201 movs r2, #1
80029a4: 6839 ldr r1, [r7, #0]
80029a6: 4618 mov r0, r3
80029a8: f000 fee6 bl 8003778 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
80029ac: 687b ldr r3, [r7, #4]
80029ae: 681b ldr r3, [r3, #0]
80029b0: 4a2d ldr r2, [pc, #180] ; (8002a68 <HAL_TIM_PWM_Start+0x174>)
80029b2: 4293 cmp r3, r2
80029b4: d004 beq.n 80029c0 <HAL_TIM_PWM_Start+0xcc>
80029b6: 687b ldr r3, [r7, #4]
80029b8: 681b ldr r3, [r3, #0]
80029ba: 4a2c ldr r2, [pc, #176] ; (8002a6c <HAL_TIM_PWM_Start+0x178>)
80029bc: 4293 cmp r3, r2
80029be: d101 bne.n 80029c4 <HAL_TIM_PWM_Start+0xd0>
80029c0: 2301 movs r3, #1
80029c2: e000 b.n 80029c6 <HAL_TIM_PWM_Start+0xd2>
80029c4: 2300 movs r3, #0
80029c6: 2b00 cmp r3, #0
80029c8: d007 beq.n 80029da <HAL_TIM_PWM_Start+0xe6>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
80029ca: 687b ldr r3, [r7, #4]
80029cc: 681b ldr r3, [r3, #0]
80029ce: 6c5a ldr r2, [r3, #68] ; 0x44
80029d0: 687b ldr r3, [r7, #4]
80029d2: 681b ldr r3, [r3, #0]
80029d4: f442 4200 orr.w r2, r2, #32768 ; 0x8000
80029d8: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80029da: 687b ldr r3, [r7, #4]
80029dc: 681b ldr r3, [r3, #0]
80029de: 4a22 ldr r2, [pc, #136] ; (8002a68 <HAL_TIM_PWM_Start+0x174>)
80029e0: 4293 cmp r3, r2
80029e2: d022 beq.n 8002a2a <HAL_TIM_PWM_Start+0x136>
80029e4: 687b ldr r3, [r7, #4]
80029e6: 681b ldr r3, [r3, #0]
80029e8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80029ec: d01d beq.n 8002a2a <HAL_TIM_PWM_Start+0x136>
80029ee: 687b ldr r3, [r7, #4]
80029f0: 681b ldr r3, [r3, #0]
80029f2: 4a1f ldr r2, [pc, #124] ; (8002a70 <HAL_TIM_PWM_Start+0x17c>)
80029f4: 4293 cmp r3, r2
80029f6: d018 beq.n 8002a2a <HAL_TIM_PWM_Start+0x136>
80029f8: 687b ldr r3, [r7, #4]
80029fa: 681b ldr r3, [r3, #0]
80029fc: 4a1d ldr r2, [pc, #116] ; (8002a74 <HAL_TIM_PWM_Start+0x180>)
80029fe: 4293 cmp r3, r2
8002a00: d013 beq.n 8002a2a <HAL_TIM_PWM_Start+0x136>
8002a02: 687b ldr r3, [r7, #4]
8002a04: 681b ldr r3, [r3, #0]
8002a06: 4a1c ldr r2, [pc, #112] ; (8002a78 <HAL_TIM_PWM_Start+0x184>)
8002a08: 4293 cmp r3, r2
8002a0a: d00e beq.n 8002a2a <HAL_TIM_PWM_Start+0x136>
8002a0c: 687b ldr r3, [r7, #4]
8002a0e: 681b ldr r3, [r3, #0]
8002a10: 4a16 ldr r2, [pc, #88] ; (8002a6c <HAL_TIM_PWM_Start+0x178>)
8002a12: 4293 cmp r3, r2
8002a14: d009 beq.n 8002a2a <HAL_TIM_PWM_Start+0x136>
8002a16: 687b ldr r3, [r7, #4]
8002a18: 681b ldr r3, [r3, #0]
8002a1a: 4a18 ldr r2, [pc, #96] ; (8002a7c <HAL_TIM_PWM_Start+0x188>)
8002a1c: 4293 cmp r3, r2
8002a1e: d004 beq.n 8002a2a <HAL_TIM_PWM_Start+0x136>
8002a20: 687b ldr r3, [r7, #4]
8002a22: 681b ldr r3, [r3, #0]
8002a24: 4a16 ldr r2, [pc, #88] ; (8002a80 <HAL_TIM_PWM_Start+0x18c>)
8002a26: 4293 cmp r3, r2
8002a28: d111 bne.n 8002a4e <HAL_TIM_PWM_Start+0x15a>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8002a2a: 687b ldr r3, [r7, #4]
8002a2c: 681b ldr r3, [r3, #0]
8002a2e: 689b ldr r3, [r3, #8]
8002a30: f003 0307 and.w r3, r3, #7
8002a34: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002a36: 68fb ldr r3, [r7, #12]
8002a38: 2b06 cmp r3, #6
8002a3a: d010 beq.n 8002a5e <HAL_TIM_PWM_Start+0x16a>
{
__HAL_TIM_ENABLE(htim);
8002a3c: 687b ldr r3, [r7, #4]
8002a3e: 681b ldr r3, [r3, #0]
8002a40: 681a ldr r2, [r3, #0]
8002a42: 687b ldr r3, [r7, #4]
8002a44: 681b ldr r3, [r3, #0]
8002a46: f042 0201 orr.w r2, r2, #1
8002a4a: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002a4c: e007 b.n 8002a5e <HAL_TIM_PWM_Start+0x16a>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8002a4e: 687b ldr r3, [r7, #4]
8002a50: 681b ldr r3, [r3, #0]
8002a52: 681a ldr r2, [r3, #0]
8002a54: 687b ldr r3, [r7, #4]
8002a56: 681b ldr r3, [r3, #0]
8002a58: f042 0201 orr.w r2, r2, #1
8002a5c: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8002a5e: 2300 movs r3, #0
}
8002a60: 4618 mov r0, r3
8002a62: 3710 adds r7, #16
8002a64: 46bd mov sp, r7
8002a66: bd80 pop {r7, pc}
8002a68: 40010000 .word 0x40010000
8002a6c: 40010400 .word 0x40010400
8002a70: 40000400 .word 0x40000400
8002a74: 40000800 .word 0x40000800
8002a78: 40000c00 .word 0x40000c00
8002a7c: 40014000 .word 0x40014000
8002a80: 40001800 .word 0x40001800
08002a84 <HAL_TIM_PWM_Stop>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8002a84: b580 push {r7, lr}
8002a86: b082 sub sp, #8
8002a88: af00 add r7, sp, #0
8002a8a: 6078 str r0, [r7, #4]
8002a8c: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
8002a8e: 687b ldr r3, [r7, #4]
8002a90: 681b ldr r3, [r3, #0]
8002a92: 2200 movs r2, #0
8002a94: 6839 ldr r1, [r7, #0]
8002a96: 4618 mov r0, r3
8002a98: f000 fe6e bl 8003778 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8002a9c: 687b ldr r3, [r7, #4]
8002a9e: 681b ldr r3, [r3, #0]
8002aa0: 4a2e ldr r2, [pc, #184] ; (8002b5c <HAL_TIM_PWM_Stop+0xd8>)
8002aa2: 4293 cmp r3, r2
8002aa4: d004 beq.n 8002ab0 <HAL_TIM_PWM_Stop+0x2c>
8002aa6: 687b ldr r3, [r7, #4]
8002aa8: 681b ldr r3, [r3, #0]
8002aaa: 4a2d ldr r2, [pc, #180] ; (8002b60 <HAL_TIM_PWM_Stop+0xdc>)
8002aac: 4293 cmp r3, r2
8002aae: d101 bne.n 8002ab4 <HAL_TIM_PWM_Stop+0x30>
8002ab0: 2301 movs r3, #1
8002ab2: e000 b.n 8002ab6 <HAL_TIM_PWM_Stop+0x32>
8002ab4: 2300 movs r3, #0
8002ab6: 2b00 cmp r3, #0
8002ab8: d017 beq.n 8002aea <HAL_TIM_PWM_Stop+0x66>
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
8002aba: 687b ldr r3, [r7, #4]
8002abc: 681b ldr r3, [r3, #0]
8002abe: 6a1a ldr r2, [r3, #32]
8002ac0: f241 1311 movw r3, #4369 ; 0x1111
8002ac4: 4013 ands r3, r2
8002ac6: 2b00 cmp r3, #0
8002ac8: d10f bne.n 8002aea <HAL_TIM_PWM_Stop+0x66>
8002aca: 687b ldr r3, [r7, #4]
8002acc: 681b ldr r3, [r3, #0]
8002ace: 6a1a ldr r2, [r3, #32]
8002ad0: f240 4344 movw r3, #1092 ; 0x444
8002ad4: 4013 ands r3, r2
8002ad6: 2b00 cmp r3, #0
8002ad8: d107 bne.n 8002aea <HAL_TIM_PWM_Stop+0x66>
8002ada: 687b ldr r3, [r7, #4]
8002adc: 681b ldr r3, [r3, #0]
8002ade: 6c5a ldr r2, [r3, #68] ; 0x44
8002ae0: 687b ldr r3, [r7, #4]
8002ae2: 681b ldr r3, [r3, #0]
8002ae4: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8002ae8: 645a str r2, [r3, #68] ; 0x44
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
8002aea: 687b ldr r3, [r7, #4]
8002aec: 681b ldr r3, [r3, #0]
8002aee: 6a1a ldr r2, [r3, #32]
8002af0: f241 1311 movw r3, #4369 ; 0x1111
8002af4: 4013 ands r3, r2
8002af6: 2b00 cmp r3, #0
8002af8: d10f bne.n 8002b1a <HAL_TIM_PWM_Stop+0x96>
8002afa: 687b ldr r3, [r7, #4]
8002afc: 681b ldr r3, [r3, #0]
8002afe: 6a1a ldr r2, [r3, #32]
8002b00: f240 4344 movw r3, #1092 ; 0x444
8002b04: 4013 ands r3, r2
8002b06: 2b00 cmp r3, #0
8002b08: d107 bne.n 8002b1a <HAL_TIM_PWM_Stop+0x96>
8002b0a: 687b ldr r3, [r7, #4]
8002b0c: 681b ldr r3, [r3, #0]
8002b0e: 681a ldr r2, [r3, #0]
8002b10: 687b ldr r3, [r7, #4]
8002b12: 681b ldr r3, [r3, #0]
8002b14: f022 0201 bic.w r2, r2, #1
8002b18: 601a str r2, [r3, #0]
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
8002b1a: 683b ldr r3, [r7, #0]
8002b1c: 2b00 cmp r3, #0
8002b1e: d104 bne.n 8002b2a <HAL_TIM_PWM_Stop+0xa6>
8002b20: 687b ldr r3, [r7, #4]
8002b22: 2201 movs r2, #1
8002b24: f883 203e strb.w r2, [r3, #62] ; 0x3e
8002b28: e013 b.n 8002b52 <HAL_TIM_PWM_Stop+0xce>
8002b2a: 683b ldr r3, [r7, #0]
8002b2c: 2b04 cmp r3, #4
8002b2e: d104 bne.n 8002b3a <HAL_TIM_PWM_Stop+0xb6>
8002b30: 687b ldr r3, [r7, #4]
8002b32: 2201 movs r2, #1
8002b34: f883 203f strb.w r2, [r3, #63] ; 0x3f
8002b38: e00b b.n 8002b52 <HAL_TIM_PWM_Stop+0xce>
8002b3a: 683b ldr r3, [r7, #0]
8002b3c: 2b08 cmp r3, #8
8002b3e: d104 bne.n 8002b4a <HAL_TIM_PWM_Stop+0xc6>
8002b40: 687b ldr r3, [r7, #4]
8002b42: 2201 movs r2, #1
8002b44: f883 2040 strb.w r2, [r3, #64] ; 0x40
8002b48: e003 b.n 8002b52 <HAL_TIM_PWM_Stop+0xce>
8002b4a: 687b ldr r3, [r7, #4]
8002b4c: 2201 movs r2, #1
8002b4e: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Return function status */
return HAL_OK;
8002b52: 2300 movs r3, #0
}
8002b54: 4618 mov r0, r3
8002b56: 3708 adds r7, #8
8002b58: 46bd mov sp, r7
8002b5a: bd80 pop {r7, pc}
8002b5c: 40010000 .word 0x40010000
8002b60: 40010400 .word 0x40010400
08002b64 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8002b64: b580 push {r7, lr}
8002b66: b082 sub sp, #8
8002b68: af00 add r7, sp, #0
8002b6a: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8002b6c: 687b ldr r3, [r7, #4]
8002b6e: 681b ldr r3, [r3, #0]
8002b70: 691b ldr r3, [r3, #16]
8002b72: f003 0302 and.w r3, r3, #2
8002b76: 2b02 cmp r3, #2
8002b78: d122 bne.n 8002bc0 <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8002b7a: 687b ldr r3, [r7, #4]
8002b7c: 681b ldr r3, [r3, #0]
8002b7e: 68db ldr r3, [r3, #12]
8002b80: f003 0302 and.w r3, r3, #2
8002b84: 2b02 cmp r3, #2
8002b86: d11b bne.n 8002bc0 <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8002b88: 687b ldr r3, [r7, #4]
8002b8a: 681b ldr r3, [r3, #0]
8002b8c: f06f 0202 mvn.w r2, #2
8002b90: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8002b92: 687b ldr r3, [r7, #4]
8002b94: 2201 movs r2, #1
8002b96: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8002b98: 687b ldr r3, [r7, #4]
8002b9a: 681b ldr r3, [r3, #0]
8002b9c: 699b ldr r3, [r3, #24]
8002b9e: f003 0303 and.w r3, r3, #3
8002ba2: 2b00 cmp r3, #0
8002ba4: d003 beq.n 8002bae <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002ba6: 6878 ldr r0, [r7, #4]
8002ba8: f000 fadd bl 8003166 <HAL_TIM_IC_CaptureCallback>
8002bac: e005 b.n 8002bba <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002bae: 6878 ldr r0, [r7, #4]
8002bb0: f000 facf bl 8003152 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002bb4: 6878 ldr r0, [r7, #4]
8002bb6: f000 fae0 bl 800317a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002bba: 687b ldr r3, [r7, #4]
8002bbc: 2200 movs r2, #0
8002bbe: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8002bc0: 687b ldr r3, [r7, #4]
8002bc2: 681b ldr r3, [r3, #0]
8002bc4: 691b ldr r3, [r3, #16]
8002bc6: f003 0304 and.w r3, r3, #4
8002bca: 2b04 cmp r3, #4
8002bcc: d122 bne.n 8002c14 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8002bce: 687b ldr r3, [r7, #4]
8002bd0: 681b ldr r3, [r3, #0]
8002bd2: 68db ldr r3, [r3, #12]
8002bd4: f003 0304 and.w r3, r3, #4
8002bd8: 2b04 cmp r3, #4
8002bda: d11b bne.n 8002c14 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8002bdc: 687b ldr r3, [r7, #4]
8002bde: 681b ldr r3, [r3, #0]
8002be0: f06f 0204 mvn.w r2, #4
8002be4: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8002be6: 687b ldr r3, [r7, #4]
8002be8: 2202 movs r2, #2
8002bea: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8002bec: 687b ldr r3, [r7, #4]
8002bee: 681b ldr r3, [r3, #0]
8002bf0: 699b ldr r3, [r3, #24]
8002bf2: f403 7340 and.w r3, r3, #768 ; 0x300
8002bf6: 2b00 cmp r3, #0
8002bf8: d003 beq.n 8002c02 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002bfa: 6878 ldr r0, [r7, #4]
8002bfc: f000 fab3 bl 8003166 <HAL_TIM_IC_CaptureCallback>
8002c00: e005 b.n 8002c0e <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002c02: 6878 ldr r0, [r7, #4]
8002c04: f000 faa5 bl 8003152 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002c08: 6878 ldr r0, [r7, #4]
8002c0a: f000 fab6 bl 800317a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002c0e: 687b ldr r3, [r7, #4]
8002c10: 2200 movs r2, #0
8002c12: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8002c14: 687b ldr r3, [r7, #4]
8002c16: 681b ldr r3, [r3, #0]
8002c18: 691b ldr r3, [r3, #16]
8002c1a: f003 0308 and.w r3, r3, #8
8002c1e: 2b08 cmp r3, #8
8002c20: d122 bne.n 8002c68 <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8002c22: 687b ldr r3, [r7, #4]
8002c24: 681b ldr r3, [r3, #0]
8002c26: 68db ldr r3, [r3, #12]
8002c28: f003 0308 and.w r3, r3, #8
8002c2c: 2b08 cmp r3, #8
8002c2e: d11b bne.n 8002c68 <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8002c30: 687b ldr r3, [r7, #4]
8002c32: 681b ldr r3, [r3, #0]
8002c34: f06f 0208 mvn.w r2, #8
8002c38: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8002c3a: 687b ldr r3, [r7, #4]
8002c3c: 2204 movs r2, #4
8002c3e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8002c40: 687b ldr r3, [r7, #4]
8002c42: 681b ldr r3, [r3, #0]
8002c44: 69db ldr r3, [r3, #28]
8002c46: f003 0303 and.w r3, r3, #3
8002c4a: 2b00 cmp r3, #0
8002c4c: d003 beq.n 8002c56 <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002c4e: 6878 ldr r0, [r7, #4]
8002c50: f000 fa89 bl 8003166 <HAL_TIM_IC_CaptureCallback>
8002c54: e005 b.n 8002c62 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002c56: 6878 ldr r0, [r7, #4]
8002c58: f000 fa7b bl 8003152 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002c5c: 6878 ldr r0, [r7, #4]
8002c5e: f000 fa8c bl 800317a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002c62: 687b ldr r3, [r7, #4]
8002c64: 2200 movs r2, #0
8002c66: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8002c68: 687b ldr r3, [r7, #4]
8002c6a: 681b ldr r3, [r3, #0]
8002c6c: 691b ldr r3, [r3, #16]
8002c6e: f003 0310 and.w r3, r3, #16
8002c72: 2b10 cmp r3, #16
8002c74: d122 bne.n 8002cbc <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8002c76: 687b ldr r3, [r7, #4]
8002c78: 681b ldr r3, [r3, #0]
8002c7a: 68db ldr r3, [r3, #12]
8002c7c: f003 0310 and.w r3, r3, #16
8002c80: 2b10 cmp r3, #16
8002c82: d11b bne.n 8002cbc <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8002c84: 687b ldr r3, [r7, #4]
8002c86: 681b ldr r3, [r3, #0]
8002c88: f06f 0210 mvn.w r2, #16
8002c8c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8002c8e: 687b ldr r3, [r7, #4]
8002c90: 2208 movs r2, #8
8002c92: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8002c94: 687b ldr r3, [r7, #4]
8002c96: 681b ldr r3, [r3, #0]
8002c98: 69db ldr r3, [r3, #28]
8002c9a: f403 7340 and.w r3, r3, #768 ; 0x300
8002c9e: 2b00 cmp r3, #0
8002ca0: d003 beq.n 8002caa <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002ca2: 6878 ldr r0, [r7, #4]
8002ca4: f000 fa5f bl 8003166 <HAL_TIM_IC_CaptureCallback>
8002ca8: e005 b.n 8002cb6 <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002caa: 6878 ldr r0, [r7, #4]
8002cac: f000 fa51 bl 8003152 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002cb0: 6878 ldr r0, [r7, #4]
8002cb2: f000 fa62 bl 800317a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002cb6: 687b ldr r3, [r7, #4]
8002cb8: 2200 movs r2, #0
8002cba: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8002cbc: 687b ldr r3, [r7, #4]
8002cbe: 681b ldr r3, [r3, #0]
8002cc0: 691b ldr r3, [r3, #16]
8002cc2: f003 0301 and.w r3, r3, #1
8002cc6: 2b01 cmp r3, #1
8002cc8: d10e bne.n 8002ce8 <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8002cca: 687b ldr r3, [r7, #4]
8002ccc: 681b ldr r3, [r3, #0]
8002cce: 68db ldr r3, [r3, #12]
8002cd0: f003 0301 and.w r3, r3, #1
8002cd4: 2b01 cmp r3, #1
8002cd6: d107 bne.n 8002ce8 <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8002cd8: 687b ldr r3, [r7, #4]
8002cda: 681b ldr r3, [r3, #0]
8002cdc: f06f 0201 mvn.w r2, #1
8002ce0: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8002ce2: 6878 ldr r0, [r7, #4]
8002ce4: f000 fa2b bl 800313e <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8002ce8: 687b ldr r3, [r7, #4]
8002cea: 681b ldr r3, [r3, #0]
8002cec: 691b ldr r3, [r3, #16]
8002cee: f003 0380 and.w r3, r3, #128 ; 0x80
8002cf2: 2b80 cmp r3, #128 ; 0x80
8002cf4: d10e bne.n 8002d14 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8002cf6: 687b ldr r3, [r7, #4]
8002cf8: 681b ldr r3, [r3, #0]
8002cfa: 68db ldr r3, [r3, #12]
8002cfc: f003 0380 and.w r3, r3, #128 ; 0x80
8002d00: 2b80 cmp r3, #128 ; 0x80
8002d02: d107 bne.n 8002d14 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8002d04: 687b ldr r3, [r7, #4]
8002d06: 681b ldr r3, [r3, #0]
8002d08: f06f 0280 mvn.w r2, #128 ; 0x80
8002d0c: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8002d0e: 6878 ldr r0, [r7, #4]
8002d10: f000 fe30 bl 8003974 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8002d14: 687b ldr r3, [r7, #4]
8002d16: 681b ldr r3, [r3, #0]
8002d18: 691b ldr r3, [r3, #16]
8002d1a: f003 0340 and.w r3, r3, #64 ; 0x40
8002d1e: 2b40 cmp r3, #64 ; 0x40
8002d20: d10e bne.n 8002d40 <HAL_TIM_IRQHandler+0x1dc>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8002d22: 687b ldr r3, [r7, #4]
8002d24: 681b ldr r3, [r3, #0]
8002d26: 68db ldr r3, [r3, #12]
8002d28: f003 0340 and.w r3, r3, #64 ; 0x40
8002d2c: 2b40 cmp r3, #64 ; 0x40
8002d2e: d107 bne.n 8002d40 <HAL_TIM_IRQHandler+0x1dc>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8002d30: 687b ldr r3, [r7, #4]
8002d32: 681b ldr r3, [r3, #0]
8002d34: f06f 0240 mvn.w r2, #64 ; 0x40
8002d38: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8002d3a: 6878 ldr r0, [r7, #4]
8002d3c: f000 fa27 bl 800318e <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8002d40: 687b ldr r3, [r7, #4]
8002d42: 681b ldr r3, [r3, #0]
8002d44: 691b ldr r3, [r3, #16]
8002d46: f003 0320 and.w r3, r3, #32
8002d4a: 2b20 cmp r3, #32
8002d4c: d10e bne.n 8002d6c <HAL_TIM_IRQHandler+0x208>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8002d4e: 687b ldr r3, [r7, #4]
8002d50: 681b ldr r3, [r3, #0]
8002d52: 68db ldr r3, [r3, #12]
8002d54: f003 0320 and.w r3, r3, #32
8002d58: 2b20 cmp r3, #32
8002d5a: d107 bne.n 8002d6c <HAL_TIM_IRQHandler+0x208>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8002d5c: 687b ldr r3, [r7, #4]
8002d5e: 681b ldr r3, [r3, #0]
8002d60: f06f 0220 mvn.w r2, #32
8002d64: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8002d66: 6878 ldr r0, [r7, #4]
8002d68: f000 fdfa bl 8003960 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8002d6c: bf00 nop
8002d6e: 3708 adds r7, #8
8002d70: 46bd mov sp, r7
8002d72: bd80 pop {r7, pc}
08002d74 <HAL_TIM_OC_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8002d74: b580 push {r7, lr}
8002d76: b086 sub sp, #24
8002d78: af00 add r7, sp, #0
8002d7a: 60f8 str r0, [r7, #12]
8002d7c: 60b9 str r1, [r7, #8]
8002d7e: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8002d80: 2300 movs r3, #0
8002d82: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
/* Process Locked */
__HAL_LOCK(htim);
8002d84: 68fb ldr r3, [r7, #12]
8002d86: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002d8a: 2b01 cmp r3, #1
8002d8c: d101 bne.n 8002d92 <HAL_TIM_OC_ConfigChannel+0x1e>
8002d8e: 2302 movs r3, #2
8002d90: e048 b.n 8002e24 <HAL_TIM_OC_ConfigChannel+0xb0>
8002d92: 68fb ldr r3, [r7, #12]
8002d94: 2201 movs r2, #1
8002d96: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
8002d9a: 687b ldr r3, [r7, #4]
8002d9c: 2b0c cmp r3, #12
8002d9e: d839 bhi.n 8002e14 <HAL_TIM_OC_ConfigChannel+0xa0>
8002da0: a201 add r2, pc, #4 ; (adr r2, 8002da8 <HAL_TIM_OC_ConfigChannel+0x34>)
8002da2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002da6: bf00 nop
8002da8: 08002ddd .word 0x08002ddd
8002dac: 08002e15 .word 0x08002e15
8002db0: 08002e15 .word 0x08002e15
8002db4: 08002e15 .word 0x08002e15
8002db8: 08002deb .word 0x08002deb
8002dbc: 08002e15 .word 0x08002e15
8002dc0: 08002e15 .word 0x08002e15
8002dc4: 08002e15 .word 0x08002e15
8002dc8: 08002df9 .word 0x08002df9
8002dcc: 08002e15 .word 0x08002e15
8002dd0: 08002e15 .word 0x08002e15
8002dd4: 08002e15 .word 0x08002e15
8002dd8: 08002e07 .word 0x08002e07
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the TIM Channel 1 in Output Compare */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8002ddc: 68fb ldr r3, [r7, #12]
8002dde: 681b ldr r3, [r3, #0]
8002de0: 68b9 ldr r1, [r7, #8]
8002de2: 4618 mov r0, r3
8002de4: f000 fa7e bl 80032e4 <TIM_OC1_SetConfig>
break;
8002de8: e017 b.n 8002e1a <HAL_TIM_OC_ConfigChannel+0xa6>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the TIM Channel 2 in Output Compare */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8002dea: 68fb ldr r3, [r7, #12]
8002dec: 681b ldr r3, [r3, #0]
8002dee: 68b9 ldr r1, [r7, #8]
8002df0: 4618 mov r0, r3
8002df2: f000 fae7 bl 80033c4 <TIM_OC2_SetConfig>
break;
8002df6: e010 b.n 8002e1a <HAL_TIM_OC_ConfigChannel+0xa6>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the TIM Channel 3 in Output Compare */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8002df8: 68fb ldr r3, [r7, #12]
8002dfa: 681b ldr r3, [r3, #0]
8002dfc: 68b9 ldr r1, [r7, #8]
8002dfe: 4618 mov r0, r3
8002e00: f000 fb56 bl 80034b0 <TIM_OC3_SetConfig>
break;
8002e04: e009 b.n 8002e1a <HAL_TIM_OC_ConfigChannel+0xa6>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the TIM Channel 4 in Output Compare */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8002e06: 68fb ldr r3, [r7, #12]
8002e08: 681b ldr r3, [r3, #0]
8002e0a: 68b9 ldr r1, [r7, #8]
8002e0c: 4618 mov r0, r3
8002e0e: f000 fbc3 bl 8003598 <TIM_OC4_SetConfig>
break;
8002e12: e002 b.n 8002e1a <HAL_TIM_OC_ConfigChannel+0xa6>
}
default:
status = HAL_ERROR;
8002e14: 2301 movs r3, #1
8002e16: 75fb strb r3, [r7, #23]
break;
8002e18: bf00 nop
}
__HAL_UNLOCK(htim);
8002e1a: 68fb ldr r3, [r7, #12]
8002e1c: 2200 movs r2, #0
8002e1e: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
8002e22: 7dfb ldrb r3, [r7, #23]
}
8002e24: 4618 mov r0, r3
8002e26: 3718 adds r7, #24
8002e28: 46bd mov sp, r7
8002e2a: bd80 pop {r7, pc}
08002e2c <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8002e2c: b580 push {r7, lr}
8002e2e: b086 sub sp, #24
8002e30: af00 add r7, sp, #0
8002e32: 60f8 str r0, [r7, #12]
8002e34: 60b9 str r1, [r7, #8]
8002e36: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8002e38: 2300 movs r3, #0
8002e3a: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8002e3c: 68fb ldr r3, [r7, #12]
8002e3e: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002e42: 2b01 cmp r3, #1
8002e44: d101 bne.n 8002e4a <HAL_TIM_PWM_ConfigChannel+0x1e>
8002e46: 2302 movs r3, #2
8002e48: e0ae b.n 8002fa8 <HAL_TIM_PWM_ConfigChannel+0x17c>
8002e4a: 68fb ldr r3, [r7, #12]
8002e4c: 2201 movs r2, #1
8002e4e: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
8002e52: 687b ldr r3, [r7, #4]
8002e54: 2b0c cmp r3, #12
8002e56: f200 809f bhi.w 8002f98 <HAL_TIM_PWM_ConfigChannel+0x16c>
8002e5a: a201 add r2, pc, #4 ; (adr r2, 8002e60 <HAL_TIM_PWM_ConfigChannel+0x34>)
8002e5c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002e60: 08002e95 .word 0x08002e95
8002e64: 08002f99 .word 0x08002f99
8002e68: 08002f99 .word 0x08002f99
8002e6c: 08002f99 .word 0x08002f99
8002e70: 08002ed5 .word 0x08002ed5
8002e74: 08002f99 .word 0x08002f99
8002e78: 08002f99 .word 0x08002f99
8002e7c: 08002f99 .word 0x08002f99
8002e80: 08002f17 .word 0x08002f17
8002e84: 08002f99 .word 0x08002f99
8002e88: 08002f99 .word 0x08002f99
8002e8c: 08002f99 .word 0x08002f99
8002e90: 08002f57 .word 0x08002f57
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8002e94: 68fb ldr r3, [r7, #12]
8002e96: 681b ldr r3, [r3, #0]
8002e98: 68b9 ldr r1, [r7, #8]
8002e9a: 4618 mov r0, r3
8002e9c: f000 fa22 bl 80032e4 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8002ea0: 68fb ldr r3, [r7, #12]
8002ea2: 681b ldr r3, [r3, #0]
8002ea4: 699a ldr r2, [r3, #24]
8002ea6: 68fb ldr r3, [r7, #12]
8002ea8: 681b ldr r3, [r3, #0]
8002eaa: f042 0208 orr.w r2, r2, #8
8002eae: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8002eb0: 68fb ldr r3, [r7, #12]
8002eb2: 681b ldr r3, [r3, #0]
8002eb4: 699a ldr r2, [r3, #24]
8002eb6: 68fb ldr r3, [r7, #12]
8002eb8: 681b ldr r3, [r3, #0]
8002eba: f022 0204 bic.w r2, r2, #4
8002ebe: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8002ec0: 68fb ldr r3, [r7, #12]
8002ec2: 681b ldr r3, [r3, #0]
8002ec4: 6999 ldr r1, [r3, #24]
8002ec6: 68bb ldr r3, [r7, #8]
8002ec8: 691a ldr r2, [r3, #16]
8002eca: 68fb ldr r3, [r7, #12]
8002ecc: 681b ldr r3, [r3, #0]
8002ece: 430a orrs r2, r1
8002ed0: 619a str r2, [r3, #24]
break;
8002ed2: e064 b.n 8002f9e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8002ed4: 68fb ldr r3, [r7, #12]
8002ed6: 681b ldr r3, [r3, #0]
8002ed8: 68b9 ldr r1, [r7, #8]
8002eda: 4618 mov r0, r3
8002edc: f000 fa72 bl 80033c4 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8002ee0: 68fb ldr r3, [r7, #12]
8002ee2: 681b ldr r3, [r3, #0]
8002ee4: 699a ldr r2, [r3, #24]
8002ee6: 68fb ldr r3, [r7, #12]
8002ee8: 681b ldr r3, [r3, #0]
8002eea: f442 6200 orr.w r2, r2, #2048 ; 0x800
8002eee: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8002ef0: 68fb ldr r3, [r7, #12]
8002ef2: 681b ldr r3, [r3, #0]
8002ef4: 699a ldr r2, [r3, #24]
8002ef6: 68fb ldr r3, [r7, #12]
8002ef8: 681b ldr r3, [r3, #0]
8002efa: f422 6280 bic.w r2, r2, #1024 ; 0x400
8002efe: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8002f00: 68fb ldr r3, [r7, #12]
8002f02: 681b ldr r3, [r3, #0]
8002f04: 6999 ldr r1, [r3, #24]
8002f06: 68bb ldr r3, [r7, #8]
8002f08: 691b ldr r3, [r3, #16]
8002f0a: 021a lsls r2, r3, #8
8002f0c: 68fb ldr r3, [r7, #12]
8002f0e: 681b ldr r3, [r3, #0]
8002f10: 430a orrs r2, r1
8002f12: 619a str r2, [r3, #24]
break;
8002f14: e043 b.n 8002f9e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8002f16: 68fb ldr r3, [r7, #12]
8002f18: 681b ldr r3, [r3, #0]
8002f1a: 68b9 ldr r1, [r7, #8]
8002f1c: 4618 mov r0, r3
8002f1e: f000 fac7 bl 80034b0 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8002f22: 68fb ldr r3, [r7, #12]
8002f24: 681b ldr r3, [r3, #0]
8002f26: 69da ldr r2, [r3, #28]
8002f28: 68fb ldr r3, [r7, #12]
8002f2a: 681b ldr r3, [r3, #0]
8002f2c: f042 0208 orr.w r2, r2, #8
8002f30: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8002f32: 68fb ldr r3, [r7, #12]
8002f34: 681b ldr r3, [r3, #0]
8002f36: 69da ldr r2, [r3, #28]
8002f38: 68fb ldr r3, [r7, #12]
8002f3a: 681b ldr r3, [r3, #0]
8002f3c: f022 0204 bic.w r2, r2, #4
8002f40: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8002f42: 68fb ldr r3, [r7, #12]
8002f44: 681b ldr r3, [r3, #0]
8002f46: 69d9 ldr r1, [r3, #28]
8002f48: 68bb ldr r3, [r7, #8]
8002f4a: 691a ldr r2, [r3, #16]
8002f4c: 68fb ldr r3, [r7, #12]
8002f4e: 681b ldr r3, [r3, #0]
8002f50: 430a orrs r2, r1
8002f52: 61da str r2, [r3, #28]
break;
8002f54: e023 b.n 8002f9e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8002f56: 68fb ldr r3, [r7, #12]
8002f58: 681b ldr r3, [r3, #0]
8002f5a: 68b9 ldr r1, [r7, #8]
8002f5c: 4618 mov r0, r3
8002f5e: f000 fb1b bl 8003598 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8002f62: 68fb ldr r3, [r7, #12]
8002f64: 681b ldr r3, [r3, #0]
8002f66: 69da ldr r2, [r3, #28]
8002f68: 68fb ldr r3, [r7, #12]
8002f6a: 681b ldr r3, [r3, #0]
8002f6c: f442 6200 orr.w r2, r2, #2048 ; 0x800
8002f70: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8002f72: 68fb ldr r3, [r7, #12]
8002f74: 681b ldr r3, [r3, #0]
8002f76: 69da ldr r2, [r3, #28]
8002f78: 68fb ldr r3, [r7, #12]
8002f7a: 681b ldr r3, [r3, #0]
8002f7c: f422 6280 bic.w r2, r2, #1024 ; 0x400
8002f80: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8002f82: 68fb ldr r3, [r7, #12]
8002f84: 681b ldr r3, [r3, #0]
8002f86: 69d9 ldr r1, [r3, #28]
8002f88: 68bb ldr r3, [r7, #8]
8002f8a: 691b ldr r3, [r3, #16]
8002f8c: 021a lsls r2, r3, #8
8002f8e: 68fb ldr r3, [r7, #12]
8002f90: 681b ldr r3, [r3, #0]
8002f92: 430a orrs r2, r1
8002f94: 61da str r2, [r3, #28]
break;
8002f96: e002 b.n 8002f9e <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
8002f98: 2301 movs r3, #1
8002f9a: 75fb strb r3, [r7, #23]
break;
8002f9c: bf00 nop
}
__HAL_UNLOCK(htim);
8002f9e: 68fb ldr r3, [r7, #12]
8002fa0: 2200 movs r2, #0
8002fa2: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
8002fa6: 7dfb ldrb r3, [r7, #23]
}
8002fa8: 4618 mov r0, r3
8002faa: 3718 adds r7, #24
8002fac: 46bd mov sp, r7
8002fae: bd80 pop {r7, pc}
08002fb0 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8002fb0: b580 push {r7, lr}
8002fb2: b084 sub sp, #16
8002fb4: af00 add r7, sp, #0
8002fb6: 6078 str r0, [r7, #4]
8002fb8: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8002fba: 2300 movs r3, #0
8002fbc: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
8002fbe: 687b ldr r3, [r7, #4]
8002fc0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002fc4: 2b01 cmp r3, #1
8002fc6: d101 bne.n 8002fcc <HAL_TIM_ConfigClockSource+0x1c>
8002fc8: 2302 movs r3, #2
8002fca: e0b4 b.n 8003136 <HAL_TIM_ConfigClockSource+0x186>
8002fcc: 687b ldr r3, [r7, #4]
8002fce: 2201 movs r2, #1
8002fd0: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8002fd4: 687b ldr r3, [r7, #4]
8002fd6: 2202 movs r2, #2
8002fd8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8002fdc: 687b ldr r3, [r7, #4]
8002fde: 681b ldr r3, [r3, #0]
8002fe0: 689b ldr r3, [r3, #8]
8002fe2: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8002fe4: 68bb ldr r3, [r7, #8]
8002fe6: f023 0377 bic.w r3, r3, #119 ; 0x77
8002fea: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8002fec: 68bb ldr r3, [r7, #8]
8002fee: f423 437f bic.w r3, r3, #65280 ; 0xff00
8002ff2: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8002ff4: 687b ldr r3, [r7, #4]
8002ff6: 681b ldr r3, [r3, #0]
8002ff8: 68ba ldr r2, [r7, #8]
8002ffa: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8002ffc: 683b ldr r3, [r7, #0]
8002ffe: 681b ldr r3, [r3, #0]
8003000: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8003004: d03e beq.n 8003084 <HAL_TIM_ConfigClockSource+0xd4>
8003006: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800300a: f200 8087 bhi.w 800311c <HAL_TIM_ConfigClockSource+0x16c>
800300e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8003012: f000 8086 beq.w 8003122 <HAL_TIM_ConfigClockSource+0x172>
8003016: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800301a: d87f bhi.n 800311c <HAL_TIM_ConfigClockSource+0x16c>
800301c: 2b70 cmp r3, #112 ; 0x70
800301e: d01a beq.n 8003056 <HAL_TIM_ConfigClockSource+0xa6>
8003020: 2b70 cmp r3, #112 ; 0x70
8003022: d87b bhi.n 800311c <HAL_TIM_ConfigClockSource+0x16c>
8003024: 2b60 cmp r3, #96 ; 0x60
8003026: d050 beq.n 80030ca <HAL_TIM_ConfigClockSource+0x11a>
8003028: 2b60 cmp r3, #96 ; 0x60
800302a: d877 bhi.n 800311c <HAL_TIM_ConfigClockSource+0x16c>
800302c: 2b50 cmp r3, #80 ; 0x50
800302e: d03c beq.n 80030aa <HAL_TIM_ConfigClockSource+0xfa>
8003030: 2b50 cmp r3, #80 ; 0x50
8003032: d873 bhi.n 800311c <HAL_TIM_ConfigClockSource+0x16c>
8003034: 2b40 cmp r3, #64 ; 0x40
8003036: d058 beq.n 80030ea <HAL_TIM_ConfigClockSource+0x13a>
8003038: 2b40 cmp r3, #64 ; 0x40
800303a: d86f bhi.n 800311c <HAL_TIM_ConfigClockSource+0x16c>
800303c: 2b30 cmp r3, #48 ; 0x30
800303e: d064 beq.n 800310a <HAL_TIM_ConfigClockSource+0x15a>
8003040: 2b30 cmp r3, #48 ; 0x30
8003042: d86b bhi.n 800311c <HAL_TIM_ConfigClockSource+0x16c>
8003044: 2b20 cmp r3, #32
8003046: d060 beq.n 800310a <HAL_TIM_ConfigClockSource+0x15a>
8003048: 2b20 cmp r3, #32
800304a: d867 bhi.n 800311c <HAL_TIM_ConfigClockSource+0x16c>
800304c: 2b00 cmp r3, #0
800304e: d05c beq.n 800310a <HAL_TIM_ConfigClockSource+0x15a>
8003050: 2b10 cmp r3, #16
8003052: d05a beq.n 800310a <HAL_TIM_ConfigClockSource+0x15a>
8003054: e062 b.n 800311c <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8003056: 687b ldr r3, [r7, #4]
8003058: 6818 ldr r0, [r3, #0]
800305a: 683b ldr r3, [r7, #0]
800305c: 6899 ldr r1, [r3, #8]
800305e: 683b ldr r3, [r7, #0]
8003060: 685a ldr r2, [r3, #4]
8003062: 683b ldr r3, [r7, #0]
8003064: 68db ldr r3, [r3, #12]
8003066: f000 fb67 bl 8003738 <TIM_ETR_SetConfig>
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
800306a: 687b ldr r3, [r7, #4]
800306c: 681b ldr r3, [r3, #0]
800306e: 689b ldr r3, [r3, #8]
8003070: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8003072: 68bb ldr r3, [r7, #8]
8003074: f043 0377 orr.w r3, r3, #119 ; 0x77
8003078: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800307a: 687b ldr r3, [r7, #4]
800307c: 681b ldr r3, [r3, #0]
800307e: 68ba ldr r2, [r7, #8]
8003080: 609a str r2, [r3, #8]
break;
8003082: e04f b.n 8003124 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8003084: 687b ldr r3, [r7, #4]
8003086: 6818 ldr r0, [r3, #0]
8003088: 683b ldr r3, [r7, #0]
800308a: 6899 ldr r1, [r3, #8]
800308c: 683b ldr r3, [r7, #0]
800308e: 685a ldr r2, [r3, #4]
8003090: 683b ldr r3, [r7, #0]
8003092: 68db ldr r3, [r3, #12]
8003094: f000 fb50 bl 8003738 <TIM_ETR_SetConfig>
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8003098: 687b ldr r3, [r7, #4]
800309a: 681b ldr r3, [r3, #0]
800309c: 689a ldr r2, [r3, #8]
800309e: 687b ldr r3, [r7, #4]
80030a0: 681b ldr r3, [r3, #0]
80030a2: f442 4280 orr.w r2, r2, #16384 ; 0x4000
80030a6: 609a str r2, [r3, #8]
break;
80030a8: e03c b.n 8003124 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80030aa: 687b ldr r3, [r7, #4]
80030ac: 6818 ldr r0, [r3, #0]
80030ae: 683b ldr r3, [r7, #0]
80030b0: 6859 ldr r1, [r3, #4]
80030b2: 683b ldr r3, [r7, #0]
80030b4: 68db ldr r3, [r3, #12]
80030b6: 461a mov r2, r3
80030b8: f000 fac4 bl 8003644 <TIM_TI1_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
80030bc: 687b ldr r3, [r7, #4]
80030be: 681b ldr r3, [r3, #0]
80030c0: 2150 movs r1, #80 ; 0x50
80030c2: 4618 mov r0, r3
80030c4: f000 fb1d bl 8003702 <TIM_ITRx_SetConfig>
break;
80030c8: e02c b.n 8003124 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
80030ca: 687b ldr r3, [r7, #4]
80030cc: 6818 ldr r0, [r3, #0]
80030ce: 683b ldr r3, [r7, #0]
80030d0: 6859 ldr r1, [r3, #4]
80030d2: 683b ldr r3, [r7, #0]
80030d4: 68db ldr r3, [r3, #12]
80030d6: 461a mov r2, r3
80030d8: f000 fae3 bl 80036a2 <TIM_TI2_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
80030dc: 687b ldr r3, [r7, #4]
80030de: 681b ldr r3, [r3, #0]
80030e0: 2160 movs r1, #96 ; 0x60
80030e2: 4618 mov r0, r3
80030e4: f000 fb0d bl 8003702 <TIM_ITRx_SetConfig>
break;
80030e8: e01c b.n 8003124 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80030ea: 687b ldr r3, [r7, #4]
80030ec: 6818 ldr r0, [r3, #0]
80030ee: 683b ldr r3, [r7, #0]
80030f0: 6859 ldr r1, [r3, #4]
80030f2: 683b ldr r3, [r7, #0]
80030f4: 68db ldr r3, [r3, #12]
80030f6: 461a mov r2, r3
80030f8: f000 faa4 bl 8003644 <TIM_TI1_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
80030fc: 687b ldr r3, [r7, #4]
80030fe: 681b ldr r3, [r3, #0]
8003100: 2140 movs r1, #64 ; 0x40
8003102: 4618 mov r0, r3
8003104: f000 fafd bl 8003702 <TIM_ITRx_SetConfig>
break;
8003108: e00c b.n 8003124 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
800310a: 687b ldr r3, [r7, #4]
800310c: 681a ldr r2, [r3, #0]
800310e: 683b ldr r3, [r7, #0]
8003110: 681b ldr r3, [r3, #0]
8003112: 4619 mov r1, r3
8003114: 4610 mov r0, r2
8003116: f000 faf4 bl 8003702 <TIM_ITRx_SetConfig>
break;
800311a: e003 b.n 8003124 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
800311c: 2301 movs r3, #1
800311e: 73fb strb r3, [r7, #15]
break;
8003120: e000 b.n 8003124 <HAL_TIM_ConfigClockSource+0x174>
break;
8003122: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8003124: 687b ldr r3, [r7, #4]
8003126: 2201 movs r2, #1
8003128: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800312c: 687b ldr r3, [r7, #4]
800312e: 2200 movs r2, #0
8003130: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
8003134: 7bfb ldrb r3, [r7, #15]
}
8003136: 4618 mov r0, r3
8003138: 3710 adds r7, #16
800313a: 46bd mov sp, r7
800313c: bd80 pop {r7, pc}
0800313e <HAL_TIM_PeriodElapsedCallback>:
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
800313e: b480 push {r7}
8003140: b083 sub sp, #12
8003142: af00 add r7, sp, #0
8003144: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
8003146: bf00 nop
8003148: 370c adds r7, #12
800314a: 46bd mov sp, r7
800314c: f85d 7b04 ldr.w r7, [sp], #4
8003150: 4770 bx lr
08003152 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8003152: b480 push {r7}
8003154: b083 sub sp, #12
8003156: af00 add r7, sp, #0
8003158: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
800315a: bf00 nop
800315c: 370c adds r7, #12
800315e: 46bd mov sp, r7
8003160: f85d 7b04 ldr.w r7, [sp], #4
8003164: 4770 bx lr
08003166 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8003166: b480 push {r7}
8003168: b083 sub sp, #12
800316a: af00 add r7, sp, #0
800316c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
800316e: bf00 nop
8003170: 370c adds r7, #12
8003172: 46bd mov sp, r7
8003174: f85d 7b04 ldr.w r7, [sp], #4
8003178: 4770 bx lr
0800317a <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
800317a: b480 push {r7}
800317c: b083 sub sp, #12
800317e: af00 add r7, sp, #0
8003180: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8003182: bf00 nop
8003184: 370c adds r7, #12
8003186: 46bd mov sp, r7
8003188: f85d 7b04 ldr.w r7, [sp], #4
800318c: 4770 bx lr
0800318e <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
800318e: b480 push {r7}
8003190: b083 sub sp, #12
8003192: af00 add r7, sp, #0
8003194: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8003196: bf00 nop
8003198: 370c adds r7, #12
800319a: 46bd mov sp, r7
800319c: f85d 7b04 ldr.w r7, [sp], #4
80031a0: 4770 bx lr
...
080031a4 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
80031a4: b480 push {r7}
80031a6: b085 sub sp, #20
80031a8: af00 add r7, sp, #0
80031aa: 6078 str r0, [r7, #4]
80031ac: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
80031ae: 687b ldr r3, [r7, #4]
80031b0: 681b ldr r3, [r3, #0]
80031b2: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
80031b4: 687b ldr r3, [r7, #4]
80031b6: 4a40 ldr r2, [pc, #256] ; (80032b8 <TIM_Base_SetConfig+0x114>)
80031b8: 4293 cmp r3, r2
80031ba: d013 beq.n 80031e4 <TIM_Base_SetConfig+0x40>
80031bc: 687b ldr r3, [r7, #4]
80031be: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80031c2: d00f beq.n 80031e4 <TIM_Base_SetConfig+0x40>
80031c4: 687b ldr r3, [r7, #4]
80031c6: 4a3d ldr r2, [pc, #244] ; (80032bc <TIM_Base_SetConfig+0x118>)
80031c8: 4293 cmp r3, r2
80031ca: d00b beq.n 80031e4 <TIM_Base_SetConfig+0x40>
80031cc: 687b ldr r3, [r7, #4]
80031ce: 4a3c ldr r2, [pc, #240] ; (80032c0 <TIM_Base_SetConfig+0x11c>)
80031d0: 4293 cmp r3, r2
80031d2: d007 beq.n 80031e4 <TIM_Base_SetConfig+0x40>
80031d4: 687b ldr r3, [r7, #4]
80031d6: 4a3b ldr r2, [pc, #236] ; (80032c4 <TIM_Base_SetConfig+0x120>)
80031d8: 4293 cmp r3, r2
80031da: d003 beq.n 80031e4 <TIM_Base_SetConfig+0x40>
80031dc: 687b ldr r3, [r7, #4]
80031de: 4a3a ldr r2, [pc, #232] ; (80032c8 <TIM_Base_SetConfig+0x124>)
80031e0: 4293 cmp r3, r2
80031e2: d108 bne.n 80031f6 <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
80031e4: 68fb ldr r3, [r7, #12]
80031e6: f023 0370 bic.w r3, r3, #112 ; 0x70
80031ea: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
80031ec: 683b ldr r3, [r7, #0]
80031ee: 685b ldr r3, [r3, #4]
80031f0: 68fa ldr r2, [r7, #12]
80031f2: 4313 orrs r3, r2
80031f4: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
80031f6: 687b ldr r3, [r7, #4]
80031f8: 4a2f ldr r2, [pc, #188] ; (80032b8 <TIM_Base_SetConfig+0x114>)
80031fa: 4293 cmp r3, r2
80031fc: d02b beq.n 8003256 <TIM_Base_SetConfig+0xb2>
80031fe: 687b ldr r3, [r7, #4]
8003200: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8003204: d027 beq.n 8003256 <TIM_Base_SetConfig+0xb2>
8003206: 687b ldr r3, [r7, #4]
8003208: 4a2c ldr r2, [pc, #176] ; (80032bc <TIM_Base_SetConfig+0x118>)
800320a: 4293 cmp r3, r2
800320c: d023 beq.n 8003256 <TIM_Base_SetConfig+0xb2>
800320e: 687b ldr r3, [r7, #4]
8003210: 4a2b ldr r2, [pc, #172] ; (80032c0 <TIM_Base_SetConfig+0x11c>)
8003212: 4293 cmp r3, r2
8003214: d01f beq.n 8003256 <TIM_Base_SetConfig+0xb2>
8003216: 687b ldr r3, [r7, #4]
8003218: 4a2a ldr r2, [pc, #168] ; (80032c4 <TIM_Base_SetConfig+0x120>)
800321a: 4293 cmp r3, r2
800321c: d01b beq.n 8003256 <TIM_Base_SetConfig+0xb2>
800321e: 687b ldr r3, [r7, #4]
8003220: 4a29 ldr r2, [pc, #164] ; (80032c8 <TIM_Base_SetConfig+0x124>)
8003222: 4293 cmp r3, r2
8003224: d017 beq.n 8003256 <TIM_Base_SetConfig+0xb2>
8003226: 687b ldr r3, [r7, #4]
8003228: 4a28 ldr r2, [pc, #160] ; (80032cc <TIM_Base_SetConfig+0x128>)
800322a: 4293 cmp r3, r2
800322c: d013 beq.n 8003256 <TIM_Base_SetConfig+0xb2>
800322e: 687b ldr r3, [r7, #4]
8003230: 4a27 ldr r2, [pc, #156] ; (80032d0 <TIM_Base_SetConfig+0x12c>)
8003232: 4293 cmp r3, r2
8003234: d00f beq.n 8003256 <TIM_Base_SetConfig+0xb2>
8003236: 687b ldr r3, [r7, #4]
8003238: 4a26 ldr r2, [pc, #152] ; (80032d4 <TIM_Base_SetConfig+0x130>)
800323a: 4293 cmp r3, r2
800323c: d00b beq.n 8003256 <TIM_Base_SetConfig+0xb2>
800323e: 687b ldr r3, [r7, #4]
8003240: 4a25 ldr r2, [pc, #148] ; (80032d8 <TIM_Base_SetConfig+0x134>)
8003242: 4293 cmp r3, r2
8003244: d007 beq.n 8003256 <TIM_Base_SetConfig+0xb2>
8003246: 687b ldr r3, [r7, #4]
8003248: 4a24 ldr r2, [pc, #144] ; (80032dc <TIM_Base_SetConfig+0x138>)
800324a: 4293 cmp r3, r2
800324c: d003 beq.n 8003256 <TIM_Base_SetConfig+0xb2>
800324e: 687b ldr r3, [r7, #4]
8003250: 4a23 ldr r2, [pc, #140] ; (80032e0 <TIM_Base_SetConfig+0x13c>)
8003252: 4293 cmp r3, r2
8003254: d108 bne.n 8003268 <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8003256: 68fb ldr r3, [r7, #12]
8003258: f423 7340 bic.w r3, r3, #768 ; 0x300
800325c: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800325e: 683b ldr r3, [r7, #0]
8003260: 68db ldr r3, [r3, #12]
8003262: 68fa ldr r2, [r7, #12]
8003264: 4313 orrs r3, r2
8003266: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8003268: 68fb ldr r3, [r7, #12]
800326a: f023 0280 bic.w r2, r3, #128 ; 0x80
800326e: 683b ldr r3, [r7, #0]
8003270: 695b ldr r3, [r3, #20]
8003272: 4313 orrs r3, r2
8003274: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8003276: 687b ldr r3, [r7, #4]
8003278: 68fa ldr r2, [r7, #12]
800327a: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
800327c: 683b ldr r3, [r7, #0]
800327e: 689a ldr r2, [r3, #8]
8003280: 687b ldr r3, [r7, #4]
8003282: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8003284: 683b ldr r3, [r7, #0]
8003286: 681a ldr r2, [r3, #0]
8003288: 687b ldr r3, [r7, #4]
800328a: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
800328c: 687b ldr r3, [r7, #4]
800328e: 4a0a ldr r2, [pc, #40] ; (80032b8 <TIM_Base_SetConfig+0x114>)
8003290: 4293 cmp r3, r2
8003292: d003 beq.n 800329c <TIM_Base_SetConfig+0xf8>
8003294: 687b ldr r3, [r7, #4]
8003296: 4a0c ldr r2, [pc, #48] ; (80032c8 <TIM_Base_SetConfig+0x124>)
8003298: 4293 cmp r3, r2
800329a: d103 bne.n 80032a4 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
800329c: 683b ldr r3, [r7, #0]
800329e: 691a ldr r2, [r3, #16]
80032a0: 687b ldr r3, [r7, #4]
80032a2: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
80032a4: 687b ldr r3, [r7, #4]
80032a6: 2201 movs r2, #1
80032a8: 615a str r2, [r3, #20]
}
80032aa: bf00 nop
80032ac: 3714 adds r7, #20
80032ae: 46bd mov sp, r7
80032b0: f85d 7b04 ldr.w r7, [sp], #4
80032b4: 4770 bx lr
80032b6: bf00 nop
80032b8: 40010000 .word 0x40010000
80032bc: 40000400 .word 0x40000400
80032c0: 40000800 .word 0x40000800
80032c4: 40000c00 .word 0x40000c00
80032c8: 40010400 .word 0x40010400
80032cc: 40014000 .word 0x40014000
80032d0: 40014400 .word 0x40014400
80032d4: 40014800 .word 0x40014800
80032d8: 40001800 .word 0x40001800
80032dc: 40001c00 .word 0x40001c00
80032e0: 40002000 .word 0x40002000
080032e4 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
80032e4: b480 push {r7}
80032e6: b087 sub sp, #28
80032e8: af00 add r7, sp, #0
80032ea: 6078 str r0, [r7, #4]
80032ec: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
80032ee: 687b ldr r3, [r7, #4]
80032f0: 6a1b ldr r3, [r3, #32]
80032f2: f023 0201 bic.w r2, r3, #1
80032f6: 687b ldr r3, [r7, #4]
80032f8: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80032fa: 687b ldr r3, [r7, #4]
80032fc: 6a1b ldr r3, [r3, #32]
80032fe: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003300: 687b ldr r3, [r7, #4]
8003302: 685b ldr r3, [r3, #4]
8003304: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8003306: 687b ldr r3, [r7, #4]
8003308: 699b ldr r3, [r3, #24]
800330a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
800330c: 68fb ldr r3, [r7, #12]
800330e: f023 0370 bic.w r3, r3, #112 ; 0x70
8003312: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8003314: 68fb ldr r3, [r7, #12]
8003316: f023 0303 bic.w r3, r3, #3
800331a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800331c: 683b ldr r3, [r7, #0]
800331e: 681b ldr r3, [r3, #0]
8003320: 68fa ldr r2, [r7, #12]
8003322: 4313 orrs r3, r2
8003324: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8003326: 697b ldr r3, [r7, #20]
8003328: f023 0302 bic.w r3, r3, #2
800332c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
800332e: 683b ldr r3, [r7, #0]
8003330: 689b ldr r3, [r3, #8]
8003332: 697a ldr r2, [r7, #20]
8003334: 4313 orrs r3, r2
8003336: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8003338: 687b ldr r3, [r7, #4]
800333a: 4a20 ldr r2, [pc, #128] ; (80033bc <TIM_OC1_SetConfig+0xd8>)
800333c: 4293 cmp r3, r2
800333e: d003 beq.n 8003348 <TIM_OC1_SetConfig+0x64>
8003340: 687b ldr r3, [r7, #4]
8003342: 4a1f ldr r2, [pc, #124] ; (80033c0 <TIM_OC1_SetConfig+0xdc>)
8003344: 4293 cmp r3, r2
8003346: d10c bne.n 8003362 <TIM_OC1_SetConfig+0x7e>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8003348: 697b ldr r3, [r7, #20]
800334a: f023 0308 bic.w r3, r3, #8
800334e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8003350: 683b ldr r3, [r7, #0]
8003352: 68db ldr r3, [r3, #12]
8003354: 697a ldr r2, [r7, #20]
8003356: 4313 orrs r3, r2
8003358: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
800335a: 697b ldr r3, [r7, #20]
800335c: f023 0304 bic.w r3, r3, #4
8003360: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003362: 687b ldr r3, [r7, #4]
8003364: 4a15 ldr r2, [pc, #84] ; (80033bc <TIM_OC1_SetConfig+0xd8>)
8003366: 4293 cmp r3, r2
8003368: d003 beq.n 8003372 <TIM_OC1_SetConfig+0x8e>
800336a: 687b ldr r3, [r7, #4]
800336c: 4a14 ldr r2, [pc, #80] ; (80033c0 <TIM_OC1_SetConfig+0xdc>)
800336e: 4293 cmp r3, r2
8003370: d111 bne.n 8003396 <TIM_OC1_SetConfig+0xb2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8003372: 693b ldr r3, [r7, #16]
8003374: f423 7380 bic.w r3, r3, #256 ; 0x100
8003378: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
800337a: 693b ldr r3, [r7, #16]
800337c: f423 7300 bic.w r3, r3, #512 ; 0x200
8003380: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8003382: 683b ldr r3, [r7, #0]
8003384: 695b ldr r3, [r3, #20]
8003386: 693a ldr r2, [r7, #16]
8003388: 4313 orrs r3, r2
800338a: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
800338c: 683b ldr r3, [r7, #0]
800338e: 699b ldr r3, [r3, #24]
8003390: 693a ldr r2, [r7, #16]
8003392: 4313 orrs r3, r2
8003394: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003396: 687b ldr r3, [r7, #4]
8003398: 693a ldr r2, [r7, #16]
800339a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800339c: 687b ldr r3, [r7, #4]
800339e: 68fa ldr r2, [r7, #12]
80033a0: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
80033a2: 683b ldr r3, [r7, #0]
80033a4: 685a ldr r2, [r3, #4]
80033a6: 687b ldr r3, [r7, #4]
80033a8: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80033aa: 687b ldr r3, [r7, #4]
80033ac: 697a ldr r2, [r7, #20]
80033ae: 621a str r2, [r3, #32]
}
80033b0: bf00 nop
80033b2: 371c adds r7, #28
80033b4: 46bd mov sp, r7
80033b6: f85d 7b04 ldr.w r7, [sp], #4
80033ba: 4770 bx lr
80033bc: 40010000 .word 0x40010000
80033c0: 40010400 .word 0x40010400
080033c4 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
80033c4: b480 push {r7}
80033c6: b087 sub sp, #28
80033c8: af00 add r7, sp, #0
80033ca: 6078 str r0, [r7, #4]
80033cc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
80033ce: 687b ldr r3, [r7, #4]
80033d0: 6a1b ldr r3, [r3, #32]
80033d2: f023 0210 bic.w r2, r3, #16
80033d6: 687b ldr r3, [r7, #4]
80033d8: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80033da: 687b ldr r3, [r7, #4]
80033dc: 6a1b ldr r3, [r3, #32]
80033de: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80033e0: 687b ldr r3, [r7, #4]
80033e2: 685b ldr r3, [r3, #4]
80033e4: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80033e6: 687b ldr r3, [r7, #4]
80033e8: 699b ldr r3, [r3, #24]
80033ea: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
80033ec: 68fb ldr r3, [r7, #12]
80033ee: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
80033f2: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
80033f4: 68fb ldr r3, [r7, #12]
80033f6: f423 7340 bic.w r3, r3, #768 ; 0x300
80033fa: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80033fc: 683b ldr r3, [r7, #0]
80033fe: 681b ldr r3, [r3, #0]
8003400: 021b lsls r3, r3, #8
8003402: 68fa ldr r2, [r7, #12]
8003404: 4313 orrs r3, r2
8003406: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8003408: 697b ldr r3, [r7, #20]
800340a: f023 0320 bic.w r3, r3, #32
800340e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8003410: 683b ldr r3, [r7, #0]
8003412: 689b ldr r3, [r3, #8]
8003414: 011b lsls r3, r3, #4
8003416: 697a ldr r2, [r7, #20]
8003418: 4313 orrs r3, r2
800341a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
800341c: 687b ldr r3, [r7, #4]
800341e: 4a22 ldr r2, [pc, #136] ; (80034a8 <TIM_OC2_SetConfig+0xe4>)
8003420: 4293 cmp r3, r2
8003422: d003 beq.n 800342c <TIM_OC2_SetConfig+0x68>
8003424: 687b ldr r3, [r7, #4]
8003426: 4a21 ldr r2, [pc, #132] ; (80034ac <TIM_OC2_SetConfig+0xe8>)
8003428: 4293 cmp r3, r2
800342a: d10d bne.n 8003448 <TIM_OC2_SetConfig+0x84>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
800342c: 697b ldr r3, [r7, #20]
800342e: f023 0380 bic.w r3, r3, #128 ; 0x80
8003432: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8003434: 683b ldr r3, [r7, #0]
8003436: 68db ldr r3, [r3, #12]
8003438: 011b lsls r3, r3, #4
800343a: 697a ldr r2, [r7, #20]
800343c: 4313 orrs r3, r2
800343e: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8003440: 697b ldr r3, [r7, #20]
8003442: f023 0340 bic.w r3, r3, #64 ; 0x40
8003446: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003448: 687b ldr r3, [r7, #4]
800344a: 4a17 ldr r2, [pc, #92] ; (80034a8 <TIM_OC2_SetConfig+0xe4>)
800344c: 4293 cmp r3, r2
800344e: d003 beq.n 8003458 <TIM_OC2_SetConfig+0x94>
8003450: 687b ldr r3, [r7, #4]
8003452: 4a16 ldr r2, [pc, #88] ; (80034ac <TIM_OC2_SetConfig+0xe8>)
8003454: 4293 cmp r3, r2
8003456: d113 bne.n 8003480 <TIM_OC2_SetConfig+0xbc>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8003458: 693b ldr r3, [r7, #16]
800345a: f423 6380 bic.w r3, r3, #1024 ; 0x400
800345e: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8003460: 693b ldr r3, [r7, #16]
8003462: f423 6300 bic.w r3, r3, #2048 ; 0x800
8003466: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8003468: 683b ldr r3, [r7, #0]
800346a: 695b ldr r3, [r3, #20]
800346c: 009b lsls r3, r3, #2
800346e: 693a ldr r2, [r7, #16]
8003470: 4313 orrs r3, r2
8003472: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8003474: 683b ldr r3, [r7, #0]
8003476: 699b ldr r3, [r3, #24]
8003478: 009b lsls r3, r3, #2
800347a: 693a ldr r2, [r7, #16]
800347c: 4313 orrs r3, r2
800347e: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003480: 687b ldr r3, [r7, #4]
8003482: 693a ldr r2, [r7, #16]
8003484: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8003486: 687b ldr r3, [r7, #4]
8003488: 68fa ldr r2, [r7, #12]
800348a: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
800348c: 683b ldr r3, [r7, #0]
800348e: 685a ldr r2, [r3, #4]
8003490: 687b ldr r3, [r7, #4]
8003492: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003494: 687b ldr r3, [r7, #4]
8003496: 697a ldr r2, [r7, #20]
8003498: 621a str r2, [r3, #32]
}
800349a: bf00 nop
800349c: 371c adds r7, #28
800349e: 46bd mov sp, r7
80034a0: f85d 7b04 ldr.w r7, [sp], #4
80034a4: 4770 bx lr
80034a6: bf00 nop
80034a8: 40010000 .word 0x40010000
80034ac: 40010400 .word 0x40010400
080034b0 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
80034b0: b480 push {r7}
80034b2: b087 sub sp, #28
80034b4: af00 add r7, sp, #0
80034b6: 6078 str r0, [r7, #4]
80034b8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
80034ba: 687b ldr r3, [r7, #4]
80034bc: 6a1b ldr r3, [r3, #32]
80034be: f423 7280 bic.w r2, r3, #256 ; 0x100
80034c2: 687b ldr r3, [r7, #4]
80034c4: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80034c6: 687b ldr r3, [r7, #4]
80034c8: 6a1b ldr r3, [r3, #32]
80034ca: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80034cc: 687b ldr r3, [r7, #4]
80034ce: 685b ldr r3, [r3, #4]
80034d0: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
80034d2: 687b ldr r3, [r7, #4]
80034d4: 69db ldr r3, [r3, #28]
80034d6: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
80034d8: 68fb ldr r3, [r7, #12]
80034da: f023 0370 bic.w r3, r3, #112 ; 0x70
80034de: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
80034e0: 68fb ldr r3, [r7, #12]
80034e2: f023 0303 bic.w r3, r3, #3
80034e6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80034e8: 683b ldr r3, [r7, #0]
80034ea: 681b ldr r3, [r3, #0]
80034ec: 68fa ldr r2, [r7, #12]
80034ee: 4313 orrs r3, r2
80034f0: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
80034f2: 697b ldr r3, [r7, #20]
80034f4: f423 7300 bic.w r3, r3, #512 ; 0x200
80034f8: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
80034fa: 683b ldr r3, [r7, #0]
80034fc: 689b ldr r3, [r3, #8]
80034fe: 021b lsls r3, r3, #8
8003500: 697a ldr r2, [r7, #20]
8003502: 4313 orrs r3, r2
8003504: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8003506: 687b ldr r3, [r7, #4]
8003508: 4a21 ldr r2, [pc, #132] ; (8003590 <TIM_OC3_SetConfig+0xe0>)
800350a: 4293 cmp r3, r2
800350c: d003 beq.n 8003516 <TIM_OC3_SetConfig+0x66>
800350e: 687b ldr r3, [r7, #4]
8003510: 4a20 ldr r2, [pc, #128] ; (8003594 <TIM_OC3_SetConfig+0xe4>)
8003512: 4293 cmp r3, r2
8003514: d10d bne.n 8003532 <TIM_OC3_SetConfig+0x82>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8003516: 697b ldr r3, [r7, #20]
8003518: f423 6300 bic.w r3, r3, #2048 ; 0x800
800351c: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
800351e: 683b ldr r3, [r7, #0]
8003520: 68db ldr r3, [r3, #12]
8003522: 021b lsls r3, r3, #8
8003524: 697a ldr r2, [r7, #20]
8003526: 4313 orrs r3, r2
8003528: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
800352a: 697b ldr r3, [r7, #20]
800352c: f423 6380 bic.w r3, r3, #1024 ; 0x400
8003530: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003532: 687b ldr r3, [r7, #4]
8003534: 4a16 ldr r2, [pc, #88] ; (8003590 <TIM_OC3_SetConfig+0xe0>)
8003536: 4293 cmp r3, r2
8003538: d003 beq.n 8003542 <TIM_OC3_SetConfig+0x92>
800353a: 687b ldr r3, [r7, #4]
800353c: 4a15 ldr r2, [pc, #84] ; (8003594 <TIM_OC3_SetConfig+0xe4>)
800353e: 4293 cmp r3, r2
8003540: d113 bne.n 800356a <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8003542: 693b ldr r3, [r7, #16]
8003544: f423 5380 bic.w r3, r3, #4096 ; 0x1000
8003548: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
800354a: 693b ldr r3, [r7, #16]
800354c: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8003550: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8003552: 683b ldr r3, [r7, #0]
8003554: 695b ldr r3, [r3, #20]
8003556: 011b lsls r3, r3, #4
8003558: 693a ldr r2, [r7, #16]
800355a: 4313 orrs r3, r2
800355c: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
800355e: 683b ldr r3, [r7, #0]
8003560: 699b ldr r3, [r3, #24]
8003562: 011b lsls r3, r3, #4
8003564: 693a ldr r2, [r7, #16]
8003566: 4313 orrs r3, r2
8003568: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800356a: 687b ldr r3, [r7, #4]
800356c: 693a ldr r2, [r7, #16]
800356e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8003570: 687b ldr r3, [r7, #4]
8003572: 68fa ldr r2, [r7, #12]
8003574: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8003576: 683b ldr r3, [r7, #0]
8003578: 685a ldr r2, [r3, #4]
800357a: 687b ldr r3, [r7, #4]
800357c: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800357e: 687b ldr r3, [r7, #4]
8003580: 697a ldr r2, [r7, #20]
8003582: 621a str r2, [r3, #32]
}
8003584: bf00 nop
8003586: 371c adds r7, #28
8003588: 46bd mov sp, r7
800358a: f85d 7b04 ldr.w r7, [sp], #4
800358e: 4770 bx lr
8003590: 40010000 .word 0x40010000
8003594: 40010400 .word 0x40010400
08003598 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8003598: b480 push {r7}
800359a: b087 sub sp, #28
800359c: af00 add r7, sp, #0
800359e: 6078 str r0, [r7, #4]
80035a0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
80035a2: 687b ldr r3, [r7, #4]
80035a4: 6a1b ldr r3, [r3, #32]
80035a6: f423 5280 bic.w r2, r3, #4096 ; 0x1000
80035aa: 687b ldr r3, [r7, #4]
80035ac: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80035ae: 687b ldr r3, [r7, #4]
80035b0: 6a1b ldr r3, [r3, #32]
80035b2: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80035b4: 687b ldr r3, [r7, #4]
80035b6: 685b ldr r3, [r3, #4]
80035b8: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
80035ba: 687b ldr r3, [r7, #4]
80035bc: 69db ldr r3, [r3, #28]
80035be: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
80035c0: 68fb ldr r3, [r7, #12]
80035c2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
80035c6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
80035c8: 68fb ldr r3, [r7, #12]
80035ca: f423 7340 bic.w r3, r3, #768 ; 0x300
80035ce: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80035d0: 683b ldr r3, [r7, #0]
80035d2: 681b ldr r3, [r3, #0]
80035d4: 021b lsls r3, r3, #8
80035d6: 68fa ldr r2, [r7, #12]
80035d8: 4313 orrs r3, r2
80035da: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
80035dc: 693b ldr r3, [r7, #16]
80035de: f423 5300 bic.w r3, r3, #8192 ; 0x2000
80035e2: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
80035e4: 683b ldr r3, [r7, #0]
80035e6: 689b ldr r3, [r3, #8]
80035e8: 031b lsls r3, r3, #12
80035ea: 693a ldr r2, [r7, #16]
80035ec: 4313 orrs r3, r2
80035ee: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80035f0: 687b ldr r3, [r7, #4]
80035f2: 4a12 ldr r2, [pc, #72] ; (800363c <TIM_OC4_SetConfig+0xa4>)
80035f4: 4293 cmp r3, r2
80035f6: d003 beq.n 8003600 <TIM_OC4_SetConfig+0x68>
80035f8: 687b ldr r3, [r7, #4]
80035fa: 4a11 ldr r2, [pc, #68] ; (8003640 <TIM_OC4_SetConfig+0xa8>)
80035fc: 4293 cmp r3, r2
80035fe: d109 bne.n 8003614 <TIM_OC4_SetConfig+0x7c>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8003600: 697b ldr r3, [r7, #20]
8003602: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8003606: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8003608: 683b ldr r3, [r7, #0]
800360a: 695b ldr r3, [r3, #20]
800360c: 019b lsls r3, r3, #6
800360e: 697a ldr r2, [r7, #20]
8003610: 4313 orrs r3, r2
8003612: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003614: 687b ldr r3, [r7, #4]
8003616: 697a ldr r2, [r7, #20]
8003618: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800361a: 687b ldr r3, [r7, #4]
800361c: 68fa ldr r2, [r7, #12]
800361e: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8003620: 683b ldr r3, [r7, #0]
8003622: 685a ldr r2, [r3, #4]
8003624: 687b ldr r3, [r7, #4]
8003626: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003628: 687b ldr r3, [r7, #4]
800362a: 693a ldr r2, [r7, #16]
800362c: 621a str r2, [r3, #32]
}
800362e: bf00 nop
8003630: 371c adds r7, #28
8003632: 46bd mov sp, r7
8003634: f85d 7b04 ldr.w r7, [sp], #4
8003638: 4770 bx lr
800363a: bf00 nop
800363c: 40010000 .word 0x40010000
8003640: 40010400 .word 0x40010400
08003644 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8003644: b480 push {r7}
8003646: b087 sub sp, #28
8003648: af00 add r7, sp, #0
800364a: 60f8 str r0, [r7, #12]
800364c: 60b9 str r1, [r7, #8]
800364e: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8003650: 68fb ldr r3, [r7, #12]
8003652: 6a1b ldr r3, [r3, #32]
8003654: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8003656: 68fb ldr r3, [r7, #12]
8003658: 6a1b ldr r3, [r3, #32]
800365a: f023 0201 bic.w r2, r3, #1
800365e: 68fb ldr r3, [r7, #12]
8003660: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8003662: 68fb ldr r3, [r7, #12]
8003664: 699b ldr r3, [r3, #24]
8003666: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8003668: 693b ldr r3, [r7, #16]
800366a: f023 03f0 bic.w r3, r3, #240 ; 0xf0
800366e: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8003670: 687b ldr r3, [r7, #4]
8003672: 011b lsls r3, r3, #4
8003674: 693a ldr r2, [r7, #16]
8003676: 4313 orrs r3, r2
8003678: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800367a: 697b ldr r3, [r7, #20]
800367c: f023 030a bic.w r3, r3, #10
8003680: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8003682: 697a ldr r2, [r7, #20]
8003684: 68bb ldr r3, [r7, #8]
8003686: 4313 orrs r3, r2
8003688: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
800368a: 68fb ldr r3, [r7, #12]
800368c: 693a ldr r2, [r7, #16]
800368e: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8003690: 68fb ldr r3, [r7, #12]
8003692: 697a ldr r2, [r7, #20]
8003694: 621a str r2, [r3, #32]
}
8003696: bf00 nop
8003698: 371c adds r7, #28
800369a: 46bd mov sp, r7
800369c: f85d 7b04 ldr.w r7, [sp], #4
80036a0: 4770 bx lr
080036a2 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
80036a2: b480 push {r7}
80036a4: b087 sub sp, #28
80036a6: af00 add r7, sp, #0
80036a8: 60f8 str r0, [r7, #12]
80036aa: 60b9 str r1, [r7, #8]
80036ac: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
80036ae: 68fb ldr r3, [r7, #12]
80036b0: 6a1b ldr r3, [r3, #32]
80036b2: f023 0210 bic.w r2, r3, #16
80036b6: 68fb ldr r3, [r7, #12]
80036b8: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
80036ba: 68fb ldr r3, [r7, #12]
80036bc: 699b ldr r3, [r3, #24]
80036be: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
80036c0: 68fb ldr r3, [r7, #12]
80036c2: 6a1b ldr r3, [r3, #32]
80036c4: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
80036c6: 697b ldr r3, [r7, #20]
80036c8: f423 4370 bic.w r3, r3, #61440 ; 0xf000
80036cc: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
80036ce: 687b ldr r3, [r7, #4]
80036d0: 031b lsls r3, r3, #12
80036d2: 697a ldr r2, [r7, #20]
80036d4: 4313 orrs r3, r2
80036d6: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
80036d8: 693b ldr r3, [r7, #16]
80036da: f023 03a0 bic.w r3, r3, #160 ; 0xa0
80036de: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
80036e0: 68bb ldr r3, [r7, #8]
80036e2: 011b lsls r3, r3, #4
80036e4: 693a ldr r2, [r7, #16]
80036e6: 4313 orrs r3, r2
80036e8: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
80036ea: 68fb ldr r3, [r7, #12]
80036ec: 697a ldr r2, [r7, #20]
80036ee: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
80036f0: 68fb ldr r3, [r7, #12]
80036f2: 693a ldr r2, [r7, #16]
80036f4: 621a str r2, [r3, #32]
}
80036f6: bf00 nop
80036f8: 371c adds r7, #28
80036fa: 46bd mov sp, r7
80036fc: f85d 7b04 ldr.w r7, [sp], #4
8003700: 4770 bx lr
08003702 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8003702: b480 push {r7}
8003704: b085 sub sp, #20
8003706: af00 add r7, sp, #0
8003708: 6078 str r0, [r7, #4]
800370a: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
800370c: 687b ldr r3, [r7, #4]
800370e: 689b ldr r3, [r3, #8]
8003710: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8003712: 68fb ldr r3, [r7, #12]
8003714: f023 0370 bic.w r3, r3, #112 ; 0x70
8003718: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800371a: 683a ldr r2, [r7, #0]
800371c: 68fb ldr r3, [r7, #12]
800371e: 4313 orrs r3, r2
8003720: f043 0307 orr.w r3, r3, #7
8003724: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8003726: 687b ldr r3, [r7, #4]
8003728: 68fa ldr r2, [r7, #12]
800372a: 609a str r2, [r3, #8]
}
800372c: bf00 nop
800372e: 3714 adds r7, #20
8003730: 46bd mov sp, r7
8003732: f85d 7b04 ldr.w r7, [sp], #4
8003736: 4770 bx lr
08003738 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8003738: b480 push {r7}
800373a: b087 sub sp, #28
800373c: af00 add r7, sp, #0
800373e: 60f8 str r0, [r7, #12]
8003740: 60b9 str r1, [r7, #8]
8003742: 607a str r2, [r7, #4]
8003744: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8003746: 68fb ldr r3, [r7, #12]
8003748: 689b ldr r3, [r3, #8]
800374a: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800374c: 697b ldr r3, [r7, #20]
800374e: f423 437f bic.w r3, r3, #65280 ; 0xff00
8003752: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8003754: 683b ldr r3, [r7, #0]
8003756: 021a lsls r2, r3, #8
8003758: 687b ldr r3, [r7, #4]
800375a: 431a orrs r2, r3
800375c: 68bb ldr r3, [r7, #8]
800375e: 4313 orrs r3, r2
8003760: 697a ldr r2, [r7, #20]
8003762: 4313 orrs r3, r2
8003764: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8003766: 68fb ldr r3, [r7, #12]
8003768: 697a ldr r2, [r7, #20]
800376a: 609a str r2, [r3, #8]
}
800376c: bf00 nop
800376e: 371c adds r7, #28
8003770: 46bd mov sp, r7
8003772: f85d 7b04 ldr.w r7, [sp], #4
8003776: 4770 bx lr
08003778 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8003778: b480 push {r7}
800377a: b087 sub sp, #28
800377c: af00 add r7, sp, #0
800377e: 60f8 str r0, [r7, #12]
8003780: 60b9 str r1, [r7, #8]
8003782: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8003784: 68bb ldr r3, [r7, #8]
8003786: f003 031f and.w r3, r3, #31
800378a: 2201 movs r2, #1
800378c: fa02 f303 lsl.w r3, r2, r3
8003790: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8003792: 68fb ldr r3, [r7, #12]
8003794: 6a1a ldr r2, [r3, #32]
8003796: 697b ldr r3, [r7, #20]
8003798: 43db mvns r3, r3
800379a: 401a ands r2, r3
800379c: 68fb ldr r3, [r7, #12]
800379e: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
80037a0: 68fb ldr r3, [r7, #12]
80037a2: 6a1a ldr r2, [r3, #32]
80037a4: 68bb ldr r3, [r7, #8]
80037a6: f003 031f and.w r3, r3, #31
80037aa: 6879 ldr r1, [r7, #4]
80037ac: fa01 f303 lsl.w r3, r1, r3
80037b0: 431a orrs r2, r3
80037b2: 68fb ldr r3, [r7, #12]
80037b4: 621a str r2, [r3, #32]
}
80037b6: bf00 nop
80037b8: 371c adds r7, #28
80037ba: 46bd mov sp, r7
80037bc: f85d 7b04 ldr.w r7, [sp], #4
80037c0: 4770 bx lr
...
080037c4 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
80037c4: b480 push {r7}
80037c6: b085 sub sp, #20
80037c8: af00 add r7, sp, #0
80037ca: 6078 str r0, [r7, #4]
80037cc: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
80037ce: 687b ldr r3, [r7, #4]
80037d0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80037d4: 2b01 cmp r3, #1
80037d6: d101 bne.n 80037dc <HAL_TIMEx_MasterConfigSynchronization+0x18>
80037d8: 2302 movs r3, #2
80037da: e05a b.n 8003892 <HAL_TIMEx_MasterConfigSynchronization+0xce>
80037dc: 687b ldr r3, [r7, #4]
80037de: 2201 movs r2, #1
80037e0: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80037e4: 687b ldr r3, [r7, #4]
80037e6: 2202 movs r2, #2
80037e8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80037ec: 687b ldr r3, [r7, #4]
80037ee: 681b ldr r3, [r3, #0]
80037f0: 685b ldr r3, [r3, #4]
80037f2: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80037f4: 687b ldr r3, [r7, #4]
80037f6: 681b ldr r3, [r3, #0]
80037f8: 689b ldr r3, [r3, #8]
80037fa: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
80037fc: 68fb ldr r3, [r7, #12]
80037fe: f023 0370 bic.w r3, r3, #112 ; 0x70
8003802: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8003804: 683b ldr r3, [r7, #0]
8003806: 681b ldr r3, [r3, #0]
8003808: 68fa ldr r2, [r7, #12]
800380a: 4313 orrs r3, r2
800380c: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
800380e: 687b ldr r3, [r7, #4]
8003810: 681b ldr r3, [r3, #0]
8003812: 68fa ldr r2, [r7, #12]
8003814: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8003816: 687b ldr r3, [r7, #4]
8003818: 681b ldr r3, [r3, #0]
800381a: 4a21 ldr r2, [pc, #132] ; (80038a0 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
800381c: 4293 cmp r3, r2
800381e: d022 beq.n 8003866 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8003820: 687b ldr r3, [r7, #4]
8003822: 681b ldr r3, [r3, #0]
8003824: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8003828: d01d beq.n 8003866 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
800382a: 687b ldr r3, [r7, #4]
800382c: 681b ldr r3, [r3, #0]
800382e: 4a1d ldr r2, [pc, #116] ; (80038a4 <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
8003830: 4293 cmp r3, r2
8003832: d018 beq.n 8003866 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8003834: 687b ldr r3, [r7, #4]
8003836: 681b ldr r3, [r3, #0]
8003838: 4a1b ldr r2, [pc, #108] ; (80038a8 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
800383a: 4293 cmp r3, r2
800383c: d013 beq.n 8003866 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
800383e: 687b ldr r3, [r7, #4]
8003840: 681b ldr r3, [r3, #0]
8003842: 4a1a ldr r2, [pc, #104] ; (80038ac <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
8003844: 4293 cmp r3, r2
8003846: d00e beq.n 8003866 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8003848: 687b ldr r3, [r7, #4]
800384a: 681b ldr r3, [r3, #0]
800384c: 4a18 ldr r2, [pc, #96] ; (80038b0 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
800384e: 4293 cmp r3, r2
8003850: d009 beq.n 8003866 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8003852: 687b ldr r3, [r7, #4]
8003854: 681b ldr r3, [r3, #0]
8003856: 4a17 ldr r2, [pc, #92] ; (80038b4 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8003858: 4293 cmp r3, r2
800385a: d004 beq.n 8003866 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
800385c: 687b ldr r3, [r7, #4]
800385e: 681b ldr r3, [r3, #0]
8003860: 4a15 ldr r2, [pc, #84] ; (80038b8 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
8003862: 4293 cmp r3, r2
8003864: d10c bne.n 8003880 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8003866: 68bb ldr r3, [r7, #8]
8003868: f023 0380 bic.w r3, r3, #128 ; 0x80
800386c: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
800386e: 683b ldr r3, [r7, #0]
8003870: 685b ldr r3, [r3, #4]
8003872: 68ba ldr r2, [r7, #8]
8003874: 4313 orrs r3, r2
8003876: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8003878: 687b ldr r3, [r7, #4]
800387a: 681b ldr r3, [r3, #0]
800387c: 68ba ldr r2, [r7, #8]
800387e: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8003880: 687b ldr r3, [r7, #4]
8003882: 2201 movs r2, #1
8003884: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8003888: 687b ldr r3, [r7, #4]
800388a: 2200 movs r2, #0
800388c: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8003890: 2300 movs r3, #0
}
8003892: 4618 mov r0, r3
8003894: 3714 adds r7, #20
8003896: 46bd mov sp, r7
8003898: f85d 7b04 ldr.w r7, [sp], #4
800389c: 4770 bx lr
800389e: bf00 nop
80038a0: 40010000 .word 0x40010000
80038a4: 40000400 .word 0x40000400
80038a8: 40000800 .word 0x40000800
80038ac: 40000c00 .word 0x40000c00
80038b0: 40010400 .word 0x40010400
80038b4: 40014000 .word 0x40014000
80038b8: 40001800 .word 0x40001800
080038bc <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
80038bc: b480 push {r7}
80038be: b085 sub sp, #20
80038c0: af00 add r7, sp, #0
80038c2: 6078 str r0, [r7, #4]
80038c4: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
80038c6: 2300 movs r3, #0
80038c8: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
80038ca: 687b ldr r3, [r7, #4]
80038cc: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80038d0: 2b01 cmp r3, #1
80038d2: d101 bne.n 80038d8 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
80038d4: 2302 movs r3, #2
80038d6: e03d b.n 8003954 <HAL_TIMEx_ConfigBreakDeadTime+0x98>
80038d8: 687b ldr r3, [r7, #4]
80038da: 2201 movs r2, #1
80038dc: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
80038e0: 68fb ldr r3, [r7, #12]
80038e2: f023 02ff bic.w r2, r3, #255 ; 0xff
80038e6: 683b ldr r3, [r7, #0]
80038e8: 68db ldr r3, [r3, #12]
80038ea: 4313 orrs r3, r2
80038ec: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
80038ee: 68fb ldr r3, [r7, #12]
80038f0: f423 7240 bic.w r2, r3, #768 ; 0x300
80038f4: 683b ldr r3, [r7, #0]
80038f6: 689b ldr r3, [r3, #8]
80038f8: 4313 orrs r3, r2
80038fa: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
80038fc: 68fb ldr r3, [r7, #12]
80038fe: f423 6280 bic.w r2, r3, #1024 ; 0x400
8003902: 683b ldr r3, [r7, #0]
8003904: 685b ldr r3, [r3, #4]
8003906: 4313 orrs r3, r2
8003908: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
800390a: 68fb ldr r3, [r7, #12]
800390c: f423 6200 bic.w r2, r3, #2048 ; 0x800
8003910: 683b ldr r3, [r7, #0]
8003912: 681b ldr r3, [r3, #0]
8003914: 4313 orrs r3, r2
8003916: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8003918: 68fb ldr r3, [r7, #12]
800391a: f423 5280 bic.w r2, r3, #4096 ; 0x1000
800391e: 683b ldr r3, [r7, #0]
8003920: 691b ldr r3, [r3, #16]
8003922: 4313 orrs r3, r2
8003924: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
8003926: 68fb ldr r3, [r7, #12]
8003928: f423 5200 bic.w r2, r3, #8192 ; 0x2000
800392c: 683b ldr r3, [r7, #0]
800392e: 695b ldr r3, [r3, #20]
8003930: 4313 orrs r3, r2
8003932: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8003934: 68fb ldr r3, [r7, #12]
8003936: f423 4280 bic.w r2, r3, #16384 ; 0x4000
800393a: 683b ldr r3, [r7, #0]
800393c: 69db ldr r3, [r3, #28]
800393e: 4313 orrs r3, r2
8003940: 60fb str r3, [r7, #12]
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
8003942: 687b ldr r3, [r7, #4]
8003944: 681b ldr r3, [r3, #0]
8003946: 68fa ldr r2, [r7, #12]
8003948: 645a str r2, [r3, #68] ; 0x44
__HAL_UNLOCK(htim);
800394a: 687b ldr r3, [r7, #4]
800394c: 2200 movs r2, #0
800394e: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8003952: 2300 movs r3, #0
}
8003954: 4618 mov r0, r3
8003956: 3714 adds r7, #20
8003958: 46bd mov sp, r7
800395a: f85d 7b04 ldr.w r7, [sp], #4
800395e: 4770 bx lr
08003960 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8003960: b480 push {r7}
8003962: b083 sub sp, #12
8003964: af00 add r7, sp, #0
8003966: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8003968: bf00 nop
800396a: 370c adds r7, #12
800396c: 46bd mov sp, r7
800396e: f85d 7b04 ldr.w r7, [sp], #4
8003972: 4770 bx lr
08003974 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8003974: b480 push {r7}
8003976: b083 sub sp, #12
8003978: af00 add r7, sp, #0
800397a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
800397c: bf00 nop
800397e: 370c adds r7, #12
8003980: 46bd mov sp, r7
8003982: f85d 7b04 ldr.w r7, [sp], #4
8003986: 4770 bx lr
08003988 <memset>:
8003988: 4402 add r2, r0
800398a: 4603 mov r3, r0
800398c: 4293 cmp r3, r2
800398e: d100 bne.n 8003992 <memset+0xa>
8003990: 4770 bx lr
8003992: f803 1b01 strb.w r1, [r3], #1
8003996: e7f9 b.n 800398c <memset+0x4>
08003998 <__libc_init_array>:
8003998: b570 push {r4, r5, r6, lr}
800399a: 4d0d ldr r5, [pc, #52] ; (80039d0 <__libc_init_array+0x38>)
800399c: 4c0d ldr r4, [pc, #52] ; (80039d4 <__libc_init_array+0x3c>)
800399e: 1b64 subs r4, r4, r5
80039a0: 10a4 asrs r4, r4, #2
80039a2: 2600 movs r6, #0
80039a4: 42a6 cmp r6, r4
80039a6: d109 bne.n 80039bc <__libc_init_array+0x24>
80039a8: 4d0b ldr r5, [pc, #44] ; (80039d8 <__libc_init_array+0x40>)
80039aa: 4c0c ldr r4, [pc, #48] ; (80039dc <__libc_init_array+0x44>)
80039ac: f000 f818 bl 80039e0 <_init>
80039b0: 1b64 subs r4, r4, r5
80039b2: 10a4 asrs r4, r4, #2
80039b4: 2600 movs r6, #0
80039b6: 42a6 cmp r6, r4
80039b8: d105 bne.n 80039c6 <__libc_init_array+0x2e>
80039ba: bd70 pop {r4, r5, r6, pc}
80039bc: f855 3b04 ldr.w r3, [r5], #4
80039c0: 4798 blx r3
80039c2: 3601 adds r6, #1
80039c4: e7ee b.n 80039a4 <__libc_init_array+0xc>
80039c6: f855 3b04 ldr.w r3, [r5], #4
80039ca: 4798 blx r3
80039cc: 3601 adds r6, #1
80039ce: e7f2 b.n 80039b6 <__libc_init_array+0x1e>
80039d0: 08003a10 .word 0x08003a10
80039d4: 08003a10 .word 0x08003a10
80039d8: 08003a10 .word 0x08003a10
80039dc: 08003a14 .word 0x08003a14
080039e0 <_init>:
80039e0: b5f8 push {r3, r4, r5, r6, r7, lr}
80039e2: bf00 nop
80039e4: bcf8 pop {r3, r4, r5, r6, r7}
80039e6: bc08 pop {r3}
80039e8: 469e mov lr, r3
80039ea: 4770 bx lr
080039ec <_fini>:
80039ec: b5f8 push {r3, r4, r5, r6, r7, lr}
80039ee: bf00 nop
80039f0: bcf8 pop {r3, r4, r5, r6, r7}
80039f2: bc08 pop {r3}
80039f4: 469e mov lr, r3
80039f6: 4770 bx lr
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