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1/копии на всякий случай/gen pwm/Debug/STM_gen.list

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STM_gen.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00003134 08000188 08000188 00010188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000010 080032bc 080032bc 000132bc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080032cc 080032cc 00020010 2**0
CONTENTS
4 .ARM 00000008 080032cc 080032cc 000132cc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080032d4 080032d4 00020010 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080032d4 080032d4 000132d4 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 080032d8 080032d8 000132d8 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000010 20000000 080032dc 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .ccmram 00000000 10000000 10000000 00020010 2**0
CONTENTS
10 .bss 0000010c 20000010 20000010 00020010 2**2
ALLOC
11 ._user_heap_stack 00000604 2000011c 2000011c 00020010 2**0
ALLOC
12 .ARM.attributes 00000030 00000000 00000000 00020010 2**0
CONTENTS, READONLY
13 .comment 00000043 00000000 00000000 00020040 2**0
CONTENTS, READONLY
14 .debug_info 0000aabe 00000000 00000000 00020083 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_abbrev 000018a1 00000000 00000000 0002ab41 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_aranges 00000b48 00000000 00000000 0002c3e8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_rnglists 000008c2 00000000 00000000 0002cf30 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_macro 0001ff5d 00000000 00000000 0002d7f2 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_line 0000c179 00000000 00000000 0004d74f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_str 000c6453 00000000 00000000 000598c8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_frame 00002f94 00000000 00000000 0011fd1c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
22 .debug_line_str 0000004b 00000000 00000000 00122cb0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 20000010 .word 0x20000010
80001a4: 00000000 .word 0x00000000
80001a8: 080032a4 .word 0x080032a4
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000014 .word 0x20000014
80001c4: 080032a4 .word 0x080032a4
080001c8 <__aeabi_uldivmod>:
80001c8: b953 cbnz r3, 80001e0 <__aeabi_uldivmod+0x18>
80001ca: b94a cbnz r2, 80001e0 <__aeabi_uldivmod+0x18>
80001cc: 2900 cmp r1, #0
80001ce: bf08 it eq
80001d0: 2800 cmpeq r0, #0
80001d2: bf1c itt ne
80001d4: f04f 31ff movne.w r1, #4294967295
80001d8: f04f 30ff movne.w r0, #4294967295
80001dc: f000 b970 b.w 80004c0 <__aeabi_idiv0>
80001e0: f1ad 0c08 sub.w ip, sp, #8
80001e4: e96d ce04 strd ip, lr, [sp, #-16]!
80001e8: f000 f806 bl 80001f8 <__udivmoddi4>
80001ec: f8dd e004 ldr.w lr, [sp, #4]
80001f0: e9dd 2302 ldrd r2, r3, [sp, #8]
80001f4: b004 add sp, #16
80001f6: 4770 bx lr
080001f8 <__udivmoddi4>:
80001f8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80001fc: 9e08 ldr r6, [sp, #32]
80001fe: 460d mov r5, r1
8000200: 4604 mov r4, r0
8000202: 460f mov r7, r1
8000204: 2b00 cmp r3, #0
8000206: d14a bne.n 800029e <__udivmoddi4+0xa6>
8000208: 428a cmp r2, r1
800020a: 4694 mov ip, r2
800020c: d965 bls.n 80002da <__udivmoddi4+0xe2>
800020e: fab2 f382 clz r3, r2
8000212: b143 cbz r3, 8000226 <__udivmoddi4+0x2e>
8000214: fa02 fc03 lsl.w ip, r2, r3
8000218: f1c3 0220 rsb r2, r3, #32
800021c: 409f lsls r7, r3
800021e: fa20 f202 lsr.w r2, r0, r2
8000222: 4317 orrs r7, r2
8000224: 409c lsls r4, r3
8000226: ea4f 4e1c mov.w lr, ip, lsr #16
800022a: fa1f f58c uxth.w r5, ip
800022e: fbb7 f1fe udiv r1, r7, lr
8000232: 0c22 lsrs r2, r4, #16
8000234: fb0e 7711 mls r7, lr, r1, r7
8000238: ea42 4207 orr.w r2, r2, r7, lsl #16
800023c: fb01 f005 mul.w r0, r1, r5
8000240: 4290 cmp r0, r2
8000242: d90a bls.n 800025a <__udivmoddi4+0x62>
8000244: eb1c 0202 adds.w r2, ip, r2
8000248: f101 37ff add.w r7, r1, #4294967295
800024c: f080 811c bcs.w 8000488 <__udivmoddi4+0x290>
8000250: 4290 cmp r0, r2
8000252: f240 8119 bls.w 8000488 <__udivmoddi4+0x290>
8000256: 3902 subs r1, #2
8000258: 4462 add r2, ip
800025a: 1a12 subs r2, r2, r0
800025c: b2a4 uxth r4, r4
800025e: fbb2 f0fe udiv r0, r2, lr
8000262: fb0e 2210 mls r2, lr, r0, r2
8000266: ea44 4402 orr.w r4, r4, r2, lsl #16
800026a: fb00 f505 mul.w r5, r0, r5
800026e: 42a5 cmp r5, r4
8000270: d90a bls.n 8000288 <__udivmoddi4+0x90>
8000272: eb1c 0404 adds.w r4, ip, r4
8000276: f100 32ff add.w r2, r0, #4294967295
800027a: f080 8107 bcs.w 800048c <__udivmoddi4+0x294>
800027e: 42a5 cmp r5, r4
8000280: f240 8104 bls.w 800048c <__udivmoddi4+0x294>
8000284: 4464 add r4, ip
8000286: 3802 subs r0, #2
8000288: ea40 4001 orr.w r0, r0, r1, lsl #16
800028c: 1b64 subs r4, r4, r5
800028e: 2100 movs r1, #0
8000290: b11e cbz r6, 800029a <__udivmoddi4+0xa2>
8000292: 40dc lsrs r4, r3
8000294: 2300 movs r3, #0
8000296: e9c6 4300 strd r4, r3, [r6]
800029a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800029e: 428b cmp r3, r1
80002a0: d908 bls.n 80002b4 <__udivmoddi4+0xbc>
80002a2: 2e00 cmp r6, #0
80002a4: f000 80ed beq.w 8000482 <__udivmoddi4+0x28a>
80002a8: 2100 movs r1, #0
80002aa: e9c6 0500 strd r0, r5, [r6]
80002ae: 4608 mov r0, r1
80002b0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002b4: fab3 f183 clz r1, r3
80002b8: 2900 cmp r1, #0
80002ba: d149 bne.n 8000350 <__udivmoddi4+0x158>
80002bc: 42ab cmp r3, r5
80002be: d302 bcc.n 80002c6 <__udivmoddi4+0xce>
80002c0: 4282 cmp r2, r0
80002c2: f200 80f8 bhi.w 80004b6 <__udivmoddi4+0x2be>
80002c6: 1a84 subs r4, r0, r2
80002c8: eb65 0203 sbc.w r2, r5, r3
80002cc: 2001 movs r0, #1
80002ce: 4617 mov r7, r2
80002d0: 2e00 cmp r6, #0
80002d2: d0e2 beq.n 800029a <__udivmoddi4+0xa2>
80002d4: e9c6 4700 strd r4, r7, [r6]
80002d8: e7df b.n 800029a <__udivmoddi4+0xa2>
80002da: b902 cbnz r2, 80002de <__udivmoddi4+0xe6>
80002dc: deff udf #255 ; 0xff
80002de: fab2 f382 clz r3, r2
80002e2: 2b00 cmp r3, #0
80002e4: f040 8090 bne.w 8000408 <__udivmoddi4+0x210>
80002e8: 1a8a subs r2, r1, r2
80002ea: ea4f 471c mov.w r7, ip, lsr #16
80002ee: fa1f fe8c uxth.w lr, ip
80002f2: 2101 movs r1, #1
80002f4: fbb2 f5f7 udiv r5, r2, r7
80002f8: fb07 2015 mls r0, r7, r5, r2
80002fc: 0c22 lsrs r2, r4, #16
80002fe: ea42 4200 orr.w r2, r2, r0, lsl #16
8000302: fb0e f005 mul.w r0, lr, r5
8000306: 4290 cmp r0, r2
8000308: d908 bls.n 800031c <__udivmoddi4+0x124>
800030a: eb1c 0202 adds.w r2, ip, r2
800030e: f105 38ff add.w r8, r5, #4294967295
8000312: d202 bcs.n 800031a <__udivmoddi4+0x122>
8000314: 4290 cmp r0, r2
8000316: f200 80cb bhi.w 80004b0 <__udivmoddi4+0x2b8>
800031a: 4645 mov r5, r8
800031c: 1a12 subs r2, r2, r0
800031e: b2a4 uxth r4, r4
8000320: fbb2 f0f7 udiv r0, r2, r7
8000324: fb07 2210 mls r2, r7, r0, r2
8000328: ea44 4402 orr.w r4, r4, r2, lsl #16
800032c: fb0e fe00 mul.w lr, lr, r0
8000330: 45a6 cmp lr, r4
8000332: d908 bls.n 8000346 <__udivmoddi4+0x14e>
8000334: eb1c 0404 adds.w r4, ip, r4
8000338: f100 32ff add.w r2, r0, #4294967295
800033c: d202 bcs.n 8000344 <__udivmoddi4+0x14c>
800033e: 45a6 cmp lr, r4
8000340: f200 80bb bhi.w 80004ba <__udivmoddi4+0x2c2>
8000344: 4610 mov r0, r2
8000346: eba4 040e sub.w r4, r4, lr
800034a: ea40 4005 orr.w r0, r0, r5, lsl #16
800034e: e79f b.n 8000290 <__udivmoddi4+0x98>
8000350: f1c1 0720 rsb r7, r1, #32
8000354: 408b lsls r3, r1
8000356: fa22 fc07 lsr.w ip, r2, r7
800035a: ea4c 0c03 orr.w ip, ip, r3
800035e: fa05 f401 lsl.w r4, r5, r1
8000362: fa20 f307 lsr.w r3, r0, r7
8000366: 40fd lsrs r5, r7
8000368: ea4f 491c mov.w r9, ip, lsr #16
800036c: 4323 orrs r3, r4
800036e: fbb5 f8f9 udiv r8, r5, r9
8000372: fa1f fe8c uxth.w lr, ip
8000376: fb09 5518 mls r5, r9, r8, r5
800037a: 0c1c lsrs r4, r3, #16
800037c: ea44 4405 orr.w r4, r4, r5, lsl #16
8000380: fb08 f50e mul.w r5, r8, lr
8000384: 42a5 cmp r5, r4
8000386: fa02 f201 lsl.w r2, r2, r1
800038a: fa00 f001 lsl.w r0, r0, r1
800038e: d90b bls.n 80003a8 <__udivmoddi4+0x1b0>
8000390: eb1c 0404 adds.w r4, ip, r4
8000394: f108 3aff add.w sl, r8, #4294967295
8000398: f080 8088 bcs.w 80004ac <__udivmoddi4+0x2b4>
800039c: 42a5 cmp r5, r4
800039e: f240 8085 bls.w 80004ac <__udivmoddi4+0x2b4>
80003a2: f1a8 0802 sub.w r8, r8, #2
80003a6: 4464 add r4, ip
80003a8: 1b64 subs r4, r4, r5
80003aa: b29d uxth r5, r3
80003ac: fbb4 f3f9 udiv r3, r4, r9
80003b0: fb09 4413 mls r4, r9, r3, r4
80003b4: ea45 4404 orr.w r4, r5, r4, lsl #16
80003b8: fb03 fe0e mul.w lr, r3, lr
80003bc: 45a6 cmp lr, r4
80003be: d908 bls.n 80003d2 <__udivmoddi4+0x1da>
80003c0: eb1c 0404 adds.w r4, ip, r4
80003c4: f103 35ff add.w r5, r3, #4294967295
80003c8: d26c bcs.n 80004a4 <__udivmoddi4+0x2ac>
80003ca: 45a6 cmp lr, r4
80003cc: d96a bls.n 80004a4 <__udivmoddi4+0x2ac>
80003ce: 3b02 subs r3, #2
80003d0: 4464 add r4, ip
80003d2: ea43 4308 orr.w r3, r3, r8, lsl #16
80003d6: fba3 9502 umull r9, r5, r3, r2
80003da: eba4 040e sub.w r4, r4, lr
80003de: 42ac cmp r4, r5
80003e0: 46c8 mov r8, r9
80003e2: 46ae mov lr, r5
80003e4: d356 bcc.n 8000494 <__udivmoddi4+0x29c>
80003e6: d053 beq.n 8000490 <__udivmoddi4+0x298>
80003e8: b156 cbz r6, 8000400 <__udivmoddi4+0x208>
80003ea: ebb0 0208 subs.w r2, r0, r8
80003ee: eb64 040e sbc.w r4, r4, lr
80003f2: fa04 f707 lsl.w r7, r4, r7
80003f6: 40ca lsrs r2, r1
80003f8: 40cc lsrs r4, r1
80003fa: 4317 orrs r7, r2
80003fc: e9c6 7400 strd r7, r4, [r6]
8000400: 4618 mov r0, r3
8000402: 2100 movs r1, #0
8000404: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000408: f1c3 0120 rsb r1, r3, #32
800040c: fa02 fc03 lsl.w ip, r2, r3
8000410: fa20 f201 lsr.w r2, r0, r1
8000414: fa25 f101 lsr.w r1, r5, r1
8000418: 409d lsls r5, r3
800041a: 432a orrs r2, r5
800041c: ea4f 471c mov.w r7, ip, lsr #16
8000420: fa1f fe8c uxth.w lr, ip
8000424: fbb1 f0f7 udiv r0, r1, r7
8000428: fb07 1510 mls r5, r7, r0, r1
800042c: 0c11 lsrs r1, r2, #16
800042e: ea41 4105 orr.w r1, r1, r5, lsl #16
8000432: fb00 f50e mul.w r5, r0, lr
8000436: 428d cmp r5, r1
8000438: fa04 f403 lsl.w r4, r4, r3
800043c: d908 bls.n 8000450 <__udivmoddi4+0x258>
800043e: eb1c 0101 adds.w r1, ip, r1
8000442: f100 38ff add.w r8, r0, #4294967295
8000446: d22f bcs.n 80004a8 <__udivmoddi4+0x2b0>
8000448: 428d cmp r5, r1
800044a: d92d bls.n 80004a8 <__udivmoddi4+0x2b0>
800044c: 3802 subs r0, #2
800044e: 4461 add r1, ip
8000450: 1b49 subs r1, r1, r5
8000452: b292 uxth r2, r2
8000454: fbb1 f5f7 udiv r5, r1, r7
8000458: fb07 1115 mls r1, r7, r5, r1
800045c: ea42 4201 orr.w r2, r2, r1, lsl #16
8000460: fb05 f10e mul.w r1, r5, lr
8000464: 4291 cmp r1, r2
8000466: d908 bls.n 800047a <__udivmoddi4+0x282>
8000468: eb1c 0202 adds.w r2, ip, r2
800046c: f105 38ff add.w r8, r5, #4294967295
8000470: d216 bcs.n 80004a0 <__udivmoddi4+0x2a8>
8000472: 4291 cmp r1, r2
8000474: d914 bls.n 80004a0 <__udivmoddi4+0x2a8>
8000476: 3d02 subs r5, #2
8000478: 4462 add r2, ip
800047a: 1a52 subs r2, r2, r1
800047c: ea45 4100 orr.w r1, r5, r0, lsl #16
8000480: e738 b.n 80002f4 <__udivmoddi4+0xfc>
8000482: 4631 mov r1, r6
8000484: 4630 mov r0, r6
8000486: e708 b.n 800029a <__udivmoddi4+0xa2>
8000488: 4639 mov r1, r7
800048a: e6e6 b.n 800025a <__udivmoddi4+0x62>
800048c: 4610 mov r0, r2
800048e: e6fb b.n 8000288 <__udivmoddi4+0x90>
8000490: 4548 cmp r0, r9
8000492: d2a9 bcs.n 80003e8 <__udivmoddi4+0x1f0>
8000494: ebb9 0802 subs.w r8, r9, r2
8000498: eb65 0e0c sbc.w lr, r5, ip
800049c: 3b01 subs r3, #1
800049e: e7a3 b.n 80003e8 <__udivmoddi4+0x1f0>
80004a0: 4645 mov r5, r8
80004a2: e7ea b.n 800047a <__udivmoddi4+0x282>
80004a4: 462b mov r3, r5
80004a6: e794 b.n 80003d2 <__udivmoddi4+0x1da>
80004a8: 4640 mov r0, r8
80004aa: e7d1 b.n 8000450 <__udivmoddi4+0x258>
80004ac: 46d0 mov r8, sl
80004ae: e77b b.n 80003a8 <__udivmoddi4+0x1b0>
80004b0: 3d02 subs r5, #2
80004b2: 4462 add r2, ip
80004b4: e732 b.n 800031c <__udivmoddi4+0x124>
80004b6: 4608 mov r0, r1
80004b8: e70a b.n 80002d0 <__udivmoddi4+0xd8>
80004ba: 4464 add r4, ip
80004bc: 3802 subs r0, #2
80004be: e742 b.n 8000346 <__udivmoddi4+0x14e>
080004c0 <__aeabi_idiv0>:
80004c0: 4770 bx lr
80004c2: bf00 nop
080004c4 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80004c4: b580 push {r7, lr}
80004c6: b08a sub sp, #40 ; 0x28
80004c8: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80004ca: f000 fd03 bl 8000ed4 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80004ce: f000 f8c9 bl 8000664 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80004d2: f000 fa6d bl 80009b0 <MX_GPIO_Init>
MX_SPI1_Init();
80004d6: f000 f921 bl 800071c <MX_SPI1_Init>
MX_TIM2_Init();
80004da: f000 f9f3 bl 80008c4 <MX_TIM2_Init>
MX_TIM1_Init();
80004de: f000 f94f bl 8000780 <MX_TIM1_Init>
/* USER CODE BEGIN 2 */
struct mode modes[CHANNELS];
modes[0].time_mode = 5; // время работы в данном режиме, секунды (задается)
80004e2: 2305 movs r3, #5
80004e4: 713b strb r3, [r7, #4]
modes[0].pwm_value = 35000; // скважность для данного режими (задается)
80004e6: f648 03b8 movw r3, #35000 ; 0x88b8
80004ea: 80fb strh r3, [r7, #6]
modes[0].f = 40; // частота импульсной последовательности, Гц (задается)
80004ec: 2328 movs r3, #40 ; 0x28
80004ee: 723b strb r3, [r7, #8]
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1, GPIO_PIN_RESET);
80004f0: 2200 movs r2, #0
80004f2: 2102 movs r1, #2
80004f4: 4852 ldr r0, [pc, #328] ; (8000640 <main+0x17c>)
80004f6: f001 f80d bl 8001514 <HAL_GPIO_WritePin>
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
if (modes[0].time_mode >= 0 && modes[0].pwm_value > 0 && modes[0].f > 0) { // проверяем введенные данные
80004fa: 88fb ldrh r3, [r7, #6]
80004fc: 2b00 cmp r3, #0
80004fe: d0fc beq.n 80004fa <main+0x36>
8000500: 7a3b ldrb r3, [r7, #8]
8000502: 2b00 cmp r3, #0
8000504: d0f9 beq.n 80004fa <main+0x36>
uint8_t T = 1000 / modes[0].f; // период следования импульсов
8000506: 7a3b ldrb r3, [r7, #8]
8000508: 461a mov r2, r3
800050a: f44f 737a mov.w r3, #1000 ; 0x3e8
800050e: fb93 f3f2 sdiv r3, r3, r2
8000512: f887 3027 strb.w r3, [r7, #39] ; 0x27
// Считаем, какая частота таймера нужна для получения заданного периода T
uint32_t freq_T_check = (F_CPU * T) / 1000;
8000516: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
800051a: f645 52c0 movw r2, #24000 ; 0x5dc0
800051e: fb02 f303 mul.w r3, r2, r3
8000522: 623b str r3, [r7, #32]
// Если частота больше максимально допустимой 65536 - добавляем предделитель
if (freq_T_check >= MAX_PWM_FREQ) {
8000524: 6a3b ldr r3, [r7, #32]
8000526: f64f 72fe movw r2, #65534 ; 0xfffe
800052a: 4293 cmp r3, r2
800052c: d9e5 bls.n 80004fa <main+0x36>
// Делим полученную выше частоту на максимально допустимую (65536) - получаем значение предделителя
modes[0].coef = freq_T_check / MAX_PWM_FREQ;
800052e: 6a3b ldr r3, [r7, #32]
8000530: 4a44 ldr r2, [pc, #272] ; (8000644 <main+0x180>)
8000532: fba2 2303 umull r2, r3, r2, r3
8000536: 0bdb lsrs r3, r3, #15
8000538: b2db uxtb r3, r3
800053a: 727b strb r3, [r7, #9]
// Округляем предделитель в большую сторону для запаса, если необходимо
if (freq_T_check % MAX_PWM_FREQ != 0) {
800053c: 6a39 ldr r1, [r7, #32]
800053e: 4b41 ldr r3, [pc, #260] ; (8000644 <main+0x180>)
8000540: fba3 2301 umull r2, r3, r3, r1
8000544: 0bda lsrs r2, r3, #15
8000546: 4613 mov r3, r2
8000548: 041b lsls r3, r3, #16
800054a: 1a9b subs r3, r3, r2
800054c: 1aca subs r2, r1, r3
800054e: 2a00 cmp r2, #0
8000550: d003 beq.n 800055a <main+0x96>
modes[0].coef++;
8000552: 7a7b ldrb r3, [r7, #9]
8000554: 3301 adds r3, #1
8000556: b2db uxtb r3, r3
8000558: 727b strb r3, [r7, #9]
}
// Частота от процессора после прохождения предделителя
int F_tmp = F_CPU / modes[0].coef;
800055a: 7a7b ldrb r3, [r7, #9]
800055c: 461a mov r2, r3
800055e: 4b3a ldr r3, [pc, #232] ; (8000648 <main+0x184>)
8000560: fb93 f3f2 sdiv r3, r3, r2
8000564: 61fb str r3, [r7, #28]
// Считаем частоту таймера нужна для получения заданного периода T (с новым значением частоты процессора)
modes[0].freq_pwm_new = (F_tmp * T) / 1000;
8000566: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
800056a: 69fa ldr r2, [r7, #28]
800056c: fb02 f303 mul.w r3, r2, r3
8000570: 4a36 ldr r2, [pc, #216] ; (800064c <main+0x188>)
8000572: fb82 1203 smull r1, r2, r2, r3
8000576: 1192 asrs r2, r2, #6
8000578: 17db asrs r3, r3, #31
800057a: 1ad3 subs r3, r2, r3
800057c: b29b uxth r3, r3
800057e: 817b strh r3, [r7, #10]
// Если все успешно - получим значение меньше 65536
if (modes[0].freq_pwm_new <= MAX_PWM_FREQ && channel == 1 && flag == 0) {
8000580: 4b33 ldr r3, [pc, #204] ; (8000650 <main+0x18c>)
8000582: 681b ldr r3, [r3, #0]
8000584: 2b01 cmp r3, #1
8000586: d13d bne.n 8000604 <main+0x140>
8000588: 4b32 ldr r3, [pc, #200] ; (8000654 <main+0x190>)
800058a: 681b ldr r3, [r3, #0]
800058c: 2b00 cmp r3, #0
800058e: d139 bne.n 8000604 <main+0x140>
modes[0].pwm_value_res = (modes[0].pwm_value * modes[0].freq_pwm_new) / MAX_PWM_FREQ;
8000590: 88fb ldrh r3, [r7, #6]
8000592: 897a ldrh r2, [r7, #10]
8000594: fb02 f303 mul.w r3, r2, r3
8000598: 4a2a ldr r2, [pc, #168] ; (8000644 <main+0x180>)
800059a: fb82 1203 smull r1, r2, r2, r3
800059e: 441a add r2, r3
80005a0: 13d2 asrs r2, r2, #15
80005a2: 17db asrs r3, r3, #31
80005a4: 1ad3 subs r3, r2, r3
80005a6: b29b uxth r3, r3
80005a8: 81bb strh r3, [r7, #12]
PWM_Init(modes[0].coef-1, modes[0].freq_pwm_new-1, modes[0].pwm_value_res);
80005aa: 7a7b ldrb r3, [r7, #9]
80005ac: 3b01 subs r3, #1
80005ae: b2d8 uxtb r0, r3
80005b0: 897b ldrh r3, [r7, #10]
80005b2: 3b01 subs r3, #1
80005b4: b29b uxth r3, r3
80005b6: 89ba ldrh r2, [r7, #12]
80005b8: 4619 mov r1, r3
80005ba: f000 fa7b bl 8000ab4 <PWM_Init>
uint16_t time_to_tick = modes[0].time_mode * F_CPU_TIM1; // время * 366 (24 000 000 / 65 536)
80005be: 793b ldrb r3, [r7, #4]
80005c0: b29b uxth r3, r3
80005c2: 461a mov r2, r3
80005c4: 0112 lsls r2, r2, #4
80005c6: 1ad2 subs r2, r2, r3
80005c8: 0092 lsls r2, r2, #2
80005ca: 4413 add r3, r2
80005cc: 461a mov r2, r3
80005ce: 0092 lsls r2, r2, #2
80005d0: 1ad3 subs r3, r2, r3
80005d2: 005b lsls r3, r3, #1
80005d4: 837b strh r3, [r7, #26]
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); // запуск PWM на таймер 2 канал 1
80005d6: 2100 movs r1, #0
80005d8: 481f ldr r0, [pc, #124] ; (8000658 <main+0x194>)
80005da: f001 fded bl 80021b8 <HAL_TIM_PWM_Start>
__HAL_TIM_SET_AUTORELOAD(&htim1, time_to_tick); // перенастройка period под заданное пользователем время
80005de: 4b1f ldr r3, [pc, #124] ; (800065c <main+0x198>)
80005e0: 681b ldr r3, [r3, #0]
80005e2: 8b7a ldrh r2, [r7, #26]
80005e4: 62da str r2, [r3, #44] ; 0x2c
80005e6: 8b7b ldrh r3, [r7, #26]
80005e8: 4a1c ldr r2, [pc, #112] ; (800065c <main+0x198>)
80005ea: 60d3 str r3, [r2, #12]
__HAL_TIM_SET_COUNTER(&htim1, time_to_tick - 1); // начинаем счет не с 0, а с (max - 1) значения - избавляемся от прерывания сразу после старта
80005ec: 8b7b ldrh r3, [r7, #26]
80005ee: 1e5a subs r2, r3, #1
80005f0: 4b1a ldr r3, [pc, #104] ; (800065c <main+0x198>)
80005f2: 681b ldr r3, [r3, #0]
80005f4: 625a str r2, [r3, #36] ; 0x24
HAL_TIM_Base_Start_IT(&htim1); // запускает таймер 1 для прерываний
80005f6: 4819 ldr r0, [pc, #100] ; (800065c <main+0x198>)
80005f8: f001 fcbc bl 8001f74 <HAL_TIM_Base_Start_IT>
flag = 1;
80005fc: 4b15 ldr r3, [pc, #84] ; (8000654 <main+0x190>)
80005fe: 2201 movs r2, #1
8000600: 601a str r2, [r3, #0]
if (modes[0].freq_pwm_new <= MAX_PWM_FREQ && channel == 1 && flag == 0) {
8000602: e01b b.n 800063c <main+0x178>
} else if (channel == 2) {
8000604: 4b12 ldr r3, [pc, #72] ; (8000650 <main+0x18c>)
8000606: 681b ldr r3, [r3, #0]
8000608: 2b02 cmp r3, #2
800060a: d109 bne.n 8000620 <main+0x15c>
HAL_TIM_PWM_Stop(&htim2, TIM_CHANNEL_1); // запуск PWM на таймер 2 канал 1
800060c: 2100 movs r1, #0
800060e: 4812 ldr r0, [pc, #72] ; (8000658 <main+0x194>)
8000610: f001 fe9a bl 8002348 <HAL_TIM_PWM_Stop>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_RESET);
8000614: 2200 movs r2, #0
8000616: 2101 movs r1, #1
8000618: 4811 ldr r0, [pc, #68] ; (8000660 <main+0x19c>)
800061a: f000 ff7b bl 8001514 <HAL_GPIO_WritePin>
800061e: e76c b.n 80004fa <main+0x36>
}
else if(channel == 1 && flag == 1){
8000620: 4b0b ldr r3, [pc, #44] ; (8000650 <main+0x18c>)
8000622: 681b ldr r3, [r3, #0]
8000624: 2b01 cmp r3, #1
8000626: f47f af68 bne.w 80004fa <main+0x36>
800062a: 4b0a ldr r3, [pc, #40] ; (8000654 <main+0x190>)
800062c: 681b ldr r3, [r3, #0]
800062e: 2b01 cmp r3, #1
8000630: f47f af63 bne.w 80004fa <main+0x36>
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
8000634: 2100 movs r1, #0
8000636: 4808 ldr r0, [pc, #32] ; (8000658 <main+0x194>)
8000638: f001 fdbe bl 80021b8 <HAL_TIM_PWM_Start>
if (modes[0].time_mode >= 0 && modes[0].pwm_value > 0 && modes[0].f > 0) { // проверяем введенные данные
800063c: e75d b.n 80004fa <main+0x36>
800063e: bf00 nop
8000640: 40020800 .word 0x40020800
8000644: 80008001 .word 0x80008001
8000648: 016e3600 .word 0x016e3600
800064c: 10624dd3 .word 0x10624dd3
8000650: 20000000 .word 0x20000000
8000654: 20000114 .word 0x20000114
8000658: 200000cc .word 0x200000cc
800065c: 20000084 .word 0x20000084
8000660: 40020000 .word 0x40020000
08000664 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000664: b580 push {r7, lr}
8000666: b094 sub sp, #80 ; 0x50
8000668: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800066a: f107 0320 add.w r3, r7, #32
800066e: 2230 movs r2, #48 ; 0x30
8000670: 2100 movs r1, #0
8000672: 4618 mov r0, r3
8000674: f002 fdea bl 800324c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000678: f107 030c add.w r3, r7, #12
800067c: 2200 movs r2, #0
800067e: 601a str r2, [r3, #0]
8000680: 605a str r2, [r3, #4]
8000682: 609a str r2, [r3, #8]
8000684: 60da str r2, [r3, #12]
8000686: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000688: 2300 movs r3, #0
800068a: 60bb str r3, [r7, #8]
800068c: 4b21 ldr r3, [pc, #132] ; (8000714 <SystemClock_Config+0xb0>)
800068e: 6c1b ldr r3, [r3, #64] ; 0x40
8000690: 4a20 ldr r2, [pc, #128] ; (8000714 <SystemClock_Config+0xb0>)
8000692: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000696: 6413 str r3, [r2, #64] ; 0x40
8000698: 4b1e ldr r3, [pc, #120] ; (8000714 <SystemClock_Config+0xb0>)
800069a: 6c1b ldr r3, [r3, #64] ; 0x40
800069c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80006a0: 60bb str r3, [r7, #8]
80006a2: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
80006a4: 2300 movs r3, #0
80006a6: 607b str r3, [r7, #4]
80006a8: 4b1b ldr r3, [pc, #108] ; (8000718 <SystemClock_Config+0xb4>)
80006aa: 681b ldr r3, [r3, #0]
80006ac: 4a1a ldr r2, [pc, #104] ; (8000718 <SystemClock_Config+0xb4>)
80006ae: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80006b2: 6013 str r3, [r2, #0]
80006b4: 4b18 ldr r3, [pc, #96] ; (8000718 <SystemClock_Config+0xb4>)
80006b6: 681b ldr r3, [r3, #0]
80006b8: f403 4380 and.w r3, r3, #16384 ; 0x4000
80006bc: 607b str r3, [r7, #4]
80006be: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80006c0: 2301 movs r3, #1
80006c2: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
80006c4: f44f 23a0 mov.w r3, #327680 ; 0x50000
80006c8: 627b str r3, [r7, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
80006ca: 2300 movs r3, #0
80006cc: 63bb str r3, [r7, #56] ; 0x38
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80006ce: f107 0320 add.w r3, r7, #32
80006d2: 4618 mov r0, r3
80006d4: f000 ff52 bl 800157c <HAL_RCC_OscConfig>
80006d8: 4603 mov r3, r0
80006da: 2b00 cmp r3, #0
80006dc: d001 beq.n 80006e2 <SystemClock_Config+0x7e>
{
Error_Handler();
80006de: f000 fa65 bl 8000bac <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80006e2: 230f movs r3, #15
80006e4: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
80006e6: 2301 movs r3, #1
80006e8: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80006ea: 2300 movs r3, #0
80006ec: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80006ee: 2300 movs r3, #0
80006f0: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80006f2: 2300 movs r3, #0
80006f4: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80006f6: f107 030c add.w r3, r7, #12
80006fa: 2100 movs r1, #0
80006fc: 4618 mov r0, r3
80006fe: f001 f9b5 bl 8001a6c <HAL_RCC_ClockConfig>
8000702: 4603 mov r3, r0
8000704: 2b00 cmp r3, #0
8000706: d001 beq.n 800070c <SystemClock_Config+0xa8>
{
Error_Handler();
8000708: f000 fa50 bl 8000bac <Error_Handler>
}
}
800070c: bf00 nop
800070e: 3750 adds r7, #80 ; 0x50
8000710: 46bd mov sp, r7
8000712: bd80 pop {r7, pc}
8000714: 40023800 .word 0x40023800
8000718: 40007000 .word 0x40007000
0800071c <MX_SPI1_Init>:
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
800071c: b580 push {r7, lr}
800071e: af00 add r7, sp, #0
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
8000720: 4b15 ldr r3, [pc, #84] ; (8000778 <MX_SPI1_Init+0x5c>)
8000722: 4a16 ldr r2, [pc, #88] ; (800077c <MX_SPI1_Init+0x60>)
8000724: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_SLAVE;
8000726: 4b14 ldr r3, [pc, #80] ; (8000778 <MX_SPI1_Init+0x5c>)
8000728: 2200 movs r2, #0
800072a: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
800072c: 4b12 ldr r3, [pc, #72] ; (8000778 <MX_SPI1_Init+0x5c>)
800072e: 2200 movs r2, #0
8000730: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
8000732: 4b11 ldr r3, [pc, #68] ; (8000778 <MX_SPI1_Init+0x5c>)
8000734: 2200 movs r2, #0
8000736: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
8000738: 4b0f ldr r3, [pc, #60] ; (8000778 <MX_SPI1_Init+0x5c>)
800073a: 2200 movs r2, #0
800073c: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
800073e: 4b0e ldr r3, [pc, #56] ; (8000778 <MX_SPI1_Init+0x5c>)
8000740: 2200 movs r2, #0
8000742: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_HARD_INPUT;
8000744: 4b0c ldr r3, [pc, #48] ; (8000778 <MX_SPI1_Init+0x5c>)
8000746: 2200 movs r2, #0
8000748: 619a str r2, [r3, #24]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
800074a: 4b0b ldr r3, [pc, #44] ; (8000778 <MX_SPI1_Init+0x5c>)
800074c: 2200 movs r2, #0
800074e: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
8000750: 4b09 ldr r3, [pc, #36] ; (8000778 <MX_SPI1_Init+0x5c>)
8000752: 2200 movs r2, #0
8000754: 625a str r2, [r3, #36] ; 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000756: 4b08 ldr r3, [pc, #32] ; (8000778 <MX_SPI1_Init+0x5c>)
8000758: 2200 movs r2, #0
800075a: 629a str r2, [r3, #40] ; 0x28
hspi1.Init.CRCPolynomial = 10;
800075c: 4b06 ldr r3, [pc, #24] ; (8000778 <MX_SPI1_Init+0x5c>)
800075e: 220a movs r2, #10
8000760: 62da str r2, [r3, #44] ; 0x2c
if (HAL_SPI_Init(&hspi1) != HAL_OK)
8000762: 4805 ldr r0, [pc, #20] ; (8000778 <MX_SPI1_Init+0x5c>)
8000764: f001 fb2e bl 8001dc4 <HAL_SPI_Init>
8000768: 4603 mov r3, r0
800076a: 2b00 cmp r3, #0
800076c: d001 beq.n 8000772 <MX_SPI1_Init+0x56>
{
Error_Handler();
800076e: f000 fa1d bl 8000bac <Error_Handler>
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
8000772: bf00 nop
8000774: bd80 pop {r7, pc}
8000776: bf00 nop
8000778: 2000002c .word 0x2000002c
800077c: 40013000 .word 0x40013000
08000780 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
8000780: b580 push {r7, lr}
8000782: b096 sub sp, #88 ; 0x58
8000784: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000786: f107 0348 add.w r3, r7, #72 ; 0x48
800078a: 2200 movs r2, #0
800078c: 601a str r2, [r3, #0]
800078e: 605a str r2, [r3, #4]
8000790: 609a str r2, [r3, #8]
8000792: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000794: f107 0340 add.w r3, r7, #64 ; 0x40
8000798: 2200 movs r2, #0
800079a: 601a str r2, [r3, #0]
800079c: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
800079e: f107 0324 add.w r3, r7, #36 ; 0x24
80007a2: 2200 movs r2, #0
80007a4: 601a str r2, [r3, #0]
80007a6: 605a str r2, [r3, #4]
80007a8: 609a str r2, [r3, #8]
80007aa: 60da str r2, [r3, #12]
80007ac: 611a str r2, [r3, #16]
80007ae: 615a str r2, [r3, #20]
80007b0: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
80007b2: 1d3b adds r3, r7, #4
80007b4: 2220 movs r2, #32
80007b6: 2100 movs r1, #0
80007b8: 4618 mov r0, r3
80007ba: f002 fd47 bl 800324c <memset>
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
80007be: 4b3f ldr r3, [pc, #252] ; (80008bc <MX_TIM1_Init+0x13c>)
80007c0: 4a3f ldr r2, [pc, #252] ; (80008c0 <MX_TIM1_Init+0x140>)
80007c2: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 65535;
80007c4: 4b3d ldr r3, [pc, #244] ; (80008bc <MX_TIM1_Init+0x13c>)
80007c6: f64f 72ff movw r2, #65535 ; 0xffff
80007ca: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
80007cc: 4b3b ldr r3, [pc, #236] ; (80008bc <MX_TIM1_Init+0x13c>)
80007ce: 2200 movs r2, #0
80007d0: 609a str r2, [r3, #8]
htim1.Init.Period = 1830;
80007d2: 4b3a ldr r3, [pc, #232] ; (80008bc <MX_TIM1_Init+0x13c>)
80007d4: f240 7226 movw r2, #1830 ; 0x726
80007d8: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80007da: 4b38 ldr r3, [pc, #224] ; (80008bc <MX_TIM1_Init+0x13c>)
80007dc: 2200 movs r2, #0
80007de: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
80007e0: 4b36 ldr r3, [pc, #216] ; (80008bc <MX_TIM1_Init+0x13c>)
80007e2: 2200 movs r2, #0
80007e4: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80007e6: 4b35 ldr r3, [pc, #212] ; (80008bc <MX_TIM1_Init+0x13c>)
80007e8: 2200 movs r2, #0
80007ea: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
80007ec: 4833 ldr r0, [pc, #204] ; (80008bc <MX_TIM1_Init+0x13c>)
80007ee: f001 fb72 bl 8001ed6 <HAL_TIM_Base_Init>
80007f2: 4603 mov r3, r0
80007f4: 2b00 cmp r3, #0
80007f6: d001 beq.n 80007fc <MX_TIM1_Init+0x7c>
{
Error_Handler();
80007f8: f000 f9d8 bl 8000bac <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80007fc: f44f 5380 mov.w r3, #4096 ; 0x1000
8000800: 64bb str r3, [r7, #72] ; 0x48
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8000802: f107 0348 add.w r3, r7, #72 ; 0x48
8000806: 4619 mov r1, r3
8000808: 482c ldr r0, [pc, #176] ; (80008bc <MX_TIM1_Init+0x13c>)
800080a: f002 f833 bl 8002874 <HAL_TIM_ConfigClockSource>
800080e: 4603 mov r3, r0
8000810: 2b00 cmp r3, #0
8000812: d001 beq.n 8000818 <MX_TIM1_Init+0x98>
{
Error_Handler();
8000814: f000 f9ca bl 8000bac <Error_Handler>
}
if (HAL_TIM_OC_Init(&htim1) != HAL_OK)
8000818: 4828 ldr r0, [pc, #160] ; (80008bc <MX_TIM1_Init+0x13c>)
800081a: f001 fc1b bl 8002054 <HAL_TIM_OC_Init>
800081e: 4603 mov r3, r0
8000820: 2b00 cmp r3, #0
8000822: d001 beq.n 8000828 <MX_TIM1_Init+0xa8>
{
Error_Handler();
8000824: f000 f9c2 bl 8000bac <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000828: 2300 movs r3, #0
800082a: 643b str r3, [r7, #64] ; 0x40
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800082c: 2300 movs r3, #0
800082e: 647b str r3, [r7, #68] ; 0x44
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8000830: f107 0340 add.w r3, r7, #64 ; 0x40
8000834: 4619 mov r1, r3
8000836: 4821 ldr r0, [pc, #132] ; (80008bc <MX_TIM1_Init+0x13c>)
8000838: f002 fc26 bl 8003088 <HAL_TIMEx_MasterConfigSynchronization>
800083c: 4603 mov r3, r0
800083e: 2b00 cmp r3, #0
8000840: d001 beq.n 8000846 <MX_TIM1_Init+0xc6>
{
Error_Handler();
8000842: f000 f9b3 bl 8000bac <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_TIMING;
8000846: 2300 movs r3, #0
8000848: 627b str r3, [r7, #36] ; 0x24
sConfigOC.Pulse = 0;
800084a: 2300 movs r3, #0
800084c: 62bb str r3, [r7, #40] ; 0x28
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
800084e: 2300 movs r3, #0
8000850: 62fb str r3, [r7, #44] ; 0x2c
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
8000852: 2300 movs r3, #0
8000854: 633b str r3, [r7, #48] ; 0x30
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000856: 2300 movs r3, #0
8000858: 637b str r3, [r7, #52] ; 0x34
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
800085a: 2300 movs r3, #0
800085c: 63bb str r3, [r7, #56] ; 0x38
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
800085e: 2300 movs r3, #0
8000860: 63fb str r3, [r7, #60] ; 0x3c
if (HAL_TIM_OC_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000862: f107 0324 add.w r3, r7, #36 ; 0x24
8000866: 2200 movs r2, #0
8000868: 4619 mov r1, r3
800086a: 4814 ldr r0, [pc, #80] ; (80008bc <MX_TIM1_Init+0x13c>)
800086c: f001 fee4 bl 8002638 <HAL_TIM_OC_ConfigChannel>
8000870: 4603 mov r3, r0
8000872: 2b00 cmp r3, #0
8000874: d001 beq.n 800087a <MX_TIM1_Init+0xfa>
{
Error_Handler();
8000876: f000 f999 bl 8000bac <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
800087a: 2300 movs r3, #0
800087c: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
800087e: 2300 movs r3, #0
8000880: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8000882: 2300 movs r3, #0
8000884: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.DeadTime = 0;
8000886: 2300 movs r3, #0
8000888: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
800088a: 2300 movs r3, #0
800088c: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
800088e: f44f 5300 mov.w r3, #8192 ; 0x2000
8000892: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
8000894: 2300 movs r3, #0
8000896: 623b str r3, [r7, #32]
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
8000898: 1d3b adds r3, r7, #4
800089a: 4619 mov r1, r3
800089c: 4807 ldr r0, [pc, #28] ; (80008bc <MX_TIM1_Init+0x13c>)
800089e: f002 fc6f bl 8003180 <HAL_TIMEx_ConfigBreakDeadTime>
80008a2: 4603 mov r3, r0
80008a4: 2b00 cmp r3, #0
80008a6: d001 beq.n 80008ac <MX_TIM1_Init+0x12c>
{
Error_Handler();
80008a8: f000 f980 bl 8000bac <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
80008ac: 4803 ldr r0, [pc, #12] ; (80008bc <MX_TIM1_Init+0x13c>)
80008ae: f000 fa2f bl 8000d10 <HAL_TIM_MspPostInit>
}
80008b2: bf00 nop
80008b4: 3758 adds r7, #88 ; 0x58
80008b6: 46bd mov sp, r7
80008b8: bd80 pop {r7, pc}
80008ba: bf00 nop
80008bc: 20000084 .word 0x20000084
80008c0: 40010000 .word 0x40010000
080008c4 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
80008c4: b580 push {r7, lr}
80008c6: b08e sub sp, #56 ; 0x38
80008c8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80008ca: f107 0328 add.w r3, r7, #40 ; 0x28
80008ce: 2200 movs r2, #0
80008d0: 601a str r2, [r3, #0]
80008d2: 605a str r2, [r3, #4]
80008d4: 609a str r2, [r3, #8]
80008d6: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80008d8: f107 0320 add.w r3, r7, #32
80008dc: 2200 movs r2, #0
80008de: 601a str r2, [r3, #0]
80008e0: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
80008e2: 1d3b adds r3, r7, #4
80008e4: 2200 movs r2, #0
80008e6: 601a str r2, [r3, #0]
80008e8: 605a str r2, [r3, #4]
80008ea: 609a str r2, [r3, #8]
80008ec: 60da str r2, [r3, #12]
80008ee: 611a str r2, [r3, #16]
80008f0: 615a str r2, [r3, #20]
80008f2: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
80008f4: 4b2d ldr r3, [pc, #180] ; (80009ac <MX_TIM2_Init+0xe8>)
80008f6: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
80008fa: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
80008fc: 4b2b ldr r3, [pc, #172] ; (80009ac <MX_TIM2_Init+0xe8>)
80008fe: 2200 movs r2, #0
8000900: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8000902: 4b2a ldr r3, [pc, #168] ; (80009ac <MX_TIM2_Init+0xe8>)
8000904: 2200 movs r2, #0
8000906: 609a str r2, [r3, #8]
htim2.Init.Period = 65535;
8000908: 4b28 ldr r3, [pc, #160] ; (80009ac <MX_TIM2_Init+0xe8>)
800090a: f64f 72ff movw r2, #65535 ; 0xffff
800090e: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000910: 4b26 ldr r3, [pc, #152] ; (80009ac <MX_TIM2_Init+0xe8>)
8000912: 2200 movs r2, #0
8000914: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000916: 4b25 ldr r3, [pc, #148] ; (80009ac <MX_TIM2_Init+0xe8>)
8000918: 2200 movs r2, #0
800091a: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
800091c: 4823 ldr r0, [pc, #140] ; (80009ac <MX_TIM2_Init+0xe8>)
800091e: f001 fada bl 8001ed6 <HAL_TIM_Base_Init>
8000922: 4603 mov r3, r0
8000924: 2b00 cmp r3, #0
8000926: d001 beq.n 800092c <MX_TIM2_Init+0x68>
{
Error_Handler();
8000928: f000 f940 bl 8000bac <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
800092c: f44f 5380 mov.w r3, #4096 ; 0x1000
8000930: 62bb str r3, [r7, #40] ; 0x28
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
8000932: f107 0328 add.w r3, r7, #40 ; 0x28
8000936: 4619 mov r1, r3
8000938: 481c ldr r0, [pc, #112] ; (80009ac <MX_TIM2_Init+0xe8>)
800093a: f001 ff9b bl 8002874 <HAL_TIM_ConfigClockSource>
800093e: 4603 mov r3, r0
8000940: 2b00 cmp r3, #0
8000942: d001 beq.n 8000948 <MX_TIM2_Init+0x84>
{
Error_Handler();
8000944: f000 f932 bl 8000bac <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
8000948: 4818 ldr r0, [pc, #96] ; (80009ac <MX_TIM2_Init+0xe8>)
800094a: f001 fbdc bl 8002106 <HAL_TIM_PWM_Init>
800094e: 4603 mov r3, r0
8000950: 2b00 cmp r3, #0
8000952: d001 beq.n 8000958 <MX_TIM2_Init+0x94>
{
Error_Handler();
8000954: f000 f92a bl 8000bac <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000958: 2300 movs r3, #0
800095a: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800095c: 2300 movs r3, #0
800095e: 627b str r3, [r7, #36] ; 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000960: f107 0320 add.w r3, r7, #32
8000964: 4619 mov r1, r3
8000966: 4811 ldr r0, [pc, #68] ; (80009ac <MX_TIM2_Init+0xe8>)
8000968: f002 fb8e bl 8003088 <HAL_TIMEx_MasterConfigSynchronization>
800096c: 4603 mov r3, r0
800096e: 2b00 cmp r3, #0
8000970: d001 beq.n 8000976 <MX_TIM2_Init+0xb2>
{
Error_Handler();
8000972: f000 f91b bl 8000bac <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000976: 2360 movs r3, #96 ; 0x60
8000978: 607b str r3, [r7, #4]
sConfigOC.Pulse = 10000;
800097a: f242 7310 movw r3, #10000 ; 0x2710
800097e: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000980: 2300 movs r3, #0
8000982: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000984: 2300 movs r3, #0
8000986: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000988: 1d3b adds r3, r7, #4
800098a: 2200 movs r2, #0
800098c: 4619 mov r1, r3
800098e: 4807 ldr r0, [pc, #28] ; (80009ac <MX_TIM2_Init+0xe8>)
8000990: f001 feae bl 80026f0 <HAL_TIM_PWM_ConfigChannel>
8000994: 4603 mov r3, r0
8000996: 2b00 cmp r3, #0
8000998: d001 beq.n 800099e <MX_TIM2_Init+0xda>
{
Error_Handler();
800099a: f000 f907 bl 8000bac <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
800099e: 4803 ldr r0, [pc, #12] ; (80009ac <MX_TIM2_Init+0xe8>)
80009a0: f000 f9b6 bl 8000d10 <HAL_TIM_MspPostInit>
}
80009a4: bf00 nop
80009a6: 3738 adds r7, #56 ; 0x38
80009a8: 46bd mov sp, r7
80009aa: bd80 pop {r7, pc}
80009ac: 200000cc .word 0x200000cc
080009b0 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80009b0: b580 push {r7, lr}
80009b2: b08a sub sp, #40 ; 0x28
80009b4: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80009b6: f107 0314 add.w r3, r7, #20
80009ba: 2200 movs r2, #0
80009bc: 601a str r2, [r3, #0]
80009be: 605a str r2, [r3, #4]
80009c0: 609a str r2, [r3, #8]
80009c2: 60da str r2, [r3, #12]
80009c4: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOH_CLK_ENABLE();
80009c6: 2300 movs r3, #0
80009c8: 613b str r3, [r7, #16]
80009ca: 4b37 ldr r3, [pc, #220] ; (8000aa8 <MX_GPIO_Init+0xf8>)
80009cc: 6b1b ldr r3, [r3, #48] ; 0x30
80009ce: 4a36 ldr r2, [pc, #216] ; (8000aa8 <MX_GPIO_Init+0xf8>)
80009d0: f043 0380 orr.w r3, r3, #128 ; 0x80
80009d4: 6313 str r3, [r2, #48] ; 0x30
80009d6: 4b34 ldr r3, [pc, #208] ; (8000aa8 <MX_GPIO_Init+0xf8>)
80009d8: 6b1b ldr r3, [r3, #48] ; 0x30
80009da: f003 0380 and.w r3, r3, #128 ; 0x80
80009de: 613b str r3, [r7, #16]
80009e0: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
80009e2: 2300 movs r3, #0
80009e4: 60fb str r3, [r7, #12]
80009e6: 4b30 ldr r3, [pc, #192] ; (8000aa8 <MX_GPIO_Init+0xf8>)
80009e8: 6b1b ldr r3, [r3, #48] ; 0x30
80009ea: 4a2f ldr r2, [pc, #188] ; (8000aa8 <MX_GPIO_Init+0xf8>)
80009ec: f043 0304 orr.w r3, r3, #4
80009f0: 6313 str r3, [r2, #48] ; 0x30
80009f2: 4b2d ldr r3, [pc, #180] ; (8000aa8 <MX_GPIO_Init+0xf8>)
80009f4: 6b1b ldr r3, [r3, #48] ; 0x30
80009f6: f003 0304 and.w r3, r3, #4
80009fa: 60fb str r3, [r7, #12]
80009fc: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80009fe: 2300 movs r3, #0
8000a00: 60bb str r3, [r7, #8]
8000a02: 4b29 ldr r3, [pc, #164] ; (8000aa8 <MX_GPIO_Init+0xf8>)
8000a04: 6b1b ldr r3, [r3, #48] ; 0x30
8000a06: 4a28 ldr r2, [pc, #160] ; (8000aa8 <MX_GPIO_Init+0xf8>)
8000a08: f043 0301 orr.w r3, r3, #1
8000a0c: 6313 str r3, [r2, #48] ; 0x30
8000a0e: 4b26 ldr r3, [pc, #152] ; (8000aa8 <MX_GPIO_Init+0xf8>)
8000a10: 6b1b ldr r3, [r3, #48] ; 0x30
8000a12: f003 0301 and.w r3, r3, #1
8000a16: 60bb str r3, [r7, #8]
8000a18: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOE_CLK_ENABLE();
8000a1a: 2300 movs r3, #0
8000a1c: 607b str r3, [r7, #4]
8000a1e: 4b22 ldr r3, [pc, #136] ; (8000aa8 <MX_GPIO_Init+0xf8>)
8000a20: 6b1b ldr r3, [r3, #48] ; 0x30
8000a22: 4a21 ldr r2, [pc, #132] ; (8000aa8 <MX_GPIO_Init+0xf8>)
8000a24: f043 0310 orr.w r3, r3, #16
8000a28: 6313 str r3, [r2, #48] ; 0x30
8000a2a: 4b1f ldr r3, [pc, #124] ; (8000aa8 <MX_GPIO_Init+0xf8>)
8000a2c: 6b1b ldr r3, [r3, #48] ; 0x30
8000a2e: f003 0310 and.w r3, r3, #16
8000a32: 607b str r3, [r7, #4]
8000a34: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1, GPIO_PIN_RESET);
8000a36: 2200 movs r2, #0
8000a38: 2102 movs r1, #2
8000a3a: 481c ldr r0, [pc, #112] ; (8000aac <MX_GPIO_Init+0xfc>)
8000a3c: f000 fd6a bl 8001514 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1|GPIO_PIN_3, GPIO_PIN_RESET);
8000a40: 2200 movs r2, #0
8000a42: 210a movs r1, #10
8000a44: 481a ldr r0, [pc, #104] ; (8000ab0 <MX_GPIO_Init+0x100>)
8000a46: f000 fd65 bl 8001514 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PC1 */
GPIO_InitStruct.Pin = GPIO_PIN_1;
8000a4a: 2302 movs r3, #2
8000a4c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000a4e: 2301 movs r3, #1
8000a50: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a52: 2300 movs r3, #0
8000a54: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a56: 2303 movs r3, #3
8000a58: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000a5a: f107 0314 add.w r3, r7, #20
8000a5e: 4619 mov r1, r3
8000a60: 4812 ldr r0, [pc, #72] ; (8000aac <MX_GPIO_Init+0xfc>)
8000a62: f000 fbbb bl 80011dc <HAL_GPIO_Init>
/*Configure GPIO pin : PA1 */
GPIO_InitStruct.Pin = GPIO_PIN_1;
8000a66: 2302 movs r3, #2
8000a68: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000a6a: 2301 movs r3, #1
8000a6c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a6e: 2300 movs r3, #0
8000a70: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a72: 2300 movs r3, #0
8000a74: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000a76: f107 0314 add.w r3, r7, #20
8000a7a: 4619 mov r1, r3
8000a7c: 480c ldr r0, [pc, #48] ; (8000ab0 <MX_GPIO_Init+0x100>)
8000a7e: f000 fbad bl 80011dc <HAL_GPIO_Init>
/*Configure GPIO pin : PA3 */
GPIO_InitStruct.Pin = GPIO_PIN_3;
8000a82: 2308 movs r3, #8
8000a84: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000a86: 2301 movs r3, #1
8000a88: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a8a: 2300 movs r3, #0
8000a8c: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a8e: 2303 movs r3, #3
8000a90: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000a92: f107 0314 add.w r3, r7, #20
8000a96: 4619 mov r1, r3
8000a98: 4805 ldr r0, [pc, #20] ; (8000ab0 <MX_GPIO_Init+0x100>)
8000a9a: f000 fb9f bl 80011dc <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000a9e: bf00 nop
8000aa0: 3728 adds r7, #40 ; 0x28
8000aa2: 46bd mov sp, r7
8000aa4: bd80 pop {r7, pc}
8000aa6: bf00 nop
8000aa8: 40023800 .word 0x40023800
8000aac: 40020800 .word 0x40020800
8000ab0: 40020000 .word 0x40020000
08000ab4 <PWM_Init>:
/* USER CODE BEGIN 4 */
void PWM_Init(uint8_t prescaler, uint16_t period, uint16_t pwm_value) {
8000ab4: b580 push {r7, lr}
8000ab6: b090 sub sp, #64 ; 0x40
8000ab8: af00 add r7, sp, #0
8000aba: 4603 mov r3, r0
8000abc: 71fb strb r3, [r7, #7]
8000abe: 460b mov r3, r1
8000ac0: 80bb strh r3, [r7, #4]
8000ac2: 4613 mov r3, r2
8000ac4: 807b strh r3, [r7, #2]
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000ac6: f107 0330 add.w r3, r7, #48 ; 0x30
8000aca: 2200 movs r2, #0
8000acc: 601a str r2, [r3, #0]
8000ace: 605a str r2, [r3, #4]
8000ad0: 609a str r2, [r3, #8]
8000ad2: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000ad4: f107 0328 add.w r3, r7, #40 ; 0x28
8000ad8: 2200 movs r2, #0
8000ada: 601a str r2, [r3, #0]
8000adc: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8000ade: f107 030c add.w r3, r7, #12
8000ae2: 2200 movs r2, #0
8000ae4: 601a str r2, [r3, #0]
8000ae6: 605a str r2, [r3, #4]
8000ae8: 609a str r2, [r3, #8]
8000aea: 60da str r2, [r3, #12]
8000aec: 611a str r2, [r3, #16]
8000aee: 615a str r2, [r3, #20]
8000af0: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8000af2: 4b2d ldr r3, [pc, #180] ; (8000ba8 <PWM_Init+0xf4>)
8000af4: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
8000af8: 601a str r2, [r3, #0]
htim2.Init.Prescaler = prescaler;
8000afa: 79fb ldrb r3, [r7, #7]
8000afc: 4a2a ldr r2, [pc, #168] ; (8000ba8 <PWM_Init+0xf4>)
8000afe: 6053 str r3, [r2, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8000b00: 4b29 ldr r3, [pc, #164] ; (8000ba8 <PWM_Init+0xf4>)
8000b02: 2200 movs r2, #0
8000b04: 609a str r2, [r3, #8]
htim2.Init.Period = period;
8000b06: 88bb ldrh r3, [r7, #4]
8000b08: 4a27 ldr r2, [pc, #156] ; (8000ba8 <PWM_Init+0xf4>)
8000b0a: 60d3 str r3, [r2, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000b0c: 4b26 ldr r3, [pc, #152] ; (8000ba8 <PWM_Init+0xf4>)
8000b0e: 2200 movs r2, #0
8000b10: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000b12: 4b25 ldr r3, [pc, #148] ; (8000ba8 <PWM_Init+0xf4>)
8000b14: 2200 movs r2, #0
8000b16: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
8000b18: 4823 ldr r0, [pc, #140] ; (8000ba8 <PWM_Init+0xf4>)
8000b1a: f001 f9dc bl 8001ed6 <HAL_TIM_Base_Init>
8000b1e: 4603 mov r3, r0
8000b20: 2b00 cmp r3, #0
8000b22: d001 beq.n 8000b28 <PWM_Init+0x74>
{
Error_Handler();
8000b24: f000 f842 bl 8000bac <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000b28: f44f 5380 mov.w r3, #4096 ; 0x1000
8000b2c: 633b str r3, [r7, #48] ; 0x30
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
8000b2e: f107 0330 add.w r3, r7, #48 ; 0x30
8000b32: 4619 mov r1, r3
8000b34: 481c ldr r0, [pc, #112] ; (8000ba8 <PWM_Init+0xf4>)
8000b36: f001 fe9d bl 8002874 <HAL_TIM_ConfigClockSource>
8000b3a: 4603 mov r3, r0
8000b3c: 2b00 cmp r3, #0
8000b3e: d001 beq.n 8000b44 <PWM_Init+0x90>
{
Error_Handler();
8000b40: f000 f834 bl 8000bac <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
8000b44: 4818 ldr r0, [pc, #96] ; (8000ba8 <PWM_Init+0xf4>)
8000b46: f001 fade bl 8002106 <HAL_TIM_PWM_Init>
8000b4a: 4603 mov r3, r0
8000b4c: 2b00 cmp r3, #0
8000b4e: d001 beq.n 8000b54 <PWM_Init+0xa0>
{
Error_Handler();
8000b50: f000 f82c bl 8000bac <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000b54: 2300 movs r3, #0
8000b56: 62bb str r3, [r7, #40] ; 0x28
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000b58: 2300 movs r3, #0
8000b5a: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000b5c: f107 0328 add.w r3, r7, #40 ; 0x28
8000b60: 4619 mov r1, r3
8000b62: 4811 ldr r0, [pc, #68] ; (8000ba8 <PWM_Init+0xf4>)
8000b64: f002 fa90 bl 8003088 <HAL_TIMEx_MasterConfigSynchronization>
8000b68: 4603 mov r3, r0
8000b6a: 2b00 cmp r3, #0
8000b6c: d001 beq.n 8000b72 <PWM_Init+0xbe>
{
Error_Handler();
8000b6e: f000 f81d bl 8000bac <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000b72: 2360 movs r3, #96 ; 0x60
8000b74: 60fb str r3, [r7, #12]
sConfigOC.Pulse = pwm_value;
8000b76: 887b ldrh r3, [r7, #2]
8000b78: 613b str r3, [r7, #16]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000b7a: 2300 movs r3, #0
8000b7c: 617b str r3, [r7, #20]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000b7e: 2300 movs r3, #0
8000b80: 61fb str r3, [r7, #28]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000b82: f107 030c add.w r3, r7, #12
8000b86: 2200 movs r2, #0
8000b88: 4619 mov r1, r3
8000b8a: 4807 ldr r0, [pc, #28] ; (8000ba8 <PWM_Init+0xf4>)
8000b8c: f001 fdb0 bl 80026f0 <HAL_TIM_PWM_ConfigChannel>
8000b90: 4603 mov r3, r0
8000b92: 2b00 cmp r3, #0
8000b94: d001 beq.n 8000b9a <PWM_Init+0xe6>
{
Error_Handler();
8000b96: f000 f809 bl 8000bac <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
//TIM2->CCR1 = pwmValue;
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
8000b9a: 4803 ldr r0, [pc, #12] ; (8000ba8 <PWM_Init+0xf4>)
8000b9c: f000 f8b8 bl 8000d10 <HAL_TIM_MspPostInit>
}
8000ba0: bf00 nop
8000ba2: 3740 adds r7, #64 ; 0x40
8000ba4: 46bd mov sp, r7
8000ba6: bd80 pop {r7, pc}
8000ba8: 200000cc .word 0x200000cc
08000bac <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000bac: b480 push {r7}
8000bae: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000bb0: b672 cpsid i
}
8000bb2: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000bb4: e7fe b.n 8000bb4 <Error_Handler+0x8>
...
08000bb8 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000bb8: b480 push {r7}
8000bba: b083 sub sp, #12
8000bbc: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000bbe: 2300 movs r3, #0
8000bc0: 607b str r3, [r7, #4]
8000bc2: 4b10 ldr r3, [pc, #64] ; (8000c04 <HAL_MspInit+0x4c>)
8000bc4: 6c5b ldr r3, [r3, #68] ; 0x44
8000bc6: 4a0f ldr r2, [pc, #60] ; (8000c04 <HAL_MspInit+0x4c>)
8000bc8: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000bcc: 6453 str r3, [r2, #68] ; 0x44
8000bce: 4b0d ldr r3, [pc, #52] ; (8000c04 <HAL_MspInit+0x4c>)
8000bd0: 6c5b ldr r3, [r3, #68] ; 0x44
8000bd2: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000bd6: 607b str r3, [r7, #4]
8000bd8: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000bda: 2300 movs r3, #0
8000bdc: 603b str r3, [r7, #0]
8000bde: 4b09 ldr r3, [pc, #36] ; (8000c04 <HAL_MspInit+0x4c>)
8000be0: 6c1b ldr r3, [r3, #64] ; 0x40
8000be2: 4a08 ldr r2, [pc, #32] ; (8000c04 <HAL_MspInit+0x4c>)
8000be4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000be8: 6413 str r3, [r2, #64] ; 0x40
8000bea: 4b06 ldr r3, [pc, #24] ; (8000c04 <HAL_MspInit+0x4c>)
8000bec: 6c1b ldr r3, [r3, #64] ; 0x40
8000bee: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000bf2: 603b str r3, [r7, #0]
8000bf4: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000bf6: bf00 nop
8000bf8: 370c adds r7, #12
8000bfa: 46bd mov sp, r7
8000bfc: f85d 7b04 ldr.w r7, [sp], #4
8000c00: 4770 bx lr
8000c02: bf00 nop
8000c04: 40023800 .word 0x40023800
08000c08 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8000c08: b580 push {r7, lr}
8000c0a: b08a sub sp, #40 ; 0x28
8000c0c: af00 add r7, sp, #0
8000c0e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000c10: f107 0314 add.w r3, r7, #20
8000c14: 2200 movs r2, #0
8000c16: 601a str r2, [r3, #0]
8000c18: 605a str r2, [r3, #4]
8000c1a: 609a str r2, [r3, #8]
8000c1c: 60da str r2, [r3, #12]
8000c1e: 611a str r2, [r3, #16]
if(hspi->Instance==SPI1)
8000c20: 687b ldr r3, [r7, #4]
8000c22: 681b ldr r3, [r3, #0]
8000c24: 4a19 ldr r2, [pc, #100] ; (8000c8c <HAL_SPI_MspInit+0x84>)
8000c26: 4293 cmp r3, r2
8000c28: d12b bne.n 8000c82 <HAL_SPI_MspInit+0x7a>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
8000c2a: 2300 movs r3, #0
8000c2c: 613b str r3, [r7, #16]
8000c2e: 4b18 ldr r3, [pc, #96] ; (8000c90 <HAL_SPI_MspInit+0x88>)
8000c30: 6c5b ldr r3, [r3, #68] ; 0x44
8000c32: 4a17 ldr r2, [pc, #92] ; (8000c90 <HAL_SPI_MspInit+0x88>)
8000c34: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8000c38: 6453 str r3, [r2, #68] ; 0x44
8000c3a: 4b15 ldr r3, [pc, #84] ; (8000c90 <HAL_SPI_MspInit+0x88>)
8000c3c: 6c5b ldr r3, [r3, #68] ; 0x44
8000c3e: f403 5380 and.w r3, r3, #4096 ; 0x1000
8000c42: 613b str r3, [r7, #16]
8000c44: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000c46: 2300 movs r3, #0
8000c48: 60fb str r3, [r7, #12]
8000c4a: 4b11 ldr r3, [pc, #68] ; (8000c90 <HAL_SPI_MspInit+0x88>)
8000c4c: 6b1b ldr r3, [r3, #48] ; 0x30
8000c4e: 4a10 ldr r2, [pc, #64] ; (8000c90 <HAL_SPI_MspInit+0x88>)
8000c50: f043 0301 orr.w r3, r3, #1
8000c54: 6313 str r3, [r2, #48] ; 0x30
8000c56: 4b0e ldr r3, [pc, #56] ; (8000c90 <HAL_SPI_MspInit+0x88>)
8000c58: 6b1b ldr r3, [r3, #48] ; 0x30
8000c5a: f003 0301 and.w r3, r3, #1
8000c5e: 60fb str r3, [r7, #12]
8000c60: 68fb ldr r3, [r7, #12]
PA4 ------> SPI1_NSS
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
8000c62: 23f0 movs r3, #240 ; 0xf0
8000c64: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c66: 2302 movs r3, #2
8000c68: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c6a: 2300 movs r3, #0
8000c6c: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c6e: 2303 movs r3, #3
8000c70: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8000c72: 2305 movs r3, #5
8000c74: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000c76: f107 0314 add.w r3, r7, #20
8000c7a: 4619 mov r1, r3
8000c7c: 4805 ldr r0, [pc, #20] ; (8000c94 <HAL_SPI_MspInit+0x8c>)
8000c7e: f000 faad bl 80011dc <HAL_GPIO_Init>
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
}
8000c82: bf00 nop
8000c84: 3728 adds r7, #40 ; 0x28
8000c86: 46bd mov sp, r7
8000c88: bd80 pop {r7, pc}
8000c8a: bf00 nop
8000c8c: 40013000 .word 0x40013000
8000c90: 40023800 .word 0x40023800
8000c94: 40020000 .word 0x40020000
08000c98 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8000c98: b580 push {r7, lr}
8000c9a: b084 sub sp, #16
8000c9c: af00 add r7, sp, #0
8000c9e: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
8000ca0: 687b ldr r3, [r7, #4]
8000ca2: 681b ldr r3, [r3, #0]
8000ca4: 4a18 ldr r2, [pc, #96] ; (8000d08 <HAL_TIM_Base_MspInit+0x70>)
8000ca6: 4293 cmp r3, r2
8000ca8: d116 bne.n 8000cd8 <HAL_TIM_Base_MspInit+0x40>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
8000caa: 2300 movs r3, #0
8000cac: 60fb str r3, [r7, #12]
8000cae: 4b17 ldr r3, [pc, #92] ; (8000d0c <HAL_TIM_Base_MspInit+0x74>)
8000cb0: 6c5b ldr r3, [r3, #68] ; 0x44
8000cb2: 4a16 ldr r2, [pc, #88] ; (8000d0c <HAL_TIM_Base_MspInit+0x74>)
8000cb4: f043 0301 orr.w r3, r3, #1
8000cb8: 6453 str r3, [r2, #68] ; 0x44
8000cba: 4b14 ldr r3, [pc, #80] ; (8000d0c <HAL_TIM_Base_MspInit+0x74>)
8000cbc: 6c5b ldr r3, [r3, #68] ; 0x44
8000cbe: f003 0301 and.w r3, r3, #1
8000cc2: 60fb str r3, [r7, #12]
8000cc4: 68fb ldr r3, [r7, #12]
/* TIM1 interrupt Init */
HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 0, 0);
8000cc6: 2200 movs r2, #0
8000cc8: 2100 movs r1, #0
8000cca: 2019 movs r0, #25
8000ccc: f000 fa4f bl 800116e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
8000cd0: 2019 movs r0, #25
8000cd2: f000 fa68 bl 80011a6 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM2_MspInit 1 */
/* USER CODE END TIM2_MspInit 1 */
}
}
8000cd6: e012 b.n 8000cfe <HAL_TIM_Base_MspInit+0x66>
else if(htim_base->Instance==TIM2)
8000cd8: 687b ldr r3, [r7, #4]
8000cda: 681b ldr r3, [r3, #0]
8000cdc: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8000ce0: d10d bne.n 8000cfe <HAL_TIM_Base_MspInit+0x66>
__HAL_RCC_TIM2_CLK_ENABLE();
8000ce2: 2300 movs r3, #0
8000ce4: 60bb str r3, [r7, #8]
8000ce6: 4b09 ldr r3, [pc, #36] ; (8000d0c <HAL_TIM_Base_MspInit+0x74>)
8000ce8: 6c1b ldr r3, [r3, #64] ; 0x40
8000cea: 4a08 ldr r2, [pc, #32] ; (8000d0c <HAL_TIM_Base_MspInit+0x74>)
8000cec: f043 0301 orr.w r3, r3, #1
8000cf0: 6413 str r3, [r2, #64] ; 0x40
8000cf2: 4b06 ldr r3, [pc, #24] ; (8000d0c <HAL_TIM_Base_MspInit+0x74>)
8000cf4: 6c1b ldr r3, [r3, #64] ; 0x40
8000cf6: f003 0301 and.w r3, r3, #1
8000cfa: 60bb str r3, [r7, #8]
8000cfc: 68bb ldr r3, [r7, #8]
}
8000cfe: bf00 nop
8000d00: 3710 adds r7, #16
8000d02: 46bd mov sp, r7
8000d04: bd80 pop {r7, pc}
8000d06: bf00 nop
8000d08: 40010000 .word 0x40010000
8000d0c: 40023800 .word 0x40023800
08000d10 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8000d10: b580 push {r7, lr}
8000d12: b08a sub sp, #40 ; 0x28
8000d14: af00 add r7, sp, #0
8000d16: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000d18: f107 0314 add.w r3, r7, #20
8000d1c: 2200 movs r2, #0
8000d1e: 601a str r2, [r3, #0]
8000d20: 605a str r2, [r3, #4]
8000d22: 609a str r2, [r3, #8]
8000d24: 60da str r2, [r3, #12]
8000d26: 611a str r2, [r3, #16]
if(htim->Instance==TIM1)
8000d28: 687b ldr r3, [r7, #4]
8000d2a: 681b ldr r3, [r3, #0]
8000d2c: 4a24 ldr r2, [pc, #144] ; (8000dc0 <HAL_TIM_MspPostInit+0xb0>)
8000d2e: 4293 cmp r3, r2
8000d30: d11f bne.n 8000d72 <HAL_TIM_MspPostInit+0x62>
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOE_CLK_ENABLE();
8000d32: 2300 movs r3, #0
8000d34: 613b str r3, [r7, #16]
8000d36: 4b23 ldr r3, [pc, #140] ; (8000dc4 <HAL_TIM_MspPostInit+0xb4>)
8000d38: 6b1b ldr r3, [r3, #48] ; 0x30
8000d3a: 4a22 ldr r2, [pc, #136] ; (8000dc4 <HAL_TIM_MspPostInit+0xb4>)
8000d3c: f043 0310 orr.w r3, r3, #16
8000d40: 6313 str r3, [r2, #48] ; 0x30
8000d42: 4b20 ldr r3, [pc, #128] ; (8000dc4 <HAL_TIM_MspPostInit+0xb4>)
8000d44: 6b1b ldr r3, [r3, #48] ; 0x30
8000d46: f003 0310 and.w r3, r3, #16
8000d4a: 613b str r3, [r7, #16]
8000d4c: 693b ldr r3, [r7, #16]
/**TIM1 GPIO Configuration
PE9 ------> TIM1_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
8000d4e: f44f 7300 mov.w r3, #512 ; 0x200
8000d52: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000d54: 2302 movs r3, #2
8000d56: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d58: 2300 movs r3, #0
8000d5a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000d5c: 2300 movs r3, #0
8000d5e: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
8000d60: 2301 movs r3, #1
8000d62: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000d64: f107 0314 add.w r3, r7, #20
8000d68: 4619 mov r1, r3
8000d6a: 4817 ldr r0, [pc, #92] ; (8000dc8 <HAL_TIM_MspPostInit+0xb8>)
8000d6c: f000 fa36 bl 80011dc <HAL_GPIO_Init>
/* USER CODE BEGIN TIM2_MspPostInit 1 */
/* USER CODE END TIM2_MspPostInit 1 */
}
}
8000d70: e022 b.n 8000db8 <HAL_TIM_MspPostInit+0xa8>
else if(htim->Instance==TIM2)
8000d72: 687b ldr r3, [r7, #4]
8000d74: 681b ldr r3, [r3, #0]
8000d76: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8000d7a: d11d bne.n 8000db8 <HAL_TIM_MspPostInit+0xa8>
__HAL_RCC_GPIOA_CLK_ENABLE();
8000d7c: 2300 movs r3, #0
8000d7e: 60fb str r3, [r7, #12]
8000d80: 4b10 ldr r3, [pc, #64] ; (8000dc4 <HAL_TIM_MspPostInit+0xb4>)
8000d82: 6b1b ldr r3, [r3, #48] ; 0x30
8000d84: 4a0f ldr r2, [pc, #60] ; (8000dc4 <HAL_TIM_MspPostInit+0xb4>)
8000d86: f043 0301 orr.w r3, r3, #1
8000d8a: 6313 str r3, [r2, #48] ; 0x30
8000d8c: 4b0d ldr r3, [pc, #52] ; (8000dc4 <HAL_TIM_MspPostInit+0xb4>)
8000d8e: 6b1b ldr r3, [r3, #48] ; 0x30
8000d90: f003 0301 and.w r3, r3, #1
8000d94: 60fb str r3, [r7, #12]
8000d96: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_0;
8000d98: 2301 movs r3, #1
8000d9a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000d9c: 2302 movs r3, #2
8000d9e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000da0: 2300 movs r3, #0
8000da2: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000da4: 2300 movs r3, #0
8000da6: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8000da8: 2301 movs r3, #1
8000daa: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000dac: f107 0314 add.w r3, r7, #20
8000db0: 4619 mov r1, r3
8000db2: 4806 ldr r0, [pc, #24] ; (8000dcc <HAL_TIM_MspPostInit+0xbc>)
8000db4: f000 fa12 bl 80011dc <HAL_GPIO_Init>
}
8000db8: bf00 nop
8000dba: 3728 adds r7, #40 ; 0x28
8000dbc: 46bd mov sp, r7
8000dbe: bd80 pop {r7, pc}
8000dc0: 40010000 .word 0x40010000
8000dc4: 40023800 .word 0x40023800
8000dc8: 40021000 .word 0x40021000
8000dcc: 40020000 .word 0x40020000
08000dd0 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000dd0: b480 push {r7}
8000dd2: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000dd4: e7fe b.n 8000dd4 <NMI_Handler+0x4>
08000dd6 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000dd6: b480 push {r7}
8000dd8: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000dda: e7fe b.n 8000dda <HardFault_Handler+0x4>
08000ddc <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000ddc: b480 push {r7}
8000dde: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000de0: e7fe b.n 8000de0 <MemManage_Handler+0x4>
08000de2 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000de2: b480 push {r7}
8000de4: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000de6: e7fe b.n 8000de6 <BusFault_Handler+0x4>
08000de8 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000de8: b480 push {r7}
8000dea: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000dec: e7fe b.n 8000dec <UsageFault_Handler+0x4>
08000dee <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000dee: b480 push {r7}
8000df0: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000df2: bf00 nop
8000df4: 46bd mov sp, r7
8000df6: f85d 7b04 ldr.w r7, [sp], #4
8000dfa: 4770 bx lr
08000dfc <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000dfc: b480 push {r7}
8000dfe: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000e00: bf00 nop
8000e02: 46bd mov sp, r7
8000e04: f85d 7b04 ldr.w r7, [sp], #4
8000e08: 4770 bx lr
08000e0a <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000e0a: b480 push {r7}
8000e0c: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000e0e: bf00 nop
8000e10: 46bd mov sp, r7
8000e12: f85d 7b04 ldr.w r7, [sp], #4
8000e16: 4770 bx lr
08000e18 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000e18: b580 push {r7, lr}
8000e1a: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000e1c: f000 f8ac bl 8000f78 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000e20: bf00 nop
8000e22: bd80 pop {r7, pc}
08000e24 <TIM1_UP_TIM10_IRQHandler>:
/**
* @brief This function handles TIM1 update interrupt and TIM10 global interrupt.
*/
void TIM1_UP_TIM10_IRQHandler(void)
{
8000e24: b580 push {r7, lr}
8000e26: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */
// if ((htim2.Instance->CCMR1 & TIM_CCMR1_OC1M_Msk) == TIM_CCMR1_OC1M_1 ||
// (htim2.Instance->CCMR1 & TIM_CCMR1_OC1M_Msk) == TIM_CCMR1_OC1M_2) {
HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_1);
8000e28: 2102 movs r1, #2
8000e2a: 4809 ldr r0, [pc, #36] ; (8000e50 <TIM1_UP_TIM10_IRQHandler+0x2c>)
8000e2c: f000 fb8b bl 8001546 <HAL_GPIO_TogglePin>
if (channel == 1) {
8000e30: 4b08 ldr r3, [pc, #32] ; (8000e54 <TIM1_UP_TIM10_IRQHandler+0x30>)
8000e32: 681b ldr r3, [r3, #0]
8000e34: 2b01 cmp r3, #1
8000e36: d103 bne.n 8000e40 <TIM1_UP_TIM10_IRQHandler+0x1c>
channel = 2;
8000e38: 4b06 ldr r3, [pc, #24] ; (8000e54 <TIM1_UP_TIM10_IRQHandler+0x30>)
8000e3a: 2202 movs r2, #2
8000e3c: 601a str r2, [r3, #0]
8000e3e: e002 b.n 8000e46 <TIM1_UP_TIM10_IRQHandler+0x22>
} else {
channel = 1;
8000e40: 4b04 ldr r3, [pc, #16] ; (8000e54 <TIM1_UP_TIM10_IRQHandler+0x30>)
8000e42: 2201 movs r2, #1
8000e44: 601a str r2, [r3, #0]
}
//HAL_TIM_PWM_Stop(&htim2, TIM_CHANNEL_1);
//}
//HAL_Delay(1000);
/* USER CODE END TIM1_UP_TIM10_IRQn 0 */
HAL_TIM_IRQHandler(&htim1);
8000e46: 4804 ldr r0, [pc, #16] ; (8000e58 <TIM1_UP_TIM10_IRQHandler+0x34>)
8000e48: f001 faee bl 8002428 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */
/* USER CODE END TIM1_UP_TIM10_IRQn 1 */
}
8000e4c: bf00 nop
8000e4e: bd80 pop {r7, pc}
8000e50: 40020800 .word 0x40020800
8000e54: 20000000 .word 0x20000000
8000e58: 20000084 .word 0x20000084
08000e5c <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
8000e5c: b480 push {r7}
8000e5e: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000e60: 4b06 ldr r3, [pc, #24] ; (8000e7c <SystemInit+0x20>)
8000e62: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8000e66: 4a05 ldr r2, [pc, #20] ; (8000e7c <SystemInit+0x20>)
8000e68: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8000e6c: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000e70: bf00 nop
8000e72: 46bd mov sp, r7
8000e74: f85d 7b04 ldr.w r7, [sp], #4
8000e78: 4770 bx lr
8000e7a: bf00 nop
8000e7c: e000ed00 .word 0xe000ed00
08000e80 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8000e80: f8df d034 ldr.w sp, [pc, #52] ; 8000eb8 <LoopFillZerobss+0x12>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000e84: 480d ldr r0, [pc, #52] ; (8000ebc <LoopFillZerobss+0x16>)
ldr r1, =_edata
8000e86: 490e ldr r1, [pc, #56] ; (8000ec0 <LoopFillZerobss+0x1a>)
ldr r2, =_sidata
8000e88: 4a0e ldr r2, [pc, #56] ; (8000ec4 <LoopFillZerobss+0x1e>)
movs r3, #0
8000e8a: 2300 movs r3, #0
b LoopCopyDataInit
8000e8c: e002 b.n 8000e94 <LoopCopyDataInit>
08000e8e <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000e8e: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000e90: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000e92: 3304 adds r3, #4
08000e94 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000e94: 18c4 adds r4, r0, r3
cmp r4, r1
8000e96: 428c cmp r4, r1
bcc CopyDataInit
8000e98: d3f9 bcc.n 8000e8e <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000e9a: 4a0b ldr r2, [pc, #44] ; (8000ec8 <LoopFillZerobss+0x22>)
ldr r4, =_ebss
8000e9c: 4c0b ldr r4, [pc, #44] ; (8000ecc <LoopFillZerobss+0x26>)
movs r3, #0
8000e9e: 2300 movs r3, #0
b LoopFillZerobss
8000ea0: e001 b.n 8000ea6 <LoopFillZerobss>
08000ea2 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000ea2: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000ea4: 3204 adds r2, #4
08000ea6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000ea6: 42a2 cmp r2, r4
bcc FillZerobss
8000ea8: d3fb bcc.n 8000ea2 <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
8000eaa: f7ff ffd7 bl 8000e5c <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000eae: f002 f9d5 bl 800325c <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000eb2: f7ff fb07 bl 80004c4 <main>
bx lr
8000eb6: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8000eb8: 20020000 .word 0x20020000
ldr r0, =_sdata
8000ebc: 20000000 .word 0x20000000
ldr r1, =_edata
8000ec0: 20000010 .word 0x20000010
ldr r2, =_sidata
8000ec4: 080032dc .word 0x080032dc
ldr r2, =_sbss
8000ec8: 20000010 .word 0x20000010
ldr r4, =_ebss
8000ecc: 2000011c .word 0x2000011c
08000ed0 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000ed0: e7fe b.n 8000ed0 <ADC_IRQHandler>
...
08000ed4 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000ed4: b580 push {r7, lr}
8000ed6: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8000ed8: 4b0e ldr r3, [pc, #56] ; (8000f14 <HAL_Init+0x40>)
8000eda: 681b ldr r3, [r3, #0]
8000edc: 4a0d ldr r2, [pc, #52] ; (8000f14 <HAL_Init+0x40>)
8000ede: f443 7300 orr.w r3, r3, #512 ; 0x200
8000ee2: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8000ee4: 4b0b ldr r3, [pc, #44] ; (8000f14 <HAL_Init+0x40>)
8000ee6: 681b ldr r3, [r3, #0]
8000ee8: 4a0a ldr r2, [pc, #40] ; (8000f14 <HAL_Init+0x40>)
8000eea: f443 6380 orr.w r3, r3, #1024 ; 0x400
8000eee: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000ef0: 4b08 ldr r3, [pc, #32] ; (8000f14 <HAL_Init+0x40>)
8000ef2: 681b ldr r3, [r3, #0]
8000ef4: 4a07 ldr r2, [pc, #28] ; (8000f14 <HAL_Init+0x40>)
8000ef6: f443 7380 orr.w r3, r3, #256 ; 0x100
8000efa: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000efc: 2003 movs r0, #3
8000efe: f000 f92b bl 8001158 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000f02: 200f movs r0, #15
8000f04: f000 f808 bl 8000f18 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000f08: f7ff fe56 bl 8000bb8 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000f0c: 2300 movs r3, #0
}
8000f0e: 4618 mov r0, r3
8000f10: bd80 pop {r7, pc}
8000f12: bf00 nop
8000f14: 40023c00 .word 0x40023c00
08000f18 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000f18: b580 push {r7, lr}
8000f1a: b082 sub sp, #8
8000f1c: af00 add r7, sp, #0
8000f1e: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000f20: 4b12 ldr r3, [pc, #72] ; (8000f6c <HAL_InitTick+0x54>)
8000f22: 681a ldr r2, [r3, #0]
8000f24: 4b12 ldr r3, [pc, #72] ; (8000f70 <HAL_InitTick+0x58>)
8000f26: 781b ldrb r3, [r3, #0]
8000f28: 4619 mov r1, r3
8000f2a: f44f 737a mov.w r3, #1000 ; 0x3e8
8000f2e: fbb3 f3f1 udiv r3, r3, r1
8000f32: fbb2 f3f3 udiv r3, r2, r3
8000f36: 4618 mov r0, r3
8000f38: f000 f943 bl 80011c2 <HAL_SYSTICK_Config>
8000f3c: 4603 mov r3, r0
8000f3e: 2b00 cmp r3, #0
8000f40: d001 beq.n 8000f46 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000f42: 2301 movs r3, #1
8000f44: e00e b.n 8000f64 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000f46: 687b ldr r3, [r7, #4]
8000f48: 2b0f cmp r3, #15
8000f4a: d80a bhi.n 8000f62 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000f4c: 2200 movs r2, #0
8000f4e: 6879 ldr r1, [r7, #4]
8000f50: f04f 30ff mov.w r0, #4294967295
8000f54: f000 f90b bl 800116e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000f58: 4a06 ldr r2, [pc, #24] ; (8000f74 <HAL_InitTick+0x5c>)
8000f5a: 687b ldr r3, [r7, #4]
8000f5c: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000f5e: 2300 movs r3, #0
8000f60: e000 b.n 8000f64 <HAL_InitTick+0x4c>
return HAL_ERROR;
8000f62: 2301 movs r3, #1
}
8000f64: 4618 mov r0, r3
8000f66: 3708 adds r7, #8
8000f68: 46bd mov sp, r7
8000f6a: bd80 pop {r7, pc}
8000f6c: 20000004 .word 0x20000004
8000f70: 2000000c .word 0x2000000c
8000f74: 20000008 .word 0x20000008
08000f78 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000f78: b480 push {r7}
8000f7a: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000f7c: 4b06 ldr r3, [pc, #24] ; (8000f98 <HAL_IncTick+0x20>)
8000f7e: 781b ldrb r3, [r3, #0]
8000f80: 461a mov r2, r3
8000f82: 4b06 ldr r3, [pc, #24] ; (8000f9c <HAL_IncTick+0x24>)
8000f84: 681b ldr r3, [r3, #0]
8000f86: 4413 add r3, r2
8000f88: 4a04 ldr r2, [pc, #16] ; (8000f9c <HAL_IncTick+0x24>)
8000f8a: 6013 str r3, [r2, #0]
}
8000f8c: bf00 nop
8000f8e: 46bd mov sp, r7
8000f90: f85d 7b04 ldr.w r7, [sp], #4
8000f94: 4770 bx lr
8000f96: bf00 nop
8000f98: 2000000c .word 0x2000000c
8000f9c: 20000118 .word 0x20000118
08000fa0 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000fa0: b480 push {r7}
8000fa2: af00 add r7, sp, #0
return uwTick;
8000fa4: 4b03 ldr r3, [pc, #12] ; (8000fb4 <HAL_GetTick+0x14>)
8000fa6: 681b ldr r3, [r3, #0]
}
8000fa8: 4618 mov r0, r3
8000faa: 46bd mov sp, r7
8000fac: f85d 7b04 ldr.w r7, [sp], #4
8000fb0: 4770 bx lr
8000fb2: bf00 nop
8000fb4: 20000118 .word 0x20000118
08000fb8 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000fb8: b480 push {r7}
8000fba: b085 sub sp, #20
8000fbc: af00 add r7, sp, #0
8000fbe: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000fc0: 687b ldr r3, [r7, #4]
8000fc2: f003 0307 and.w r3, r3, #7
8000fc6: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000fc8: 4b0c ldr r3, [pc, #48] ; (8000ffc <__NVIC_SetPriorityGrouping+0x44>)
8000fca: 68db ldr r3, [r3, #12]
8000fcc: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000fce: 68ba ldr r2, [r7, #8]
8000fd0: f64f 03ff movw r3, #63743 ; 0xf8ff
8000fd4: 4013 ands r3, r2
8000fd6: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000fd8: 68fb ldr r3, [r7, #12]
8000fda: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000fdc: 68bb ldr r3, [r7, #8]
8000fde: 4313 orrs r3, r2
reg_value = (reg_value |
8000fe0: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8000fe4: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000fe8: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000fea: 4a04 ldr r2, [pc, #16] ; (8000ffc <__NVIC_SetPriorityGrouping+0x44>)
8000fec: 68bb ldr r3, [r7, #8]
8000fee: 60d3 str r3, [r2, #12]
}
8000ff0: bf00 nop
8000ff2: 3714 adds r7, #20
8000ff4: 46bd mov sp, r7
8000ff6: f85d 7b04 ldr.w r7, [sp], #4
8000ffa: 4770 bx lr
8000ffc: e000ed00 .word 0xe000ed00
08001000 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8001000: b480 push {r7}
8001002: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001004: 4b04 ldr r3, [pc, #16] ; (8001018 <__NVIC_GetPriorityGrouping+0x18>)
8001006: 68db ldr r3, [r3, #12]
8001008: 0a1b lsrs r3, r3, #8
800100a: f003 0307 and.w r3, r3, #7
}
800100e: 4618 mov r0, r3
8001010: 46bd mov sp, r7
8001012: f85d 7b04 ldr.w r7, [sp], #4
8001016: 4770 bx lr
8001018: e000ed00 .word 0xe000ed00
0800101c <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
800101c: b480 push {r7}
800101e: b083 sub sp, #12
8001020: af00 add r7, sp, #0
8001022: 4603 mov r3, r0
8001024: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001026: f997 3007 ldrsb.w r3, [r7, #7]
800102a: 2b00 cmp r3, #0
800102c: db0b blt.n 8001046 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800102e: 79fb ldrb r3, [r7, #7]
8001030: f003 021f and.w r2, r3, #31
8001034: 4907 ldr r1, [pc, #28] ; (8001054 <__NVIC_EnableIRQ+0x38>)
8001036: f997 3007 ldrsb.w r3, [r7, #7]
800103a: 095b lsrs r3, r3, #5
800103c: 2001 movs r0, #1
800103e: fa00 f202 lsl.w r2, r0, r2
8001042: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8001046: bf00 nop
8001048: 370c adds r7, #12
800104a: 46bd mov sp, r7
800104c: f85d 7b04 ldr.w r7, [sp], #4
8001050: 4770 bx lr
8001052: bf00 nop
8001054: e000e100 .word 0xe000e100
08001058 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001058: b480 push {r7}
800105a: b083 sub sp, #12
800105c: af00 add r7, sp, #0
800105e: 4603 mov r3, r0
8001060: 6039 str r1, [r7, #0]
8001062: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001064: f997 3007 ldrsb.w r3, [r7, #7]
8001068: 2b00 cmp r3, #0
800106a: db0a blt.n 8001082 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800106c: 683b ldr r3, [r7, #0]
800106e: b2da uxtb r2, r3
8001070: 490c ldr r1, [pc, #48] ; (80010a4 <__NVIC_SetPriority+0x4c>)
8001072: f997 3007 ldrsb.w r3, [r7, #7]
8001076: 0112 lsls r2, r2, #4
8001078: b2d2 uxtb r2, r2
800107a: 440b add r3, r1
800107c: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001080: e00a b.n 8001098 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001082: 683b ldr r3, [r7, #0]
8001084: b2da uxtb r2, r3
8001086: 4908 ldr r1, [pc, #32] ; (80010a8 <__NVIC_SetPriority+0x50>)
8001088: 79fb ldrb r3, [r7, #7]
800108a: f003 030f and.w r3, r3, #15
800108e: 3b04 subs r3, #4
8001090: 0112 lsls r2, r2, #4
8001092: b2d2 uxtb r2, r2
8001094: 440b add r3, r1
8001096: 761a strb r2, [r3, #24]
}
8001098: bf00 nop
800109a: 370c adds r7, #12
800109c: 46bd mov sp, r7
800109e: f85d 7b04 ldr.w r7, [sp], #4
80010a2: 4770 bx lr
80010a4: e000e100 .word 0xe000e100
80010a8: e000ed00 .word 0xe000ed00
080010ac <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80010ac: b480 push {r7}
80010ae: b089 sub sp, #36 ; 0x24
80010b0: af00 add r7, sp, #0
80010b2: 60f8 str r0, [r7, #12]
80010b4: 60b9 str r1, [r7, #8]
80010b6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80010b8: 68fb ldr r3, [r7, #12]
80010ba: f003 0307 and.w r3, r3, #7
80010be: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80010c0: 69fb ldr r3, [r7, #28]
80010c2: f1c3 0307 rsb r3, r3, #7
80010c6: 2b04 cmp r3, #4
80010c8: bf28 it cs
80010ca: 2304 movcs r3, #4
80010cc: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80010ce: 69fb ldr r3, [r7, #28]
80010d0: 3304 adds r3, #4
80010d2: 2b06 cmp r3, #6
80010d4: d902 bls.n 80010dc <NVIC_EncodePriority+0x30>
80010d6: 69fb ldr r3, [r7, #28]
80010d8: 3b03 subs r3, #3
80010da: e000 b.n 80010de <NVIC_EncodePriority+0x32>
80010dc: 2300 movs r3, #0
80010de: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80010e0: f04f 32ff mov.w r2, #4294967295
80010e4: 69bb ldr r3, [r7, #24]
80010e6: fa02 f303 lsl.w r3, r2, r3
80010ea: 43da mvns r2, r3
80010ec: 68bb ldr r3, [r7, #8]
80010ee: 401a ands r2, r3
80010f0: 697b ldr r3, [r7, #20]
80010f2: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80010f4: f04f 31ff mov.w r1, #4294967295
80010f8: 697b ldr r3, [r7, #20]
80010fa: fa01 f303 lsl.w r3, r1, r3
80010fe: 43d9 mvns r1, r3
8001100: 687b ldr r3, [r7, #4]
8001102: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001104: 4313 orrs r3, r2
);
}
8001106: 4618 mov r0, r3
8001108: 3724 adds r7, #36 ; 0x24
800110a: 46bd mov sp, r7
800110c: f85d 7b04 ldr.w r7, [sp], #4
8001110: 4770 bx lr
...
08001114 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001114: b580 push {r7, lr}
8001116: b082 sub sp, #8
8001118: af00 add r7, sp, #0
800111a: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
800111c: 687b ldr r3, [r7, #4]
800111e: 3b01 subs r3, #1
8001120: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8001124: d301 bcc.n 800112a <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8001126: 2301 movs r3, #1
8001128: e00f b.n 800114a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800112a: 4a0a ldr r2, [pc, #40] ; (8001154 <SysTick_Config+0x40>)
800112c: 687b ldr r3, [r7, #4]
800112e: 3b01 subs r3, #1
8001130: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8001132: 210f movs r1, #15
8001134: f04f 30ff mov.w r0, #4294967295
8001138: f7ff ff8e bl 8001058 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
800113c: 4b05 ldr r3, [pc, #20] ; (8001154 <SysTick_Config+0x40>)
800113e: 2200 movs r2, #0
8001140: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001142: 4b04 ldr r3, [pc, #16] ; (8001154 <SysTick_Config+0x40>)
8001144: 2207 movs r2, #7
8001146: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001148: 2300 movs r3, #0
}
800114a: 4618 mov r0, r3
800114c: 3708 adds r7, #8
800114e: 46bd mov sp, r7
8001150: bd80 pop {r7, pc}
8001152: bf00 nop
8001154: e000e010 .word 0xe000e010
08001158 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001158: b580 push {r7, lr}
800115a: b082 sub sp, #8
800115c: af00 add r7, sp, #0
800115e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001160: 6878 ldr r0, [r7, #4]
8001162: f7ff ff29 bl 8000fb8 <__NVIC_SetPriorityGrouping>
}
8001166: bf00 nop
8001168: 3708 adds r7, #8
800116a: 46bd mov sp, r7
800116c: bd80 pop {r7, pc}
0800116e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800116e: b580 push {r7, lr}
8001170: b086 sub sp, #24
8001172: af00 add r7, sp, #0
8001174: 4603 mov r3, r0
8001176: 60b9 str r1, [r7, #8]
8001178: 607a str r2, [r7, #4]
800117a: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
800117c: 2300 movs r3, #0
800117e: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001180: f7ff ff3e bl 8001000 <__NVIC_GetPriorityGrouping>
8001184: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001186: 687a ldr r2, [r7, #4]
8001188: 68b9 ldr r1, [r7, #8]
800118a: 6978 ldr r0, [r7, #20]
800118c: f7ff ff8e bl 80010ac <NVIC_EncodePriority>
8001190: 4602 mov r2, r0
8001192: f997 300f ldrsb.w r3, [r7, #15]
8001196: 4611 mov r1, r2
8001198: 4618 mov r0, r3
800119a: f7ff ff5d bl 8001058 <__NVIC_SetPriority>
}
800119e: bf00 nop
80011a0: 3718 adds r7, #24
80011a2: 46bd mov sp, r7
80011a4: bd80 pop {r7, pc}
080011a6 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80011a6: b580 push {r7, lr}
80011a8: b082 sub sp, #8
80011aa: af00 add r7, sp, #0
80011ac: 4603 mov r3, r0
80011ae: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80011b0: f997 3007 ldrsb.w r3, [r7, #7]
80011b4: 4618 mov r0, r3
80011b6: f7ff ff31 bl 800101c <__NVIC_EnableIRQ>
}
80011ba: bf00 nop
80011bc: 3708 adds r7, #8
80011be: 46bd mov sp, r7
80011c0: bd80 pop {r7, pc}
080011c2 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80011c2: b580 push {r7, lr}
80011c4: b082 sub sp, #8
80011c6: af00 add r7, sp, #0
80011c8: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80011ca: 6878 ldr r0, [r7, #4]
80011cc: f7ff ffa2 bl 8001114 <SysTick_Config>
80011d0: 4603 mov r3, r0
}
80011d2: 4618 mov r0, r3
80011d4: 3708 adds r7, #8
80011d6: 46bd mov sp, r7
80011d8: bd80 pop {r7, pc}
...
080011dc <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80011dc: b480 push {r7}
80011de: b089 sub sp, #36 ; 0x24
80011e0: af00 add r7, sp, #0
80011e2: 6078 str r0, [r7, #4]
80011e4: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
80011e6: 2300 movs r3, #0
80011e8: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
80011ea: 2300 movs r3, #0
80011ec: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
80011ee: 2300 movs r3, #0
80011f0: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
80011f2: 2300 movs r3, #0
80011f4: 61fb str r3, [r7, #28]
80011f6: e16b b.n 80014d0 <HAL_GPIO_Init+0x2f4>
{
/* Get the IO position */
ioposition = 0x01U << position;
80011f8: 2201 movs r2, #1
80011fa: 69fb ldr r3, [r7, #28]
80011fc: fa02 f303 lsl.w r3, r2, r3
8001200: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8001202: 683b ldr r3, [r7, #0]
8001204: 681b ldr r3, [r3, #0]
8001206: 697a ldr r2, [r7, #20]
8001208: 4013 ands r3, r2
800120a: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
800120c: 693a ldr r2, [r7, #16]
800120e: 697b ldr r3, [r7, #20]
8001210: 429a cmp r2, r3
8001212: f040 815a bne.w 80014ca <HAL_GPIO_Init+0x2ee>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8001216: 683b ldr r3, [r7, #0]
8001218: 685b ldr r3, [r3, #4]
800121a: f003 0303 and.w r3, r3, #3
800121e: 2b01 cmp r3, #1
8001220: d005 beq.n 800122e <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001222: 683b ldr r3, [r7, #0]
8001224: 685b ldr r3, [r3, #4]
8001226: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
800122a: 2b02 cmp r3, #2
800122c: d130 bne.n 8001290 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
800122e: 687b ldr r3, [r7, #4]
8001230: 689b ldr r3, [r3, #8]
8001232: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8001234: 69fb ldr r3, [r7, #28]
8001236: 005b lsls r3, r3, #1
8001238: 2203 movs r2, #3
800123a: fa02 f303 lsl.w r3, r2, r3
800123e: 43db mvns r3, r3
8001240: 69ba ldr r2, [r7, #24]
8001242: 4013 ands r3, r2
8001244: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8001246: 683b ldr r3, [r7, #0]
8001248: 68da ldr r2, [r3, #12]
800124a: 69fb ldr r3, [r7, #28]
800124c: 005b lsls r3, r3, #1
800124e: fa02 f303 lsl.w r3, r2, r3
8001252: 69ba ldr r2, [r7, #24]
8001254: 4313 orrs r3, r2
8001256: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8001258: 687b ldr r3, [r7, #4]
800125a: 69ba ldr r2, [r7, #24]
800125c: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
800125e: 687b ldr r3, [r7, #4]
8001260: 685b ldr r3, [r3, #4]
8001262: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001264: 2201 movs r2, #1
8001266: 69fb ldr r3, [r7, #28]
8001268: fa02 f303 lsl.w r3, r2, r3
800126c: 43db mvns r3, r3
800126e: 69ba ldr r2, [r7, #24]
8001270: 4013 ands r3, r2
8001272: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001274: 683b ldr r3, [r7, #0]
8001276: 685b ldr r3, [r3, #4]
8001278: 091b lsrs r3, r3, #4
800127a: f003 0201 and.w r2, r3, #1
800127e: 69fb ldr r3, [r7, #28]
8001280: fa02 f303 lsl.w r3, r2, r3
8001284: 69ba ldr r2, [r7, #24]
8001286: 4313 orrs r3, r2
8001288: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
800128a: 687b ldr r3, [r7, #4]
800128c: 69ba ldr r2, [r7, #24]
800128e: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001290: 683b ldr r3, [r7, #0]
8001292: 685b ldr r3, [r3, #4]
8001294: f003 0303 and.w r3, r3, #3
8001298: 2b03 cmp r3, #3
800129a: d017 beq.n 80012cc <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
800129c: 687b ldr r3, [r7, #4]
800129e: 68db ldr r3, [r3, #12]
80012a0: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
80012a2: 69fb ldr r3, [r7, #28]
80012a4: 005b lsls r3, r3, #1
80012a6: 2203 movs r2, #3
80012a8: fa02 f303 lsl.w r3, r2, r3
80012ac: 43db mvns r3, r3
80012ae: 69ba ldr r2, [r7, #24]
80012b0: 4013 ands r3, r2
80012b2: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
80012b4: 683b ldr r3, [r7, #0]
80012b6: 689a ldr r2, [r3, #8]
80012b8: 69fb ldr r3, [r7, #28]
80012ba: 005b lsls r3, r3, #1
80012bc: fa02 f303 lsl.w r3, r2, r3
80012c0: 69ba ldr r2, [r7, #24]
80012c2: 4313 orrs r3, r2
80012c4: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
80012c6: 687b ldr r3, [r7, #4]
80012c8: 69ba ldr r2, [r7, #24]
80012ca: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80012cc: 683b ldr r3, [r7, #0]
80012ce: 685b ldr r3, [r3, #4]
80012d0: f003 0303 and.w r3, r3, #3
80012d4: 2b02 cmp r3, #2
80012d6: d123 bne.n 8001320 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
80012d8: 69fb ldr r3, [r7, #28]
80012da: 08da lsrs r2, r3, #3
80012dc: 687b ldr r3, [r7, #4]
80012de: 3208 adds r2, #8
80012e0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80012e4: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
80012e6: 69fb ldr r3, [r7, #28]
80012e8: f003 0307 and.w r3, r3, #7
80012ec: 009b lsls r3, r3, #2
80012ee: 220f movs r2, #15
80012f0: fa02 f303 lsl.w r3, r2, r3
80012f4: 43db mvns r3, r3
80012f6: 69ba ldr r2, [r7, #24]
80012f8: 4013 ands r3, r2
80012fa: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
80012fc: 683b ldr r3, [r7, #0]
80012fe: 691a ldr r2, [r3, #16]
8001300: 69fb ldr r3, [r7, #28]
8001302: f003 0307 and.w r3, r3, #7
8001306: 009b lsls r3, r3, #2
8001308: fa02 f303 lsl.w r3, r2, r3
800130c: 69ba ldr r2, [r7, #24]
800130e: 4313 orrs r3, r2
8001310: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
8001312: 69fb ldr r3, [r7, #28]
8001314: 08da lsrs r2, r3, #3
8001316: 687b ldr r3, [r7, #4]
8001318: 3208 adds r2, #8
800131a: 69b9 ldr r1, [r7, #24]
800131c: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001320: 687b ldr r3, [r7, #4]
8001322: 681b ldr r3, [r3, #0]
8001324: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
8001326: 69fb ldr r3, [r7, #28]
8001328: 005b lsls r3, r3, #1
800132a: 2203 movs r2, #3
800132c: fa02 f303 lsl.w r3, r2, r3
8001330: 43db mvns r3, r3
8001332: 69ba ldr r2, [r7, #24]
8001334: 4013 ands r3, r2
8001336: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8001338: 683b ldr r3, [r7, #0]
800133a: 685b ldr r3, [r3, #4]
800133c: f003 0203 and.w r2, r3, #3
8001340: 69fb ldr r3, [r7, #28]
8001342: 005b lsls r3, r3, #1
8001344: fa02 f303 lsl.w r3, r2, r3
8001348: 69ba ldr r2, [r7, #24]
800134a: 4313 orrs r3, r2
800134c: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
800134e: 687b ldr r3, [r7, #4]
8001350: 69ba ldr r2, [r7, #24]
8001352: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8001354: 683b ldr r3, [r7, #0]
8001356: 685b ldr r3, [r3, #4]
8001358: f403 3340 and.w r3, r3, #196608 ; 0x30000
800135c: 2b00 cmp r3, #0
800135e: f000 80b4 beq.w 80014ca <HAL_GPIO_Init+0x2ee>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001362: 2300 movs r3, #0
8001364: 60fb str r3, [r7, #12]
8001366: 4b60 ldr r3, [pc, #384] ; (80014e8 <HAL_GPIO_Init+0x30c>)
8001368: 6c5b ldr r3, [r3, #68] ; 0x44
800136a: 4a5f ldr r2, [pc, #380] ; (80014e8 <HAL_GPIO_Init+0x30c>)
800136c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8001370: 6453 str r3, [r2, #68] ; 0x44
8001372: 4b5d ldr r3, [pc, #372] ; (80014e8 <HAL_GPIO_Init+0x30c>)
8001374: 6c5b ldr r3, [r3, #68] ; 0x44
8001376: f403 4380 and.w r3, r3, #16384 ; 0x4000
800137a: 60fb str r3, [r7, #12]
800137c: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
800137e: 4a5b ldr r2, [pc, #364] ; (80014ec <HAL_GPIO_Init+0x310>)
8001380: 69fb ldr r3, [r7, #28]
8001382: 089b lsrs r3, r3, #2
8001384: 3302 adds r3, #2
8001386: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800138a: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
800138c: 69fb ldr r3, [r7, #28]
800138e: f003 0303 and.w r3, r3, #3
8001392: 009b lsls r3, r3, #2
8001394: 220f movs r2, #15
8001396: fa02 f303 lsl.w r3, r2, r3
800139a: 43db mvns r3, r3
800139c: 69ba ldr r2, [r7, #24]
800139e: 4013 ands r3, r2
80013a0: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
80013a2: 687b ldr r3, [r7, #4]
80013a4: 4a52 ldr r2, [pc, #328] ; (80014f0 <HAL_GPIO_Init+0x314>)
80013a6: 4293 cmp r3, r2
80013a8: d02b beq.n 8001402 <HAL_GPIO_Init+0x226>
80013aa: 687b ldr r3, [r7, #4]
80013ac: 4a51 ldr r2, [pc, #324] ; (80014f4 <HAL_GPIO_Init+0x318>)
80013ae: 4293 cmp r3, r2
80013b0: d025 beq.n 80013fe <HAL_GPIO_Init+0x222>
80013b2: 687b ldr r3, [r7, #4]
80013b4: 4a50 ldr r2, [pc, #320] ; (80014f8 <HAL_GPIO_Init+0x31c>)
80013b6: 4293 cmp r3, r2
80013b8: d01f beq.n 80013fa <HAL_GPIO_Init+0x21e>
80013ba: 687b ldr r3, [r7, #4]
80013bc: 4a4f ldr r2, [pc, #316] ; (80014fc <HAL_GPIO_Init+0x320>)
80013be: 4293 cmp r3, r2
80013c0: d019 beq.n 80013f6 <HAL_GPIO_Init+0x21a>
80013c2: 687b ldr r3, [r7, #4]
80013c4: 4a4e ldr r2, [pc, #312] ; (8001500 <HAL_GPIO_Init+0x324>)
80013c6: 4293 cmp r3, r2
80013c8: d013 beq.n 80013f2 <HAL_GPIO_Init+0x216>
80013ca: 687b ldr r3, [r7, #4]
80013cc: 4a4d ldr r2, [pc, #308] ; (8001504 <HAL_GPIO_Init+0x328>)
80013ce: 4293 cmp r3, r2
80013d0: d00d beq.n 80013ee <HAL_GPIO_Init+0x212>
80013d2: 687b ldr r3, [r7, #4]
80013d4: 4a4c ldr r2, [pc, #304] ; (8001508 <HAL_GPIO_Init+0x32c>)
80013d6: 4293 cmp r3, r2
80013d8: d007 beq.n 80013ea <HAL_GPIO_Init+0x20e>
80013da: 687b ldr r3, [r7, #4]
80013dc: 4a4b ldr r2, [pc, #300] ; (800150c <HAL_GPIO_Init+0x330>)
80013de: 4293 cmp r3, r2
80013e0: d101 bne.n 80013e6 <HAL_GPIO_Init+0x20a>
80013e2: 2307 movs r3, #7
80013e4: e00e b.n 8001404 <HAL_GPIO_Init+0x228>
80013e6: 2308 movs r3, #8
80013e8: e00c b.n 8001404 <HAL_GPIO_Init+0x228>
80013ea: 2306 movs r3, #6
80013ec: e00a b.n 8001404 <HAL_GPIO_Init+0x228>
80013ee: 2305 movs r3, #5
80013f0: e008 b.n 8001404 <HAL_GPIO_Init+0x228>
80013f2: 2304 movs r3, #4
80013f4: e006 b.n 8001404 <HAL_GPIO_Init+0x228>
80013f6: 2303 movs r3, #3
80013f8: e004 b.n 8001404 <HAL_GPIO_Init+0x228>
80013fa: 2302 movs r3, #2
80013fc: e002 b.n 8001404 <HAL_GPIO_Init+0x228>
80013fe: 2301 movs r3, #1
8001400: e000 b.n 8001404 <HAL_GPIO_Init+0x228>
8001402: 2300 movs r3, #0
8001404: 69fa ldr r2, [r7, #28]
8001406: f002 0203 and.w r2, r2, #3
800140a: 0092 lsls r2, r2, #2
800140c: 4093 lsls r3, r2
800140e: 69ba ldr r2, [r7, #24]
8001410: 4313 orrs r3, r2
8001412: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8001414: 4935 ldr r1, [pc, #212] ; (80014ec <HAL_GPIO_Init+0x310>)
8001416: 69fb ldr r3, [r7, #28]
8001418: 089b lsrs r3, r3, #2
800141a: 3302 adds r3, #2
800141c: 69ba ldr r2, [r7, #24]
800141e: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001422: 4b3b ldr r3, [pc, #236] ; (8001510 <HAL_GPIO_Init+0x334>)
8001424: 689b ldr r3, [r3, #8]
8001426: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001428: 693b ldr r3, [r7, #16]
800142a: 43db mvns r3, r3
800142c: 69ba ldr r2, [r7, #24]
800142e: 4013 ands r3, r2
8001430: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8001432: 683b ldr r3, [r7, #0]
8001434: 685b ldr r3, [r3, #4]
8001436: f403 1380 and.w r3, r3, #1048576 ; 0x100000
800143a: 2b00 cmp r3, #0
800143c: d003 beq.n 8001446 <HAL_GPIO_Init+0x26a>
{
temp |= iocurrent;
800143e: 69ba ldr r2, [r7, #24]
8001440: 693b ldr r3, [r7, #16]
8001442: 4313 orrs r3, r2
8001444: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8001446: 4a32 ldr r2, [pc, #200] ; (8001510 <HAL_GPIO_Init+0x334>)
8001448: 69bb ldr r3, [r7, #24]
800144a: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
800144c: 4b30 ldr r3, [pc, #192] ; (8001510 <HAL_GPIO_Init+0x334>)
800144e: 68db ldr r3, [r3, #12]
8001450: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001452: 693b ldr r3, [r7, #16]
8001454: 43db mvns r3, r3
8001456: 69ba ldr r2, [r7, #24]
8001458: 4013 ands r3, r2
800145a: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
800145c: 683b ldr r3, [r7, #0]
800145e: 685b ldr r3, [r3, #4]
8001460: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8001464: 2b00 cmp r3, #0
8001466: d003 beq.n 8001470 <HAL_GPIO_Init+0x294>
{
temp |= iocurrent;
8001468: 69ba ldr r2, [r7, #24]
800146a: 693b ldr r3, [r7, #16]
800146c: 4313 orrs r3, r2
800146e: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8001470: 4a27 ldr r2, [pc, #156] ; (8001510 <HAL_GPIO_Init+0x334>)
8001472: 69bb ldr r3, [r7, #24]
8001474: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001476: 4b26 ldr r3, [pc, #152] ; (8001510 <HAL_GPIO_Init+0x334>)
8001478: 685b ldr r3, [r3, #4]
800147a: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800147c: 693b ldr r3, [r7, #16]
800147e: 43db mvns r3, r3
8001480: 69ba ldr r2, [r7, #24]
8001482: 4013 ands r3, r2
8001484: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8001486: 683b ldr r3, [r7, #0]
8001488: 685b ldr r3, [r3, #4]
800148a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800148e: 2b00 cmp r3, #0
8001490: d003 beq.n 800149a <HAL_GPIO_Init+0x2be>
{
temp |= iocurrent;
8001492: 69ba ldr r2, [r7, #24]
8001494: 693b ldr r3, [r7, #16]
8001496: 4313 orrs r3, r2
8001498: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
800149a: 4a1d ldr r2, [pc, #116] ; (8001510 <HAL_GPIO_Init+0x334>)
800149c: 69bb ldr r3, [r7, #24]
800149e: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80014a0: 4b1b ldr r3, [pc, #108] ; (8001510 <HAL_GPIO_Init+0x334>)
80014a2: 681b ldr r3, [r3, #0]
80014a4: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80014a6: 693b ldr r3, [r7, #16]
80014a8: 43db mvns r3, r3
80014aa: 69ba ldr r2, [r7, #24]
80014ac: 4013 ands r3, r2
80014ae: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
80014b0: 683b ldr r3, [r7, #0]
80014b2: 685b ldr r3, [r3, #4]
80014b4: f403 3380 and.w r3, r3, #65536 ; 0x10000
80014b8: 2b00 cmp r3, #0
80014ba: d003 beq.n 80014c4 <HAL_GPIO_Init+0x2e8>
{
temp |= iocurrent;
80014bc: 69ba ldr r2, [r7, #24]
80014be: 693b ldr r3, [r7, #16]
80014c0: 4313 orrs r3, r2
80014c2: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
80014c4: 4a12 ldr r2, [pc, #72] ; (8001510 <HAL_GPIO_Init+0x334>)
80014c6: 69bb ldr r3, [r7, #24]
80014c8: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
80014ca: 69fb ldr r3, [r7, #28]
80014cc: 3301 adds r3, #1
80014ce: 61fb str r3, [r7, #28]
80014d0: 69fb ldr r3, [r7, #28]
80014d2: 2b0f cmp r3, #15
80014d4: f67f ae90 bls.w 80011f8 <HAL_GPIO_Init+0x1c>
}
}
}
}
80014d8: bf00 nop
80014da: bf00 nop
80014dc: 3724 adds r7, #36 ; 0x24
80014de: 46bd mov sp, r7
80014e0: f85d 7b04 ldr.w r7, [sp], #4
80014e4: 4770 bx lr
80014e6: bf00 nop
80014e8: 40023800 .word 0x40023800
80014ec: 40013800 .word 0x40013800
80014f0: 40020000 .word 0x40020000
80014f4: 40020400 .word 0x40020400
80014f8: 40020800 .word 0x40020800
80014fc: 40020c00 .word 0x40020c00
8001500: 40021000 .word 0x40021000
8001504: 40021400 .word 0x40021400
8001508: 40021800 .word 0x40021800
800150c: 40021c00 .word 0x40021c00
8001510: 40013c00 .word 0x40013c00
08001514 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001514: b480 push {r7}
8001516: b083 sub sp, #12
8001518: af00 add r7, sp, #0
800151a: 6078 str r0, [r7, #4]
800151c: 460b mov r3, r1
800151e: 807b strh r3, [r7, #2]
8001520: 4613 mov r3, r2
8001522: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8001524: 787b ldrb r3, [r7, #1]
8001526: 2b00 cmp r3, #0
8001528: d003 beq.n 8001532 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
800152a: 887a ldrh r2, [r7, #2]
800152c: 687b ldr r3, [r7, #4]
800152e: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
8001530: e003 b.n 800153a <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
8001532: 887b ldrh r3, [r7, #2]
8001534: 041a lsls r2, r3, #16
8001536: 687b ldr r3, [r7, #4]
8001538: 619a str r2, [r3, #24]
}
800153a: bf00 nop
800153c: 370c adds r7, #12
800153e: 46bd mov sp, r7
8001540: f85d 7b04 ldr.w r7, [sp], #4
8001544: 4770 bx lr
08001546 <HAL_GPIO_TogglePin>:
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
* @param GPIO_Pin Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8001546: b480 push {r7}
8001548: b085 sub sp, #20
800154a: af00 add r7, sp, #0
800154c: 6078 str r0, [r7, #4]
800154e: 460b mov r3, r1
8001550: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8001552: 687b ldr r3, [r7, #4]
8001554: 695b ldr r3, [r3, #20]
8001556: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8001558: 887a ldrh r2, [r7, #2]
800155a: 68fb ldr r3, [r7, #12]
800155c: 4013 ands r3, r2
800155e: 041a lsls r2, r3, #16
8001560: 68fb ldr r3, [r7, #12]
8001562: 43d9 mvns r1, r3
8001564: 887b ldrh r3, [r7, #2]
8001566: 400b ands r3, r1
8001568: 431a orrs r2, r3
800156a: 687b ldr r3, [r7, #4]
800156c: 619a str r2, [r3, #24]
}
800156e: bf00 nop
8001570: 3714 adds r7, #20
8001572: 46bd mov sp, r7
8001574: f85d 7b04 ldr.w r7, [sp], #4
8001578: 4770 bx lr
...
0800157c <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
800157c: b580 push {r7, lr}
800157e: b086 sub sp, #24
8001580: af00 add r7, sp, #0
8001582: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8001584: 687b ldr r3, [r7, #4]
8001586: 2b00 cmp r3, #0
8001588: d101 bne.n 800158e <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800158a: 2301 movs r3, #1
800158c: e267 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800158e: 687b ldr r3, [r7, #4]
8001590: 681b ldr r3, [r3, #0]
8001592: f003 0301 and.w r3, r3, #1
8001596: 2b00 cmp r3, #0
8001598: d075 beq.n 8001686 <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
800159a: 4b88 ldr r3, [pc, #544] ; (80017bc <HAL_RCC_OscConfig+0x240>)
800159c: 689b ldr r3, [r3, #8]
800159e: f003 030c and.w r3, r3, #12
80015a2: 2b04 cmp r3, #4
80015a4: d00c beq.n 80015c0 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80015a6: 4b85 ldr r3, [pc, #532] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80015a8: 689b ldr r3, [r3, #8]
80015aa: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
80015ae: 2b08 cmp r3, #8
80015b0: d112 bne.n 80015d8 <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80015b2: 4b82 ldr r3, [pc, #520] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80015b4: 685b ldr r3, [r3, #4]
80015b6: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80015ba: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80015be: d10b bne.n 80015d8 <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80015c0: 4b7e ldr r3, [pc, #504] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80015c2: 681b ldr r3, [r3, #0]
80015c4: f403 3300 and.w r3, r3, #131072 ; 0x20000
80015c8: 2b00 cmp r3, #0
80015ca: d05b beq.n 8001684 <HAL_RCC_OscConfig+0x108>
80015cc: 687b ldr r3, [r7, #4]
80015ce: 685b ldr r3, [r3, #4]
80015d0: 2b00 cmp r3, #0
80015d2: d157 bne.n 8001684 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
80015d4: 2301 movs r3, #1
80015d6: e242 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80015d8: 687b ldr r3, [r7, #4]
80015da: 685b ldr r3, [r3, #4]
80015dc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80015e0: d106 bne.n 80015f0 <HAL_RCC_OscConfig+0x74>
80015e2: 4b76 ldr r3, [pc, #472] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80015e4: 681b ldr r3, [r3, #0]
80015e6: 4a75 ldr r2, [pc, #468] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80015e8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80015ec: 6013 str r3, [r2, #0]
80015ee: e01d b.n 800162c <HAL_RCC_OscConfig+0xb0>
80015f0: 687b ldr r3, [r7, #4]
80015f2: 685b ldr r3, [r3, #4]
80015f4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
80015f8: d10c bne.n 8001614 <HAL_RCC_OscConfig+0x98>
80015fa: 4b70 ldr r3, [pc, #448] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80015fc: 681b ldr r3, [r3, #0]
80015fe: 4a6f ldr r2, [pc, #444] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001600: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8001604: 6013 str r3, [r2, #0]
8001606: 4b6d ldr r3, [pc, #436] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001608: 681b ldr r3, [r3, #0]
800160a: 4a6c ldr r2, [pc, #432] ; (80017bc <HAL_RCC_OscConfig+0x240>)
800160c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001610: 6013 str r3, [r2, #0]
8001612: e00b b.n 800162c <HAL_RCC_OscConfig+0xb0>
8001614: 4b69 ldr r3, [pc, #420] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001616: 681b ldr r3, [r3, #0]
8001618: 4a68 ldr r2, [pc, #416] ; (80017bc <HAL_RCC_OscConfig+0x240>)
800161a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800161e: 6013 str r3, [r2, #0]
8001620: 4b66 ldr r3, [pc, #408] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001622: 681b ldr r3, [r3, #0]
8001624: 4a65 ldr r2, [pc, #404] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001626: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800162a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
800162c: 687b ldr r3, [r7, #4]
800162e: 685b ldr r3, [r3, #4]
8001630: 2b00 cmp r3, #0
8001632: d013 beq.n 800165c <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001634: f7ff fcb4 bl 8000fa0 <HAL_GetTick>
8001638: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800163a: e008 b.n 800164e <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800163c: f7ff fcb0 bl 8000fa0 <HAL_GetTick>
8001640: 4602 mov r2, r0
8001642: 693b ldr r3, [r7, #16]
8001644: 1ad3 subs r3, r2, r3
8001646: 2b64 cmp r3, #100 ; 0x64
8001648: d901 bls.n 800164e <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
800164a: 2303 movs r3, #3
800164c: e207 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800164e: 4b5b ldr r3, [pc, #364] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001650: 681b ldr r3, [r3, #0]
8001652: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001656: 2b00 cmp r3, #0
8001658: d0f0 beq.n 800163c <HAL_RCC_OscConfig+0xc0>
800165a: e014 b.n 8001686 <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800165c: f7ff fca0 bl 8000fa0 <HAL_GetTick>
8001660: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001662: e008 b.n 8001676 <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001664: f7ff fc9c bl 8000fa0 <HAL_GetTick>
8001668: 4602 mov r2, r0
800166a: 693b ldr r3, [r7, #16]
800166c: 1ad3 subs r3, r2, r3
800166e: 2b64 cmp r3, #100 ; 0x64
8001670: d901 bls.n 8001676 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8001672: 2303 movs r3, #3
8001674: e1f3 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001676: 4b51 ldr r3, [pc, #324] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001678: 681b ldr r3, [r3, #0]
800167a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800167e: 2b00 cmp r3, #0
8001680: d1f0 bne.n 8001664 <HAL_RCC_OscConfig+0xe8>
8001682: e000 b.n 8001686 <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001684: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001686: 687b ldr r3, [r7, #4]
8001688: 681b ldr r3, [r3, #0]
800168a: f003 0302 and.w r3, r3, #2
800168e: 2b00 cmp r3, #0
8001690: d063 beq.n 800175a <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8001692: 4b4a ldr r3, [pc, #296] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001694: 689b ldr r3, [r3, #8]
8001696: f003 030c and.w r3, r3, #12
800169a: 2b00 cmp r3, #0
800169c: d00b beq.n 80016b6 <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
800169e: 4b47 ldr r3, [pc, #284] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80016a0: 689b ldr r3, [r3, #8]
80016a2: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
80016a6: 2b08 cmp r3, #8
80016a8: d11c bne.n 80016e4 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80016aa: 4b44 ldr r3, [pc, #272] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80016ac: 685b ldr r3, [r3, #4]
80016ae: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80016b2: 2b00 cmp r3, #0
80016b4: d116 bne.n 80016e4 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80016b6: 4b41 ldr r3, [pc, #260] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80016b8: 681b ldr r3, [r3, #0]
80016ba: f003 0302 and.w r3, r3, #2
80016be: 2b00 cmp r3, #0
80016c0: d005 beq.n 80016ce <HAL_RCC_OscConfig+0x152>
80016c2: 687b ldr r3, [r7, #4]
80016c4: 68db ldr r3, [r3, #12]
80016c6: 2b01 cmp r3, #1
80016c8: d001 beq.n 80016ce <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
80016ca: 2301 movs r3, #1
80016cc: e1c7 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80016ce: 4b3b ldr r3, [pc, #236] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80016d0: 681b ldr r3, [r3, #0]
80016d2: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80016d6: 687b ldr r3, [r7, #4]
80016d8: 691b ldr r3, [r3, #16]
80016da: 00db lsls r3, r3, #3
80016dc: 4937 ldr r1, [pc, #220] ; (80017bc <HAL_RCC_OscConfig+0x240>)
80016de: 4313 orrs r3, r2
80016e0: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80016e2: e03a b.n 800175a <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
80016e4: 687b ldr r3, [r7, #4]
80016e6: 68db ldr r3, [r3, #12]
80016e8: 2b00 cmp r3, #0
80016ea: d020 beq.n 800172e <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80016ec: 4b34 ldr r3, [pc, #208] ; (80017c0 <HAL_RCC_OscConfig+0x244>)
80016ee: 2201 movs r2, #1
80016f0: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80016f2: f7ff fc55 bl 8000fa0 <HAL_GetTick>
80016f6: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80016f8: e008 b.n 800170c <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80016fa: f7ff fc51 bl 8000fa0 <HAL_GetTick>
80016fe: 4602 mov r2, r0
8001700: 693b ldr r3, [r7, #16]
8001702: 1ad3 subs r3, r2, r3
8001704: 2b02 cmp r3, #2
8001706: d901 bls.n 800170c <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
8001708: 2303 movs r3, #3
800170a: e1a8 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800170c: 4b2b ldr r3, [pc, #172] ; (80017bc <HAL_RCC_OscConfig+0x240>)
800170e: 681b ldr r3, [r3, #0]
8001710: f003 0302 and.w r3, r3, #2
8001714: 2b00 cmp r3, #0
8001716: d0f0 beq.n 80016fa <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001718: 4b28 ldr r3, [pc, #160] ; (80017bc <HAL_RCC_OscConfig+0x240>)
800171a: 681b ldr r3, [r3, #0]
800171c: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8001720: 687b ldr r3, [r7, #4]
8001722: 691b ldr r3, [r3, #16]
8001724: 00db lsls r3, r3, #3
8001726: 4925 ldr r1, [pc, #148] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001728: 4313 orrs r3, r2
800172a: 600b str r3, [r1, #0]
800172c: e015 b.n 800175a <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800172e: 4b24 ldr r3, [pc, #144] ; (80017c0 <HAL_RCC_OscConfig+0x244>)
8001730: 2200 movs r2, #0
8001732: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001734: f7ff fc34 bl 8000fa0 <HAL_GetTick>
8001738: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800173a: e008 b.n 800174e <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800173c: f7ff fc30 bl 8000fa0 <HAL_GetTick>
8001740: 4602 mov r2, r0
8001742: 693b ldr r3, [r7, #16]
8001744: 1ad3 subs r3, r2, r3
8001746: 2b02 cmp r3, #2
8001748: d901 bls.n 800174e <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
800174a: 2303 movs r3, #3
800174c: e187 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800174e: 4b1b ldr r3, [pc, #108] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001750: 681b ldr r3, [r3, #0]
8001752: f003 0302 and.w r3, r3, #2
8001756: 2b00 cmp r3, #0
8001758: d1f0 bne.n 800173c <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800175a: 687b ldr r3, [r7, #4]
800175c: 681b ldr r3, [r3, #0]
800175e: f003 0308 and.w r3, r3, #8
8001762: 2b00 cmp r3, #0
8001764: d036 beq.n 80017d4 <HAL_RCC_OscConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
8001766: 687b ldr r3, [r7, #4]
8001768: 695b ldr r3, [r3, #20]
800176a: 2b00 cmp r3, #0
800176c: d016 beq.n 800179c <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
800176e: 4b15 ldr r3, [pc, #84] ; (80017c4 <HAL_RCC_OscConfig+0x248>)
8001770: 2201 movs r2, #1
8001772: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001774: f7ff fc14 bl 8000fa0 <HAL_GetTick>
8001778: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800177a: e008 b.n 800178e <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800177c: f7ff fc10 bl 8000fa0 <HAL_GetTick>
8001780: 4602 mov r2, r0
8001782: 693b ldr r3, [r7, #16]
8001784: 1ad3 subs r3, r2, r3
8001786: 2b02 cmp r3, #2
8001788: d901 bls.n 800178e <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
800178a: 2303 movs r3, #3
800178c: e167 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800178e: 4b0b ldr r3, [pc, #44] ; (80017bc <HAL_RCC_OscConfig+0x240>)
8001790: 6f5b ldr r3, [r3, #116] ; 0x74
8001792: f003 0302 and.w r3, r3, #2
8001796: 2b00 cmp r3, #0
8001798: d0f0 beq.n 800177c <HAL_RCC_OscConfig+0x200>
800179a: e01b b.n 80017d4 <HAL_RCC_OscConfig+0x258>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
800179c: 4b09 ldr r3, [pc, #36] ; (80017c4 <HAL_RCC_OscConfig+0x248>)
800179e: 2200 movs r2, #0
80017a0: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80017a2: f7ff fbfd bl 8000fa0 <HAL_GetTick>
80017a6: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80017a8: e00e b.n 80017c8 <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80017aa: f7ff fbf9 bl 8000fa0 <HAL_GetTick>
80017ae: 4602 mov r2, r0
80017b0: 693b ldr r3, [r7, #16]
80017b2: 1ad3 subs r3, r2, r3
80017b4: 2b02 cmp r3, #2
80017b6: d907 bls.n 80017c8 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
80017b8: 2303 movs r3, #3
80017ba: e150 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
80017bc: 40023800 .word 0x40023800
80017c0: 42470000 .word 0x42470000
80017c4: 42470e80 .word 0x42470e80
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80017c8: 4b88 ldr r3, [pc, #544] ; (80019ec <HAL_RCC_OscConfig+0x470>)
80017ca: 6f5b ldr r3, [r3, #116] ; 0x74
80017cc: f003 0302 and.w r3, r3, #2
80017d0: 2b00 cmp r3, #0
80017d2: d1ea bne.n 80017aa <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80017d4: 687b ldr r3, [r7, #4]
80017d6: 681b ldr r3, [r3, #0]
80017d8: f003 0304 and.w r3, r3, #4
80017dc: 2b00 cmp r3, #0
80017de: f000 8097 beq.w 8001910 <HAL_RCC_OscConfig+0x394>
{
FlagStatus pwrclkchanged = RESET;
80017e2: 2300 movs r3, #0
80017e4: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80017e6: 4b81 ldr r3, [pc, #516] ; (80019ec <HAL_RCC_OscConfig+0x470>)
80017e8: 6c1b ldr r3, [r3, #64] ; 0x40
80017ea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80017ee: 2b00 cmp r3, #0
80017f0: d10f bne.n 8001812 <HAL_RCC_OscConfig+0x296>
{
__HAL_RCC_PWR_CLK_ENABLE();
80017f2: 2300 movs r3, #0
80017f4: 60bb str r3, [r7, #8]
80017f6: 4b7d ldr r3, [pc, #500] ; (80019ec <HAL_RCC_OscConfig+0x470>)
80017f8: 6c1b ldr r3, [r3, #64] ; 0x40
80017fa: 4a7c ldr r2, [pc, #496] ; (80019ec <HAL_RCC_OscConfig+0x470>)
80017fc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001800: 6413 str r3, [r2, #64] ; 0x40
8001802: 4b7a ldr r3, [pc, #488] ; (80019ec <HAL_RCC_OscConfig+0x470>)
8001804: 6c1b ldr r3, [r3, #64] ; 0x40
8001806: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800180a: 60bb str r3, [r7, #8]
800180c: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800180e: 2301 movs r3, #1
8001810: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001812: 4b77 ldr r3, [pc, #476] ; (80019f0 <HAL_RCC_OscConfig+0x474>)
8001814: 681b ldr r3, [r3, #0]
8001816: f403 7380 and.w r3, r3, #256 ; 0x100
800181a: 2b00 cmp r3, #0
800181c: d118 bne.n 8001850 <HAL_RCC_OscConfig+0x2d4>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
800181e: 4b74 ldr r3, [pc, #464] ; (80019f0 <HAL_RCC_OscConfig+0x474>)
8001820: 681b ldr r3, [r3, #0]
8001822: 4a73 ldr r2, [pc, #460] ; (80019f0 <HAL_RCC_OscConfig+0x474>)
8001824: f443 7380 orr.w r3, r3, #256 ; 0x100
8001828: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800182a: f7ff fbb9 bl 8000fa0 <HAL_GetTick>
800182e: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001830: e008 b.n 8001844 <HAL_RCC_OscConfig+0x2c8>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001832: f7ff fbb5 bl 8000fa0 <HAL_GetTick>
8001836: 4602 mov r2, r0
8001838: 693b ldr r3, [r7, #16]
800183a: 1ad3 subs r3, r2, r3
800183c: 2b02 cmp r3, #2
800183e: d901 bls.n 8001844 <HAL_RCC_OscConfig+0x2c8>
{
return HAL_TIMEOUT;
8001840: 2303 movs r3, #3
8001842: e10c b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001844: 4b6a ldr r3, [pc, #424] ; (80019f0 <HAL_RCC_OscConfig+0x474>)
8001846: 681b ldr r3, [r3, #0]
8001848: f403 7380 and.w r3, r3, #256 ; 0x100
800184c: 2b00 cmp r3, #0
800184e: d0f0 beq.n 8001832 <HAL_RCC_OscConfig+0x2b6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001850: 687b ldr r3, [r7, #4]
8001852: 689b ldr r3, [r3, #8]
8001854: 2b01 cmp r3, #1
8001856: d106 bne.n 8001866 <HAL_RCC_OscConfig+0x2ea>
8001858: 4b64 ldr r3, [pc, #400] ; (80019ec <HAL_RCC_OscConfig+0x470>)
800185a: 6f1b ldr r3, [r3, #112] ; 0x70
800185c: 4a63 ldr r2, [pc, #396] ; (80019ec <HAL_RCC_OscConfig+0x470>)
800185e: f043 0301 orr.w r3, r3, #1
8001862: 6713 str r3, [r2, #112] ; 0x70
8001864: e01c b.n 80018a0 <HAL_RCC_OscConfig+0x324>
8001866: 687b ldr r3, [r7, #4]
8001868: 689b ldr r3, [r3, #8]
800186a: 2b05 cmp r3, #5
800186c: d10c bne.n 8001888 <HAL_RCC_OscConfig+0x30c>
800186e: 4b5f ldr r3, [pc, #380] ; (80019ec <HAL_RCC_OscConfig+0x470>)
8001870: 6f1b ldr r3, [r3, #112] ; 0x70
8001872: 4a5e ldr r2, [pc, #376] ; (80019ec <HAL_RCC_OscConfig+0x470>)
8001874: f043 0304 orr.w r3, r3, #4
8001878: 6713 str r3, [r2, #112] ; 0x70
800187a: 4b5c ldr r3, [pc, #368] ; (80019ec <HAL_RCC_OscConfig+0x470>)
800187c: 6f1b ldr r3, [r3, #112] ; 0x70
800187e: 4a5b ldr r2, [pc, #364] ; (80019ec <HAL_RCC_OscConfig+0x470>)
8001880: f043 0301 orr.w r3, r3, #1
8001884: 6713 str r3, [r2, #112] ; 0x70
8001886: e00b b.n 80018a0 <HAL_RCC_OscConfig+0x324>
8001888: 4b58 ldr r3, [pc, #352] ; (80019ec <HAL_RCC_OscConfig+0x470>)
800188a: 6f1b ldr r3, [r3, #112] ; 0x70
800188c: 4a57 ldr r2, [pc, #348] ; (80019ec <HAL_RCC_OscConfig+0x470>)
800188e: f023 0301 bic.w r3, r3, #1
8001892: 6713 str r3, [r2, #112] ; 0x70
8001894: 4b55 ldr r3, [pc, #340] ; (80019ec <HAL_RCC_OscConfig+0x470>)
8001896: 6f1b ldr r3, [r3, #112] ; 0x70
8001898: 4a54 ldr r2, [pc, #336] ; (80019ec <HAL_RCC_OscConfig+0x470>)
800189a: f023 0304 bic.w r3, r3, #4
800189e: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
80018a0: 687b ldr r3, [r7, #4]
80018a2: 689b ldr r3, [r3, #8]
80018a4: 2b00 cmp r3, #0
80018a6: d015 beq.n 80018d4 <HAL_RCC_OscConfig+0x358>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80018a8: f7ff fb7a bl 8000fa0 <HAL_GetTick>
80018ac: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80018ae: e00a b.n 80018c6 <HAL_RCC_OscConfig+0x34a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80018b0: f7ff fb76 bl 8000fa0 <HAL_GetTick>
80018b4: 4602 mov r2, r0
80018b6: 693b ldr r3, [r7, #16]
80018b8: 1ad3 subs r3, r2, r3
80018ba: f241 3288 movw r2, #5000 ; 0x1388
80018be: 4293 cmp r3, r2
80018c0: d901 bls.n 80018c6 <HAL_RCC_OscConfig+0x34a>
{
return HAL_TIMEOUT;
80018c2: 2303 movs r3, #3
80018c4: e0cb b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80018c6: 4b49 ldr r3, [pc, #292] ; (80019ec <HAL_RCC_OscConfig+0x470>)
80018c8: 6f1b ldr r3, [r3, #112] ; 0x70
80018ca: f003 0302 and.w r3, r3, #2
80018ce: 2b00 cmp r3, #0
80018d0: d0ee beq.n 80018b0 <HAL_RCC_OscConfig+0x334>
80018d2: e014 b.n 80018fe <HAL_RCC_OscConfig+0x382>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80018d4: f7ff fb64 bl 8000fa0 <HAL_GetTick>
80018d8: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80018da: e00a b.n 80018f2 <HAL_RCC_OscConfig+0x376>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80018dc: f7ff fb60 bl 8000fa0 <HAL_GetTick>
80018e0: 4602 mov r2, r0
80018e2: 693b ldr r3, [r7, #16]
80018e4: 1ad3 subs r3, r2, r3
80018e6: f241 3288 movw r2, #5000 ; 0x1388
80018ea: 4293 cmp r3, r2
80018ec: d901 bls.n 80018f2 <HAL_RCC_OscConfig+0x376>
{
return HAL_TIMEOUT;
80018ee: 2303 movs r3, #3
80018f0: e0b5 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80018f2: 4b3e ldr r3, [pc, #248] ; (80019ec <HAL_RCC_OscConfig+0x470>)
80018f4: 6f1b ldr r3, [r3, #112] ; 0x70
80018f6: f003 0302 and.w r3, r3, #2
80018fa: 2b00 cmp r3, #0
80018fc: d1ee bne.n 80018dc <HAL_RCC_OscConfig+0x360>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
80018fe: 7dfb ldrb r3, [r7, #23]
8001900: 2b01 cmp r3, #1
8001902: d105 bne.n 8001910 <HAL_RCC_OscConfig+0x394>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001904: 4b39 ldr r3, [pc, #228] ; (80019ec <HAL_RCC_OscConfig+0x470>)
8001906: 6c1b ldr r3, [r3, #64] ; 0x40
8001908: 4a38 ldr r2, [pc, #224] ; (80019ec <HAL_RCC_OscConfig+0x470>)
800190a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
800190e: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001910: 687b ldr r3, [r7, #4]
8001912: 699b ldr r3, [r3, #24]
8001914: 2b00 cmp r3, #0
8001916: f000 80a1 beq.w 8001a5c <HAL_RCC_OscConfig+0x4e0>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
800191a: 4b34 ldr r3, [pc, #208] ; (80019ec <HAL_RCC_OscConfig+0x470>)
800191c: 689b ldr r3, [r3, #8]
800191e: f003 030c and.w r3, r3, #12
8001922: 2b08 cmp r3, #8
8001924: d05c beq.n 80019e0 <HAL_RCC_OscConfig+0x464>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001926: 687b ldr r3, [r7, #4]
8001928: 699b ldr r3, [r3, #24]
800192a: 2b02 cmp r3, #2
800192c: d141 bne.n 80019b2 <HAL_RCC_OscConfig+0x436>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800192e: 4b31 ldr r3, [pc, #196] ; (80019f4 <HAL_RCC_OscConfig+0x478>)
8001930: 2200 movs r2, #0
8001932: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001934: f7ff fb34 bl 8000fa0 <HAL_GetTick>
8001938: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800193a: e008 b.n 800194e <HAL_RCC_OscConfig+0x3d2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
800193c: f7ff fb30 bl 8000fa0 <HAL_GetTick>
8001940: 4602 mov r2, r0
8001942: 693b ldr r3, [r7, #16]
8001944: 1ad3 subs r3, r2, r3
8001946: 2b02 cmp r3, #2
8001948: d901 bls.n 800194e <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
800194a: 2303 movs r3, #3
800194c: e087 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800194e: 4b27 ldr r3, [pc, #156] ; (80019ec <HAL_RCC_OscConfig+0x470>)
8001950: 681b ldr r3, [r3, #0]
8001952: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001956: 2b00 cmp r3, #0
8001958: d1f0 bne.n 800193c <HAL_RCC_OscConfig+0x3c0>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
800195a: 687b ldr r3, [r7, #4]
800195c: 69da ldr r2, [r3, #28]
800195e: 687b ldr r3, [r7, #4]
8001960: 6a1b ldr r3, [r3, #32]
8001962: 431a orrs r2, r3
8001964: 687b ldr r3, [r7, #4]
8001966: 6a5b ldr r3, [r3, #36] ; 0x24
8001968: 019b lsls r3, r3, #6
800196a: 431a orrs r2, r3
800196c: 687b ldr r3, [r7, #4]
800196e: 6a9b ldr r3, [r3, #40] ; 0x28
8001970: 085b lsrs r3, r3, #1
8001972: 3b01 subs r3, #1
8001974: 041b lsls r3, r3, #16
8001976: 431a orrs r2, r3
8001978: 687b ldr r3, [r7, #4]
800197a: 6adb ldr r3, [r3, #44] ; 0x2c
800197c: 061b lsls r3, r3, #24
800197e: 491b ldr r1, [pc, #108] ; (80019ec <HAL_RCC_OscConfig+0x470>)
8001980: 4313 orrs r3, r2
8001982: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001984: 4b1b ldr r3, [pc, #108] ; (80019f4 <HAL_RCC_OscConfig+0x478>)
8001986: 2201 movs r2, #1
8001988: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800198a: f7ff fb09 bl 8000fa0 <HAL_GetTick>
800198e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001990: e008 b.n 80019a4 <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001992: f7ff fb05 bl 8000fa0 <HAL_GetTick>
8001996: 4602 mov r2, r0
8001998: 693b ldr r3, [r7, #16]
800199a: 1ad3 subs r3, r2, r3
800199c: 2b02 cmp r3, #2
800199e: d901 bls.n 80019a4 <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
80019a0: 2303 movs r3, #3
80019a2: e05c b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80019a4: 4b11 ldr r3, [pc, #68] ; (80019ec <HAL_RCC_OscConfig+0x470>)
80019a6: 681b ldr r3, [r3, #0]
80019a8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80019ac: 2b00 cmp r3, #0
80019ae: d0f0 beq.n 8001992 <HAL_RCC_OscConfig+0x416>
80019b0: e054 b.n 8001a5c <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80019b2: 4b10 ldr r3, [pc, #64] ; (80019f4 <HAL_RCC_OscConfig+0x478>)
80019b4: 2200 movs r2, #0
80019b6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80019b8: f7ff faf2 bl 8000fa0 <HAL_GetTick>
80019bc: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80019be: e008 b.n 80019d2 <HAL_RCC_OscConfig+0x456>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80019c0: f7ff faee bl 8000fa0 <HAL_GetTick>
80019c4: 4602 mov r2, r0
80019c6: 693b ldr r3, [r7, #16]
80019c8: 1ad3 subs r3, r2, r3
80019ca: 2b02 cmp r3, #2
80019cc: d901 bls.n 80019d2 <HAL_RCC_OscConfig+0x456>
{
return HAL_TIMEOUT;
80019ce: 2303 movs r3, #3
80019d0: e045 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80019d2: 4b06 ldr r3, [pc, #24] ; (80019ec <HAL_RCC_OscConfig+0x470>)
80019d4: 681b ldr r3, [r3, #0]
80019d6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80019da: 2b00 cmp r3, #0
80019dc: d1f0 bne.n 80019c0 <HAL_RCC_OscConfig+0x444>
80019de: e03d b.n 8001a5c <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80019e0: 687b ldr r3, [r7, #4]
80019e2: 699b ldr r3, [r3, #24]
80019e4: 2b01 cmp r3, #1
80019e6: d107 bne.n 80019f8 <HAL_RCC_OscConfig+0x47c>
{
return HAL_ERROR;
80019e8: 2301 movs r3, #1
80019ea: e038 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
80019ec: 40023800 .word 0x40023800
80019f0: 40007000 .word 0x40007000
80019f4: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
80019f8: 4b1b ldr r3, [pc, #108] ; (8001a68 <HAL_RCC_OscConfig+0x4ec>)
80019fa: 685b ldr r3, [r3, #4]
80019fc: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80019fe: 687b ldr r3, [r7, #4]
8001a00: 699b ldr r3, [r3, #24]
8001a02: 2b01 cmp r3, #1
8001a04: d028 beq.n 8001a58 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001a06: 68fb ldr r3, [r7, #12]
8001a08: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8001a0c: 687b ldr r3, [r7, #4]
8001a0e: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001a10: 429a cmp r2, r3
8001a12: d121 bne.n 8001a58 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001a14: 68fb ldr r3, [r7, #12]
8001a16: f003 023f and.w r2, r3, #63 ; 0x3f
8001a1a: 687b ldr r3, [r7, #4]
8001a1c: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001a1e: 429a cmp r2, r3
8001a20: d11a bne.n 8001a58 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8001a22: 68fa ldr r2, [r7, #12]
8001a24: f647 73c0 movw r3, #32704 ; 0x7fc0
8001a28: 4013 ands r3, r2
8001a2a: 687a ldr r2, [r7, #4]
8001a2c: 6a52 ldr r2, [r2, #36] ; 0x24
8001a2e: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001a30: 4293 cmp r3, r2
8001a32: d111 bne.n 8001a58 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8001a34: 68fb ldr r3, [r7, #12]
8001a36: f403 3240 and.w r2, r3, #196608 ; 0x30000
8001a3a: 687b ldr r3, [r7, #4]
8001a3c: 6a9b ldr r3, [r3, #40] ; 0x28
8001a3e: 085b lsrs r3, r3, #1
8001a40: 3b01 subs r3, #1
8001a42: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8001a44: 429a cmp r2, r3
8001a46: d107 bne.n 8001a58 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8001a48: 68fb ldr r3, [r7, #12]
8001a4a: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8001a4e: 687b ldr r3, [r7, #4]
8001a50: 6adb ldr r3, [r3, #44] ; 0x2c
8001a52: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8001a54: 429a cmp r2, r3
8001a56: d001 beq.n 8001a5c <HAL_RCC_OscConfig+0x4e0>
#endif
{
return HAL_ERROR;
8001a58: 2301 movs r3, #1
8001a5a: e000 b.n 8001a5e <HAL_RCC_OscConfig+0x4e2>
}
}
}
}
return HAL_OK;
8001a5c: 2300 movs r3, #0
}
8001a5e: 4618 mov r0, r3
8001a60: 3718 adds r7, #24
8001a62: 46bd mov sp, r7
8001a64: bd80 pop {r7, pc}
8001a66: bf00 nop
8001a68: 40023800 .word 0x40023800
08001a6c <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001a6c: b580 push {r7, lr}
8001a6e: b084 sub sp, #16
8001a70: af00 add r7, sp, #0
8001a72: 6078 str r0, [r7, #4]
8001a74: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8001a76: 687b ldr r3, [r7, #4]
8001a78: 2b00 cmp r3, #0
8001a7a: d101 bne.n 8001a80 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001a7c: 2301 movs r3, #1
8001a7e: e0cc b.n 8001c1a <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8001a80: 4b68 ldr r3, [pc, #416] ; (8001c24 <HAL_RCC_ClockConfig+0x1b8>)
8001a82: 681b ldr r3, [r3, #0]
8001a84: f003 0307 and.w r3, r3, #7
8001a88: 683a ldr r2, [r7, #0]
8001a8a: 429a cmp r2, r3
8001a8c: d90c bls.n 8001aa8 <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001a8e: 4b65 ldr r3, [pc, #404] ; (8001c24 <HAL_RCC_ClockConfig+0x1b8>)
8001a90: 683a ldr r2, [r7, #0]
8001a92: b2d2 uxtb r2, r2
8001a94: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001a96: 4b63 ldr r3, [pc, #396] ; (8001c24 <HAL_RCC_ClockConfig+0x1b8>)
8001a98: 681b ldr r3, [r3, #0]
8001a9a: f003 0307 and.w r3, r3, #7
8001a9e: 683a ldr r2, [r7, #0]
8001aa0: 429a cmp r2, r3
8001aa2: d001 beq.n 8001aa8 <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
8001aa4: 2301 movs r3, #1
8001aa6: e0b8 b.n 8001c1a <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001aa8: 687b ldr r3, [r7, #4]
8001aaa: 681b ldr r3, [r3, #0]
8001aac: f003 0302 and.w r3, r3, #2
8001ab0: 2b00 cmp r3, #0
8001ab2: d020 beq.n 8001af6 <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001ab4: 687b ldr r3, [r7, #4]
8001ab6: 681b ldr r3, [r3, #0]
8001ab8: f003 0304 and.w r3, r3, #4
8001abc: 2b00 cmp r3, #0
8001abe: d005 beq.n 8001acc <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8001ac0: 4b59 ldr r3, [pc, #356] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001ac2: 689b ldr r3, [r3, #8]
8001ac4: 4a58 ldr r2, [pc, #352] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001ac6: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
8001aca: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001acc: 687b ldr r3, [r7, #4]
8001ace: 681b ldr r3, [r3, #0]
8001ad0: f003 0308 and.w r3, r3, #8
8001ad4: 2b00 cmp r3, #0
8001ad6: d005 beq.n 8001ae4 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8001ad8: 4b53 ldr r3, [pc, #332] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001ada: 689b ldr r3, [r3, #8]
8001adc: 4a52 ldr r2, [pc, #328] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001ade: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8001ae2: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001ae4: 4b50 ldr r3, [pc, #320] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001ae6: 689b ldr r3, [r3, #8]
8001ae8: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8001aec: 687b ldr r3, [r7, #4]
8001aee: 689b ldr r3, [r3, #8]
8001af0: 494d ldr r1, [pc, #308] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001af2: 4313 orrs r3, r2
8001af4: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001af6: 687b ldr r3, [r7, #4]
8001af8: 681b ldr r3, [r3, #0]
8001afa: f003 0301 and.w r3, r3, #1
8001afe: 2b00 cmp r3, #0
8001b00: d044 beq.n 8001b8c <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001b02: 687b ldr r3, [r7, #4]
8001b04: 685b ldr r3, [r3, #4]
8001b06: 2b01 cmp r3, #1
8001b08: d107 bne.n 8001b1a <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001b0a: 4b47 ldr r3, [pc, #284] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001b0c: 681b ldr r3, [r3, #0]
8001b0e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001b12: 2b00 cmp r3, #0
8001b14: d119 bne.n 8001b4a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001b16: 2301 movs r3, #1
8001b18: e07f b.n 8001c1a <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8001b1a: 687b ldr r3, [r7, #4]
8001b1c: 685b ldr r3, [r3, #4]
8001b1e: 2b02 cmp r3, #2
8001b20: d003 beq.n 8001b2a <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
8001b22: 687b ldr r3, [r7, #4]
8001b24: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8001b26: 2b03 cmp r3, #3
8001b28: d107 bne.n 8001b3a <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001b2a: 4b3f ldr r3, [pc, #252] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001b2c: 681b ldr r3, [r3, #0]
8001b2e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001b32: 2b00 cmp r3, #0
8001b34: d109 bne.n 8001b4a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001b36: 2301 movs r3, #1
8001b38: e06f b.n 8001c1a <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001b3a: 4b3b ldr r3, [pc, #236] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001b3c: 681b ldr r3, [r3, #0]
8001b3e: f003 0302 and.w r3, r3, #2
8001b42: 2b00 cmp r3, #0
8001b44: d101 bne.n 8001b4a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001b46: 2301 movs r3, #1
8001b48: e067 b.n 8001c1a <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8001b4a: 4b37 ldr r3, [pc, #220] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001b4c: 689b ldr r3, [r3, #8]
8001b4e: f023 0203 bic.w r2, r3, #3
8001b52: 687b ldr r3, [r7, #4]
8001b54: 685b ldr r3, [r3, #4]
8001b56: 4934 ldr r1, [pc, #208] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001b58: 4313 orrs r3, r2
8001b5a: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001b5c: f7ff fa20 bl 8000fa0 <HAL_GetTick>
8001b60: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001b62: e00a b.n 8001b7a <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001b64: f7ff fa1c bl 8000fa0 <HAL_GetTick>
8001b68: 4602 mov r2, r0
8001b6a: 68fb ldr r3, [r7, #12]
8001b6c: 1ad3 subs r3, r2, r3
8001b6e: f241 3288 movw r2, #5000 ; 0x1388
8001b72: 4293 cmp r3, r2
8001b74: d901 bls.n 8001b7a <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8001b76: 2303 movs r3, #3
8001b78: e04f b.n 8001c1a <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001b7a: 4b2b ldr r3, [pc, #172] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001b7c: 689b ldr r3, [r3, #8]
8001b7e: f003 020c and.w r2, r3, #12
8001b82: 687b ldr r3, [r7, #4]
8001b84: 685b ldr r3, [r3, #4]
8001b86: 009b lsls r3, r3, #2
8001b88: 429a cmp r2, r3
8001b8a: d1eb bne.n 8001b64 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001b8c: 4b25 ldr r3, [pc, #148] ; (8001c24 <HAL_RCC_ClockConfig+0x1b8>)
8001b8e: 681b ldr r3, [r3, #0]
8001b90: f003 0307 and.w r3, r3, #7
8001b94: 683a ldr r2, [r7, #0]
8001b96: 429a cmp r2, r3
8001b98: d20c bcs.n 8001bb4 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001b9a: 4b22 ldr r3, [pc, #136] ; (8001c24 <HAL_RCC_ClockConfig+0x1b8>)
8001b9c: 683a ldr r2, [r7, #0]
8001b9e: b2d2 uxtb r2, r2
8001ba0: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001ba2: 4b20 ldr r3, [pc, #128] ; (8001c24 <HAL_RCC_ClockConfig+0x1b8>)
8001ba4: 681b ldr r3, [r3, #0]
8001ba6: f003 0307 and.w r3, r3, #7
8001baa: 683a ldr r2, [r7, #0]
8001bac: 429a cmp r2, r3
8001bae: d001 beq.n 8001bb4 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
8001bb0: 2301 movs r3, #1
8001bb2: e032 b.n 8001c1a <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001bb4: 687b ldr r3, [r7, #4]
8001bb6: 681b ldr r3, [r3, #0]
8001bb8: f003 0304 and.w r3, r3, #4
8001bbc: 2b00 cmp r3, #0
8001bbe: d008 beq.n 8001bd2 <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001bc0: 4b19 ldr r3, [pc, #100] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001bc2: 689b ldr r3, [r3, #8]
8001bc4: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
8001bc8: 687b ldr r3, [r7, #4]
8001bca: 68db ldr r3, [r3, #12]
8001bcc: 4916 ldr r1, [pc, #88] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001bce: 4313 orrs r3, r2
8001bd0: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001bd2: 687b ldr r3, [r7, #4]
8001bd4: 681b ldr r3, [r3, #0]
8001bd6: f003 0308 and.w r3, r3, #8
8001bda: 2b00 cmp r3, #0
8001bdc: d009 beq.n 8001bf2 <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8001bde: 4b12 ldr r3, [pc, #72] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001be0: 689b ldr r3, [r3, #8]
8001be2: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8001be6: 687b ldr r3, [r7, #4]
8001be8: 691b ldr r3, [r3, #16]
8001bea: 00db lsls r3, r3, #3
8001bec: 490e ldr r1, [pc, #56] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001bee: 4313 orrs r3, r2
8001bf0: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8001bf2: f000 f821 bl 8001c38 <HAL_RCC_GetSysClockFreq>
8001bf6: 4602 mov r2, r0
8001bf8: 4b0b ldr r3, [pc, #44] ; (8001c28 <HAL_RCC_ClockConfig+0x1bc>)
8001bfa: 689b ldr r3, [r3, #8]
8001bfc: 091b lsrs r3, r3, #4
8001bfe: f003 030f and.w r3, r3, #15
8001c02: 490a ldr r1, [pc, #40] ; (8001c2c <HAL_RCC_ClockConfig+0x1c0>)
8001c04: 5ccb ldrb r3, [r1, r3]
8001c06: fa22 f303 lsr.w r3, r2, r3
8001c0a: 4a09 ldr r2, [pc, #36] ; (8001c30 <HAL_RCC_ClockConfig+0x1c4>)
8001c0c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
8001c0e: 4b09 ldr r3, [pc, #36] ; (8001c34 <HAL_RCC_ClockConfig+0x1c8>)
8001c10: 681b ldr r3, [r3, #0]
8001c12: 4618 mov r0, r3
8001c14: f7ff f980 bl 8000f18 <HAL_InitTick>
return HAL_OK;
8001c18: 2300 movs r3, #0
}
8001c1a: 4618 mov r0, r3
8001c1c: 3710 adds r7, #16
8001c1e: 46bd mov sp, r7
8001c20: bd80 pop {r7, pc}
8001c22: bf00 nop
8001c24: 40023c00 .word 0x40023c00
8001c28: 40023800 .word 0x40023800
8001c2c: 080032bc .word 0x080032bc
8001c30: 20000004 .word 0x20000004
8001c34: 20000008 .word 0x20000008
08001c38 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001c38: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001c3c: b090 sub sp, #64 ; 0x40
8001c3e: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
8001c40: 2300 movs r3, #0
8001c42: 637b str r3, [r7, #52] ; 0x34
8001c44: 2300 movs r3, #0
8001c46: 63fb str r3, [r7, #60] ; 0x3c
8001c48: 2300 movs r3, #0
8001c4a: 633b str r3, [r7, #48] ; 0x30
uint32_t sysclockfreq = 0U;
8001c4c: 2300 movs r3, #0
8001c4e: 63bb str r3, [r7, #56] ; 0x38
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8001c50: 4b59 ldr r3, [pc, #356] ; (8001db8 <HAL_RCC_GetSysClockFreq+0x180>)
8001c52: 689b ldr r3, [r3, #8]
8001c54: f003 030c and.w r3, r3, #12
8001c58: 2b08 cmp r3, #8
8001c5a: d00d beq.n 8001c78 <HAL_RCC_GetSysClockFreq+0x40>
8001c5c: 2b08 cmp r3, #8
8001c5e: f200 80a1 bhi.w 8001da4 <HAL_RCC_GetSysClockFreq+0x16c>
8001c62: 2b00 cmp r3, #0
8001c64: d002 beq.n 8001c6c <HAL_RCC_GetSysClockFreq+0x34>
8001c66: 2b04 cmp r3, #4
8001c68: d003 beq.n 8001c72 <HAL_RCC_GetSysClockFreq+0x3a>
8001c6a: e09b b.n 8001da4 <HAL_RCC_GetSysClockFreq+0x16c>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8001c6c: 4b53 ldr r3, [pc, #332] ; (8001dbc <HAL_RCC_GetSysClockFreq+0x184>)
8001c6e: 63bb str r3, [r7, #56] ; 0x38
break;
8001c70: e09b b.n 8001daa <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8001c72: 4b53 ldr r3, [pc, #332] ; (8001dc0 <HAL_RCC_GetSysClockFreq+0x188>)
8001c74: 63bb str r3, [r7, #56] ; 0x38
break;
8001c76: e098 b.n 8001daa <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8001c78: 4b4f ldr r3, [pc, #316] ; (8001db8 <HAL_RCC_GetSysClockFreq+0x180>)
8001c7a: 685b ldr r3, [r3, #4]
8001c7c: f003 033f and.w r3, r3, #63 ; 0x3f
8001c80: 637b str r3, [r7, #52] ; 0x34
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8001c82: 4b4d ldr r3, [pc, #308] ; (8001db8 <HAL_RCC_GetSysClockFreq+0x180>)
8001c84: 685b ldr r3, [r3, #4]
8001c86: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8001c8a: 2b00 cmp r3, #0
8001c8c: d028 beq.n 8001ce0 <HAL_RCC_GetSysClockFreq+0xa8>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8001c8e: 4b4a ldr r3, [pc, #296] ; (8001db8 <HAL_RCC_GetSysClockFreq+0x180>)
8001c90: 685b ldr r3, [r3, #4]
8001c92: 099b lsrs r3, r3, #6
8001c94: 2200 movs r2, #0
8001c96: 623b str r3, [r7, #32]
8001c98: 627a str r2, [r7, #36] ; 0x24
8001c9a: 6a3b ldr r3, [r7, #32]
8001c9c: f3c3 0008 ubfx r0, r3, #0, #9
8001ca0: 2100 movs r1, #0
8001ca2: 4b47 ldr r3, [pc, #284] ; (8001dc0 <HAL_RCC_GetSysClockFreq+0x188>)
8001ca4: fb03 f201 mul.w r2, r3, r1
8001ca8: 2300 movs r3, #0
8001caa: fb00 f303 mul.w r3, r0, r3
8001cae: 4413 add r3, r2
8001cb0: 4a43 ldr r2, [pc, #268] ; (8001dc0 <HAL_RCC_GetSysClockFreq+0x188>)
8001cb2: fba0 1202 umull r1, r2, r0, r2
8001cb6: 62fa str r2, [r7, #44] ; 0x2c
8001cb8: 460a mov r2, r1
8001cba: 62ba str r2, [r7, #40] ; 0x28
8001cbc: 6afa ldr r2, [r7, #44] ; 0x2c
8001cbe: 4413 add r3, r2
8001cc0: 62fb str r3, [r7, #44] ; 0x2c
8001cc2: 6b7b ldr r3, [r7, #52] ; 0x34
8001cc4: 2200 movs r2, #0
8001cc6: 61bb str r3, [r7, #24]
8001cc8: 61fa str r2, [r7, #28]
8001cca: e9d7 2306 ldrd r2, r3, [r7, #24]
8001cce: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28
8001cd2: f7fe fa79 bl 80001c8 <__aeabi_uldivmod>
8001cd6: 4602 mov r2, r0
8001cd8: 460b mov r3, r1
8001cda: 4613 mov r3, r2
8001cdc: 63fb str r3, [r7, #60] ; 0x3c
8001cde: e053 b.n 8001d88 <HAL_RCC_GetSysClockFreq+0x150>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8001ce0: 4b35 ldr r3, [pc, #212] ; (8001db8 <HAL_RCC_GetSysClockFreq+0x180>)
8001ce2: 685b ldr r3, [r3, #4]
8001ce4: 099b lsrs r3, r3, #6
8001ce6: 2200 movs r2, #0
8001ce8: 613b str r3, [r7, #16]
8001cea: 617a str r2, [r7, #20]
8001cec: 693b ldr r3, [r7, #16]
8001cee: f3c3 0a08 ubfx sl, r3, #0, #9
8001cf2: f04f 0b00 mov.w fp, #0
8001cf6: 4652 mov r2, sl
8001cf8: 465b mov r3, fp
8001cfa: f04f 0000 mov.w r0, #0
8001cfe: f04f 0100 mov.w r1, #0
8001d02: 0159 lsls r1, r3, #5
8001d04: ea41 61d2 orr.w r1, r1, r2, lsr #27
8001d08: 0150 lsls r0, r2, #5
8001d0a: 4602 mov r2, r0
8001d0c: 460b mov r3, r1
8001d0e: ebb2 080a subs.w r8, r2, sl
8001d12: eb63 090b sbc.w r9, r3, fp
8001d16: f04f 0200 mov.w r2, #0
8001d1a: f04f 0300 mov.w r3, #0
8001d1e: ea4f 1389 mov.w r3, r9, lsl #6
8001d22: ea43 6398 orr.w r3, r3, r8, lsr #26
8001d26: ea4f 1288 mov.w r2, r8, lsl #6
8001d2a: ebb2 0408 subs.w r4, r2, r8
8001d2e: eb63 0509 sbc.w r5, r3, r9
8001d32: f04f 0200 mov.w r2, #0
8001d36: f04f 0300 mov.w r3, #0
8001d3a: 00eb lsls r3, r5, #3
8001d3c: ea43 7354 orr.w r3, r3, r4, lsr #29
8001d40: 00e2 lsls r2, r4, #3
8001d42: 4614 mov r4, r2
8001d44: 461d mov r5, r3
8001d46: eb14 030a adds.w r3, r4, sl
8001d4a: 603b str r3, [r7, #0]
8001d4c: eb45 030b adc.w r3, r5, fp
8001d50: 607b str r3, [r7, #4]
8001d52: f04f 0200 mov.w r2, #0
8001d56: f04f 0300 mov.w r3, #0
8001d5a: e9d7 4500 ldrd r4, r5, [r7]
8001d5e: 4629 mov r1, r5
8001d60: 028b lsls r3, r1, #10
8001d62: 4621 mov r1, r4
8001d64: ea43 5391 orr.w r3, r3, r1, lsr #22
8001d68: 4621 mov r1, r4
8001d6a: 028a lsls r2, r1, #10
8001d6c: 4610 mov r0, r2
8001d6e: 4619 mov r1, r3
8001d70: 6b7b ldr r3, [r7, #52] ; 0x34
8001d72: 2200 movs r2, #0
8001d74: 60bb str r3, [r7, #8]
8001d76: 60fa str r2, [r7, #12]
8001d78: e9d7 2302 ldrd r2, r3, [r7, #8]
8001d7c: f7fe fa24 bl 80001c8 <__aeabi_uldivmod>
8001d80: 4602 mov r2, r0
8001d82: 460b mov r3, r1
8001d84: 4613 mov r3, r2
8001d86: 63fb str r3, [r7, #60] ; 0x3c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
8001d88: 4b0b ldr r3, [pc, #44] ; (8001db8 <HAL_RCC_GetSysClockFreq+0x180>)
8001d8a: 685b ldr r3, [r3, #4]
8001d8c: 0c1b lsrs r3, r3, #16
8001d8e: f003 0303 and.w r3, r3, #3
8001d92: 3301 adds r3, #1
8001d94: 005b lsls r3, r3, #1
8001d96: 633b str r3, [r7, #48] ; 0x30
sysclockfreq = pllvco/pllp;
8001d98: 6bfa ldr r2, [r7, #60] ; 0x3c
8001d9a: 6b3b ldr r3, [r7, #48] ; 0x30
8001d9c: fbb2 f3f3 udiv r3, r2, r3
8001da0: 63bb str r3, [r7, #56] ; 0x38
break;
8001da2: e002 b.n 8001daa <HAL_RCC_GetSysClockFreq+0x172>
}
default:
{
sysclockfreq = HSI_VALUE;
8001da4: 4b05 ldr r3, [pc, #20] ; (8001dbc <HAL_RCC_GetSysClockFreq+0x184>)
8001da6: 63bb str r3, [r7, #56] ; 0x38
break;
8001da8: bf00 nop
}
}
return sysclockfreq;
8001daa: 6bbb ldr r3, [r7, #56] ; 0x38
}
8001dac: 4618 mov r0, r3
8001dae: 3740 adds r7, #64 ; 0x40
8001db0: 46bd mov sp, r7
8001db2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8001db6: bf00 nop
8001db8: 40023800 .word 0x40023800
8001dbc: 00f42400 .word 0x00f42400
8001dc0: 016e3600 .word 0x016e3600
08001dc4 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8001dc4: b580 push {r7, lr}
8001dc6: b082 sub sp, #8
8001dc8: af00 add r7, sp, #0
8001dca: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
8001dcc: 687b ldr r3, [r7, #4]
8001dce: 2b00 cmp r3, #0
8001dd0: d101 bne.n 8001dd6 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8001dd2: 2301 movs r3, #1
8001dd4: e07b b.n 8001ece <HAL_SPI_Init+0x10a>
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
8001dd6: 687b ldr r3, [r7, #4]
8001dd8: 6a5b ldr r3, [r3, #36] ; 0x24
8001dda: 2b00 cmp r3, #0
8001ddc: d108 bne.n 8001df0 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
8001dde: 687b ldr r3, [r7, #4]
8001de0: 685b ldr r3, [r3, #4]
8001de2: f5b3 7f82 cmp.w r3, #260 ; 0x104
8001de6: d009 beq.n 8001dfc <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8001de8: 687b ldr r3, [r7, #4]
8001dea: 2200 movs r2, #0
8001dec: 61da str r2, [r3, #28]
8001dee: e005 b.n 8001dfc <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
8001df0: 687b ldr r3, [r7, #4]
8001df2: 2200 movs r2, #0
8001df4: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8001df6: 687b ldr r3, [r7, #4]
8001df8: 2200 movs r2, #0
8001dfa: 615a str r2, [r3, #20]
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8001dfc: 687b ldr r3, [r7, #4]
8001dfe: 2200 movs r2, #0
8001e00: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
8001e02: 687b ldr r3, [r7, #4]
8001e04: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
8001e08: b2db uxtb r3, r3
8001e0a: 2b00 cmp r3, #0
8001e0c: d106 bne.n 8001e1c <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8001e0e: 687b ldr r3, [r7, #4]
8001e10: 2200 movs r2, #0
8001e12: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8001e16: 6878 ldr r0, [r7, #4]
8001e18: f7fe fef6 bl 8000c08 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8001e1c: 687b ldr r3, [r7, #4]
8001e1e: 2202 movs r2, #2
8001e20: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8001e24: 687b ldr r3, [r7, #4]
8001e26: 681b ldr r3, [r3, #0]
8001e28: 681a ldr r2, [r3, #0]
8001e2a: 687b ldr r3, [r7, #4]
8001e2c: 681b ldr r3, [r3, #0]
8001e2e: f022 0240 bic.w r2, r2, #64 ; 0x40
8001e32: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
8001e34: 687b ldr r3, [r7, #4]
8001e36: 685b ldr r3, [r3, #4]
8001e38: f403 7282 and.w r2, r3, #260 ; 0x104
8001e3c: 687b ldr r3, [r7, #4]
8001e3e: 689b ldr r3, [r3, #8]
8001e40: f403 4304 and.w r3, r3, #33792 ; 0x8400
8001e44: 431a orrs r2, r3
8001e46: 687b ldr r3, [r7, #4]
8001e48: 68db ldr r3, [r3, #12]
8001e4a: f403 6300 and.w r3, r3, #2048 ; 0x800
8001e4e: 431a orrs r2, r3
8001e50: 687b ldr r3, [r7, #4]
8001e52: 691b ldr r3, [r3, #16]
8001e54: f003 0302 and.w r3, r3, #2
8001e58: 431a orrs r2, r3
8001e5a: 687b ldr r3, [r7, #4]
8001e5c: 695b ldr r3, [r3, #20]
8001e5e: f003 0301 and.w r3, r3, #1
8001e62: 431a orrs r2, r3
8001e64: 687b ldr r3, [r7, #4]
8001e66: 699b ldr r3, [r3, #24]
8001e68: f403 7300 and.w r3, r3, #512 ; 0x200
8001e6c: 431a orrs r2, r3
8001e6e: 687b ldr r3, [r7, #4]
8001e70: 69db ldr r3, [r3, #28]
8001e72: f003 0338 and.w r3, r3, #56 ; 0x38
8001e76: 431a orrs r2, r3
8001e78: 687b ldr r3, [r7, #4]
8001e7a: 6a1b ldr r3, [r3, #32]
8001e7c: f003 0380 and.w r3, r3, #128 ; 0x80
8001e80: ea42 0103 orr.w r1, r2, r3
8001e84: 687b ldr r3, [r7, #4]
8001e86: 6a9b ldr r3, [r3, #40] ; 0x28
8001e88: f403 5200 and.w r2, r3, #8192 ; 0x2000
8001e8c: 687b ldr r3, [r7, #4]
8001e8e: 681b ldr r3, [r3, #0]
8001e90: 430a orrs r2, r1
8001e92: 601a str r2, [r3, #0]
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
/* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
8001e94: 687b ldr r3, [r7, #4]
8001e96: 699b ldr r3, [r3, #24]
8001e98: 0c1b lsrs r3, r3, #16
8001e9a: f003 0104 and.w r1, r3, #4
8001e9e: 687b ldr r3, [r7, #4]
8001ea0: 6a5b ldr r3, [r3, #36] ; 0x24
8001ea2: f003 0210 and.w r2, r3, #16
8001ea6: 687b ldr r3, [r7, #4]
8001ea8: 681b ldr r3, [r3, #0]
8001eaa: 430a orrs r2, r1
8001eac: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8001eae: 687b ldr r3, [r7, #4]
8001eb0: 681b ldr r3, [r3, #0]
8001eb2: 69da ldr r2, [r3, #28]
8001eb4: 687b ldr r3, [r7, #4]
8001eb6: 681b ldr r3, [r3, #0]
8001eb8: f422 6200 bic.w r2, r2, #2048 ; 0x800
8001ebc: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8001ebe: 687b ldr r3, [r7, #4]
8001ec0: 2200 movs r2, #0
8001ec2: 655a str r2, [r3, #84] ; 0x54
hspi->State = HAL_SPI_STATE_READY;
8001ec4: 687b ldr r3, [r7, #4]
8001ec6: 2201 movs r2, #1
8001ec8: f883 2051 strb.w r2, [r3, #81] ; 0x51
return HAL_OK;
8001ecc: 2300 movs r3, #0
}
8001ece: 4618 mov r0, r3
8001ed0: 3708 adds r7, #8
8001ed2: 46bd mov sp, r7
8001ed4: bd80 pop {r7, pc}
08001ed6 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8001ed6: b580 push {r7, lr}
8001ed8: b082 sub sp, #8
8001eda: af00 add r7, sp, #0
8001edc: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001ede: 687b ldr r3, [r7, #4]
8001ee0: 2b00 cmp r3, #0
8001ee2: d101 bne.n 8001ee8 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8001ee4: 2301 movs r3, #1
8001ee6: e041 b.n 8001f6c <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8001ee8: 687b ldr r3, [r7, #4]
8001eea: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001eee: b2db uxtb r3, r3
8001ef0: 2b00 cmp r3, #0
8001ef2: d106 bne.n 8001f02 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8001ef4: 687b ldr r3, [r7, #4]
8001ef6: 2200 movs r2, #0
8001ef8: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8001efc: 6878 ldr r0, [r7, #4]
8001efe: f7fe fecb bl 8000c98 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001f02: 687b ldr r3, [r7, #4]
8001f04: 2202 movs r2, #2
8001f06: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8001f0a: 687b ldr r3, [r7, #4]
8001f0c: 681a ldr r2, [r3, #0]
8001f0e: 687b ldr r3, [r7, #4]
8001f10: 3304 adds r3, #4
8001f12: 4619 mov r1, r3
8001f14: 4610 mov r0, r2
8001f16: f000 fda7 bl 8002a68 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8001f1a: 687b ldr r3, [r7, #4]
8001f1c: 2201 movs r2, #1
8001f1e: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001f22: 687b ldr r3, [r7, #4]
8001f24: 2201 movs r2, #1
8001f26: f883 203e strb.w r2, [r3, #62] ; 0x3e
8001f2a: 687b ldr r3, [r7, #4]
8001f2c: 2201 movs r2, #1
8001f2e: f883 203f strb.w r2, [r3, #63] ; 0x3f
8001f32: 687b ldr r3, [r7, #4]
8001f34: 2201 movs r2, #1
8001f36: f883 2040 strb.w r2, [r3, #64] ; 0x40
8001f3a: 687b ldr r3, [r7, #4]
8001f3c: 2201 movs r2, #1
8001f3e: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001f42: 687b ldr r3, [r7, #4]
8001f44: 2201 movs r2, #1
8001f46: f883 2042 strb.w r2, [r3, #66] ; 0x42
8001f4a: 687b ldr r3, [r7, #4]
8001f4c: 2201 movs r2, #1
8001f4e: f883 2043 strb.w r2, [r3, #67] ; 0x43
8001f52: 687b ldr r3, [r7, #4]
8001f54: 2201 movs r2, #1
8001f56: f883 2044 strb.w r2, [r3, #68] ; 0x44
8001f5a: 687b ldr r3, [r7, #4]
8001f5c: 2201 movs r2, #1
8001f5e: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8001f62: 687b ldr r3, [r7, #4]
8001f64: 2201 movs r2, #1
8001f66: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001f6a: 2300 movs r3, #0
}
8001f6c: 4618 mov r0, r3
8001f6e: 3708 adds r7, #8
8001f70: 46bd mov sp, r7
8001f72: bd80 pop {r7, pc}
08001f74 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8001f74: b480 push {r7}
8001f76: b085 sub sp, #20
8001f78: af00 add r7, sp, #0
8001f7a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8001f7c: 687b ldr r3, [r7, #4]
8001f7e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001f82: b2db uxtb r3, r3
8001f84: 2b01 cmp r3, #1
8001f86: d001 beq.n 8001f8c <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8001f88: 2301 movs r3, #1
8001f8a: e04e b.n 800202a <HAL_TIM_Base_Start_IT+0xb6>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001f8c: 687b ldr r3, [r7, #4]
8001f8e: 2202 movs r2, #2
8001f90: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8001f94: 687b ldr r3, [r7, #4]
8001f96: 681b ldr r3, [r3, #0]
8001f98: 68da ldr r2, [r3, #12]
8001f9a: 687b ldr r3, [r7, #4]
8001f9c: 681b ldr r3, [r3, #0]
8001f9e: f042 0201 orr.w r2, r2, #1
8001fa2: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8001fa4: 687b ldr r3, [r7, #4]
8001fa6: 681b ldr r3, [r3, #0]
8001fa8: 4a23 ldr r2, [pc, #140] ; (8002038 <HAL_TIM_Base_Start_IT+0xc4>)
8001faa: 4293 cmp r3, r2
8001fac: d022 beq.n 8001ff4 <HAL_TIM_Base_Start_IT+0x80>
8001fae: 687b ldr r3, [r7, #4]
8001fb0: 681b ldr r3, [r3, #0]
8001fb2: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001fb6: d01d beq.n 8001ff4 <HAL_TIM_Base_Start_IT+0x80>
8001fb8: 687b ldr r3, [r7, #4]
8001fba: 681b ldr r3, [r3, #0]
8001fbc: 4a1f ldr r2, [pc, #124] ; (800203c <HAL_TIM_Base_Start_IT+0xc8>)
8001fbe: 4293 cmp r3, r2
8001fc0: d018 beq.n 8001ff4 <HAL_TIM_Base_Start_IT+0x80>
8001fc2: 687b ldr r3, [r7, #4]
8001fc4: 681b ldr r3, [r3, #0]
8001fc6: 4a1e ldr r2, [pc, #120] ; (8002040 <HAL_TIM_Base_Start_IT+0xcc>)
8001fc8: 4293 cmp r3, r2
8001fca: d013 beq.n 8001ff4 <HAL_TIM_Base_Start_IT+0x80>
8001fcc: 687b ldr r3, [r7, #4]
8001fce: 681b ldr r3, [r3, #0]
8001fd0: 4a1c ldr r2, [pc, #112] ; (8002044 <HAL_TIM_Base_Start_IT+0xd0>)
8001fd2: 4293 cmp r3, r2
8001fd4: d00e beq.n 8001ff4 <HAL_TIM_Base_Start_IT+0x80>
8001fd6: 687b ldr r3, [r7, #4]
8001fd8: 681b ldr r3, [r3, #0]
8001fda: 4a1b ldr r2, [pc, #108] ; (8002048 <HAL_TIM_Base_Start_IT+0xd4>)
8001fdc: 4293 cmp r3, r2
8001fde: d009 beq.n 8001ff4 <HAL_TIM_Base_Start_IT+0x80>
8001fe0: 687b ldr r3, [r7, #4]
8001fe2: 681b ldr r3, [r3, #0]
8001fe4: 4a19 ldr r2, [pc, #100] ; (800204c <HAL_TIM_Base_Start_IT+0xd8>)
8001fe6: 4293 cmp r3, r2
8001fe8: d004 beq.n 8001ff4 <HAL_TIM_Base_Start_IT+0x80>
8001fea: 687b ldr r3, [r7, #4]
8001fec: 681b ldr r3, [r3, #0]
8001fee: 4a18 ldr r2, [pc, #96] ; (8002050 <HAL_TIM_Base_Start_IT+0xdc>)
8001ff0: 4293 cmp r3, r2
8001ff2: d111 bne.n 8002018 <HAL_TIM_Base_Start_IT+0xa4>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8001ff4: 687b ldr r3, [r7, #4]
8001ff6: 681b ldr r3, [r3, #0]
8001ff8: 689b ldr r3, [r3, #8]
8001ffa: f003 0307 and.w r3, r3, #7
8001ffe: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002000: 68fb ldr r3, [r7, #12]
8002002: 2b06 cmp r3, #6
8002004: d010 beq.n 8002028 <HAL_TIM_Base_Start_IT+0xb4>
{
__HAL_TIM_ENABLE(htim);
8002006: 687b ldr r3, [r7, #4]
8002008: 681b ldr r3, [r3, #0]
800200a: 681a ldr r2, [r3, #0]
800200c: 687b ldr r3, [r7, #4]
800200e: 681b ldr r3, [r3, #0]
8002010: f042 0201 orr.w r2, r2, #1
8002014: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002016: e007 b.n 8002028 <HAL_TIM_Base_Start_IT+0xb4>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8002018: 687b ldr r3, [r7, #4]
800201a: 681b ldr r3, [r3, #0]
800201c: 681a ldr r2, [r3, #0]
800201e: 687b ldr r3, [r7, #4]
8002020: 681b ldr r3, [r3, #0]
8002022: f042 0201 orr.w r2, r2, #1
8002026: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8002028: 2300 movs r3, #0
}
800202a: 4618 mov r0, r3
800202c: 3714 adds r7, #20
800202e: 46bd mov sp, r7
8002030: f85d 7b04 ldr.w r7, [sp], #4
8002034: 4770 bx lr
8002036: bf00 nop
8002038: 40010000 .word 0x40010000
800203c: 40000400 .word 0x40000400
8002040: 40000800 .word 0x40000800
8002044: 40000c00 .word 0x40000c00
8002048: 40010400 .word 0x40010400
800204c: 40014000 .word 0x40014000
8002050: 40001800 .word 0x40001800
08002054 <HAL_TIM_OC_Init>:
* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
* @param htim TIM Output Compare handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
{
8002054: b580 push {r7, lr}
8002056: b082 sub sp, #8
8002058: af00 add r7, sp, #0
800205a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800205c: 687b ldr r3, [r7, #4]
800205e: 2b00 cmp r3, #0
8002060: d101 bne.n 8002066 <HAL_TIM_OC_Init+0x12>
{
return HAL_ERROR;
8002062: 2301 movs r3, #1
8002064: e041 b.n 80020ea <HAL_TIM_OC_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002066: 687b ldr r3, [r7, #4]
8002068: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
800206c: b2db uxtb r3, r3
800206e: 2b00 cmp r3, #0
8002070: d106 bne.n 8002080 <HAL_TIM_OC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002072: 687b ldr r3, [r7, #4]
8002074: 2200 movs r2, #0
8002076: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->OC_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
800207a: 6878 ldr r0, [r7, #4]
800207c: f000 f839 bl 80020f2 <HAL_TIM_OC_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002080: 687b ldr r3, [r7, #4]
8002082: 2202 movs r2, #2
8002084: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002088: 687b ldr r3, [r7, #4]
800208a: 681a ldr r2, [r3, #0]
800208c: 687b ldr r3, [r7, #4]
800208e: 3304 adds r3, #4
8002090: 4619 mov r1, r3
8002092: 4610 mov r0, r2
8002094: f000 fce8 bl 8002a68 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002098: 687b ldr r3, [r7, #4]
800209a: 2201 movs r2, #1
800209c: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80020a0: 687b ldr r3, [r7, #4]
80020a2: 2201 movs r2, #1
80020a4: f883 203e strb.w r2, [r3, #62] ; 0x3e
80020a8: 687b ldr r3, [r7, #4]
80020aa: 2201 movs r2, #1
80020ac: f883 203f strb.w r2, [r3, #63] ; 0x3f
80020b0: 687b ldr r3, [r7, #4]
80020b2: 2201 movs r2, #1
80020b4: f883 2040 strb.w r2, [r3, #64] ; 0x40
80020b8: 687b ldr r3, [r7, #4]
80020ba: 2201 movs r2, #1
80020bc: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80020c0: 687b ldr r3, [r7, #4]
80020c2: 2201 movs r2, #1
80020c4: f883 2042 strb.w r2, [r3, #66] ; 0x42
80020c8: 687b ldr r3, [r7, #4]
80020ca: 2201 movs r2, #1
80020cc: f883 2043 strb.w r2, [r3, #67] ; 0x43
80020d0: 687b ldr r3, [r7, #4]
80020d2: 2201 movs r2, #1
80020d4: f883 2044 strb.w r2, [r3, #68] ; 0x44
80020d8: 687b ldr r3, [r7, #4]
80020da: 2201 movs r2, #1
80020dc: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80020e0: 687b ldr r3, [r7, #4]
80020e2: 2201 movs r2, #1
80020e4: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
80020e8: 2300 movs r3, #0
}
80020ea: 4618 mov r0, r3
80020ec: 3708 adds r7, #8
80020ee: 46bd mov sp, r7
80020f0: bd80 pop {r7, pc}
080020f2 <HAL_TIM_OC_MspInit>:
* @brief Initializes the TIM Output Compare MSP.
* @param htim TIM Output Compare handle
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
{
80020f2: b480 push {r7}
80020f4: b083 sub sp, #12
80020f6: af00 add r7, sp, #0
80020f8: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_MspInit could be implemented in the user file
*/
}
80020fa: bf00 nop
80020fc: 370c adds r7, #12
80020fe: 46bd mov sp, r7
8002100: f85d 7b04 ldr.w r7, [sp], #4
8002104: 4770 bx lr
08002106 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8002106: b580 push {r7, lr}
8002108: b082 sub sp, #8
800210a: af00 add r7, sp, #0
800210c: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800210e: 687b ldr r3, [r7, #4]
8002110: 2b00 cmp r3, #0
8002112: d101 bne.n 8002118 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8002114: 2301 movs r3, #1
8002116: e041 b.n 800219c <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002118: 687b ldr r3, [r7, #4]
800211a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
800211e: b2db uxtb r3, r3
8002120: 2b00 cmp r3, #0
8002122: d106 bne.n 8002132 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002124: 687b ldr r3, [r7, #4]
8002126: 2200 movs r2, #0
8002128: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
800212c: 6878 ldr r0, [r7, #4]
800212e: f000 f839 bl 80021a4 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002132: 687b ldr r3, [r7, #4]
8002134: 2202 movs r2, #2
8002136: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800213a: 687b ldr r3, [r7, #4]
800213c: 681a ldr r2, [r3, #0]
800213e: 687b ldr r3, [r7, #4]
8002140: 3304 adds r3, #4
8002142: 4619 mov r1, r3
8002144: 4610 mov r0, r2
8002146: f000 fc8f bl 8002a68 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800214a: 687b ldr r3, [r7, #4]
800214c: 2201 movs r2, #1
800214e: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002152: 687b ldr r3, [r7, #4]
8002154: 2201 movs r2, #1
8002156: f883 203e strb.w r2, [r3, #62] ; 0x3e
800215a: 687b ldr r3, [r7, #4]
800215c: 2201 movs r2, #1
800215e: f883 203f strb.w r2, [r3, #63] ; 0x3f
8002162: 687b ldr r3, [r7, #4]
8002164: 2201 movs r2, #1
8002166: f883 2040 strb.w r2, [r3, #64] ; 0x40
800216a: 687b ldr r3, [r7, #4]
800216c: 2201 movs r2, #1
800216e: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002172: 687b ldr r3, [r7, #4]
8002174: 2201 movs r2, #1
8002176: f883 2042 strb.w r2, [r3, #66] ; 0x42
800217a: 687b ldr r3, [r7, #4]
800217c: 2201 movs r2, #1
800217e: f883 2043 strb.w r2, [r3, #67] ; 0x43
8002182: 687b ldr r3, [r7, #4]
8002184: 2201 movs r2, #1
8002186: f883 2044 strb.w r2, [r3, #68] ; 0x44
800218a: 687b ldr r3, [r7, #4]
800218c: 2201 movs r2, #1
800218e: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002192: 687b ldr r3, [r7, #4]
8002194: 2201 movs r2, #1
8002196: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
800219a: 2300 movs r3, #0
}
800219c: 4618 mov r0, r3
800219e: 3708 adds r7, #8
80021a0: 46bd mov sp, r7
80021a2: bd80 pop {r7, pc}
080021a4 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
80021a4: b480 push {r7}
80021a6: b083 sub sp, #12
80021a8: af00 add r7, sp, #0
80021aa: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
80021ac: bf00 nop
80021ae: 370c adds r7, #12
80021b0: 46bd mov sp, r7
80021b2: f85d 7b04 ldr.w r7, [sp], #4
80021b6: 4770 bx lr
080021b8 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
80021b8: b580 push {r7, lr}
80021ba: b084 sub sp, #16
80021bc: af00 add r7, sp, #0
80021be: 6078 str r0, [r7, #4]
80021c0: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
80021c2: 683b ldr r3, [r7, #0]
80021c4: 2b00 cmp r3, #0
80021c6: d109 bne.n 80021dc <HAL_TIM_PWM_Start+0x24>
80021c8: 687b ldr r3, [r7, #4]
80021ca: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
80021ce: b2db uxtb r3, r3
80021d0: 2b01 cmp r3, #1
80021d2: bf14 ite ne
80021d4: 2301 movne r3, #1
80021d6: 2300 moveq r3, #0
80021d8: b2db uxtb r3, r3
80021da: e022 b.n 8002222 <HAL_TIM_PWM_Start+0x6a>
80021dc: 683b ldr r3, [r7, #0]
80021de: 2b04 cmp r3, #4
80021e0: d109 bne.n 80021f6 <HAL_TIM_PWM_Start+0x3e>
80021e2: 687b ldr r3, [r7, #4]
80021e4: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
80021e8: b2db uxtb r3, r3
80021ea: 2b01 cmp r3, #1
80021ec: bf14 ite ne
80021ee: 2301 movne r3, #1
80021f0: 2300 moveq r3, #0
80021f2: b2db uxtb r3, r3
80021f4: e015 b.n 8002222 <HAL_TIM_PWM_Start+0x6a>
80021f6: 683b ldr r3, [r7, #0]
80021f8: 2b08 cmp r3, #8
80021fa: d109 bne.n 8002210 <HAL_TIM_PWM_Start+0x58>
80021fc: 687b ldr r3, [r7, #4]
80021fe: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
8002202: b2db uxtb r3, r3
8002204: 2b01 cmp r3, #1
8002206: bf14 ite ne
8002208: 2301 movne r3, #1
800220a: 2300 moveq r3, #0
800220c: b2db uxtb r3, r3
800220e: e008 b.n 8002222 <HAL_TIM_PWM_Start+0x6a>
8002210: 687b ldr r3, [r7, #4]
8002212: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8002216: b2db uxtb r3, r3
8002218: 2b01 cmp r3, #1
800221a: bf14 ite ne
800221c: 2301 movne r3, #1
800221e: 2300 moveq r3, #0
8002220: b2db uxtb r3, r3
8002222: 2b00 cmp r3, #0
8002224: d001 beq.n 800222a <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
8002226: 2301 movs r3, #1
8002228: e07c b.n 8002324 <HAL_TIM_PWM_Start+0x16c>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
800222a: 683b ldr r3, [r7, #0]
800222c: 2b00 cmp r3, #0
800222e: d104 bne.n 800223a <HAL_TIM_PWM_Start+0x82>
8002230: 687b ldr r3, [r7, #4]
8002232: 2202 movs r2, #2
8002234: f883 203e strb.w r2, [r3, #62] ; 0x3e
8002238: e013 b.n 8002262 <HAL_TIM_PWM_Start+0xaa>
800223a: 683b ldr r3, [r7, #0]
800223c: 2b04 cmp r3, #4
800223e: d104 bne.n 800224a <HAL_TIM_PWM_Start+0x92>
8002240: 687b ldr r3, [r7, #4]
8002242: 2202 movs r2, #2
8002244: f883 203f strb.w r2, [r3, #63] ; 0x3f
8002248: e00b b.n 8002262 <HAL_TIM_PWM_Start+0xaa>
800224a: 683b ldr r3, [r7, #0]
800224c: 2b08 cmp r3, #8
800224e: d104 bne.n 800225a <HAL_TIM_PWM_Start+0xa2>
8002250: 687b ldr r3, [r7, #4]
8002252: 2202 movs r2, #2
8002254: f883 2040 strb.w r2, [r3, #64] ; 0x40
8002258: e003 b.n 8002262 <HAL_TIM_PWM_Start+0xaa>
800225a: 687b ldr r3, [r7, #4]
800225c: 2202 movs r2, #2
800225e: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
8002262: 687b ldr r3, [r7, #4]
8002264: 681b ldr r3, [r3, #0]
8002266: 2201 movs r2, #1
8002268: 6839 ldr r1, [r7, #0]
800226a: 4618 mov r0, r3
800226c: f000 fee6 bl 800303c <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8002270: 687b ldr r3, [r7, #4]
8002272: 681b ldr r3, [r3, #0]
8002274: 4a2d ldr r2, [pc, #180] ; (800232c <HAL_TIM_PWM_Start+0x174>)
8002276: 4293 cmp r3, r2
8002278: d004 beq.n 8002284 <HAL_TIM_PWM_Start+0xcc>
800227a: 687b ldr r3, [r7, #4]
800227c: 681b ldr r3, [r3, #0]
800227e: 4a2c ldr r2, [pc, #176] ; (8002330 <HAL_TIM_PWM_Start+0x178>)
8002280: 4293 cmp r3, r2
8002282: d101 bne.n 8002288 <HAL_TIM_PWM_Start+0xd0>
8002284: 2301 movs r3, #1
8002286: e000 b.n 800228a <HAL_TIM_PWM_Start+0xd2>
8002288: 2300 movs r3, #0
800228a: 2b00 cmp r3, #0
800228c: d007 beq.n 800229e <HAL_TIM_PWM_Start+0xe6>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
800228e: 687b ldr r3, [r7, #4]
8002290: 681b ldr r3, [r3, #0]
8002292: 6c5a ldr r2, [r3, #68] ; 0x44
8002294: 687b ldr r3, [r7, #4]
8002296: 681b ldr r3, [r3, #0]
8002298: f442 4200 orr.w r2, r2, #32768 ; 0x8000
800229c: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800229e: 687b ldr r3, [r7, #4]
80022a0: 681b ldr r3, [r3, #0]
80022a2: 4a22 ldr r2, [pc, #136] ; (800232c <HAL_TIM_PWM_Start+0x174>)
80022a4: 4293 cmp r3, r2
80022a6: d022 beq.n 80022ee <HAL_TIM_PWM_Start+0x136>
80022a8: 687b ldr r3, [r7, #4]
80022aa: 681b ldr r3, [r3, #0]
80022ac: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80022b0: d01d beq.n 80022ee <HAL_TIM_PWM_Start+0x136>
80022b2: 687b ldr r3, [r7, #4]
80022b4: 681b ldr r3, [r3, #0]
80022b6: 4a1f ldr r2, [pc, #124] ; (8002334 <HAL_TIM_PWM_Start+0x17c>)
80022b8: 4293 cmp r3, r2
80022ba: d018 beq.n 80022ee <HAL_TIM_PWM_Start+0x136>
80022bc: 687b ldr r3, [r7, #4]
80022be: 681b ldr r3, [r3, #0]
80022c0: 4a1d ldr r2, [pc, #116] ; (8002338 <HAL_TIM_PWM_Start+0x180>)
80022c2: 4293 cmp r3, r2
80022c4: d013 beq.n 80022ee <HAL_TIM_PWM_Start+0x136>
80022c6: 687b ldr r3, [r7, #4]
80022c8: 681b ldr r3, [r3, #0]
80022ca: 4a1c ldr r2, [pc, #112] ; (800233c <HAL_TIM_PWM_Start+0x184>)
80022cc: 4293 cmp r3, r2
80022ce: d00e beq.n 80022ee <HAL_TIM_PWM_Start+0x136>
80022d0: 687b ldr r3, [r7, #4]
80022d2: 681b ldr r3, [r3, #0]
80022d4: 4a16 ldr r2, [pc, #88] ; (8002330 <HAL_TIM_PWM_Start+0x178>)
80022d6: 4293 cmp r3, r2
80022d8: d009 beq.n 80022ee <HAL_TIM_PWM_Start+0x136>
80022da: 687b ldr r3, [r7, #4]
80022dc: 681b ldr r3, [r3, #0]
80022de: 4a18 ldr r2, [pc, #96] ; (8002340 <HAL_TIM_PWM_Start+0x188>)
80022e0: 4293 cmp r3, r2
80022e2: d004 beq.n 80022ee <HAL_TIM_PWM_Start+0x136>
80022e4: 687b ldr r3, [r7, #4]
80022e6: 681b ldr r3, [r3, #0]
80022e8: 4a16 ldr r2, [pc, #88] ; (8002344 <HAL_TIM_PWM_Start+0x18c>)
80022ea: 4293 cmp r3, r2
80022ec: d111 bne.n 8002312 <HAL_TIM_PWM_Start+0x15a>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80022ee: 687b ldr r3, [r7, #4]
80022f0: 681b ldr r3, [r3, #0]
80022f2: 689b ldr r3, [r3, #8]
80022f4: f003 0307 and.w r3, r3, #7
80022f8: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80022fa: 68fb ldr r3, [r7, #12]
80022fc: 2b06 cmp r3, #6
80022fe: d010 beq.n 8002322 <HAL_TIM_PWM_Start+0x16a>
{
__HAL_TIM_ENABLE(htim);
8002300: 687b ldr r3, [r7, #4]
8002302: 681b ldr r3, [r3, #0]
8002304: 681a ldr r2, [r3, #0]
8002306: 687b ldr r3, [r7, #4]
8002308: 681b ldr r3, [r3, #0]
800230a: f042 0201 orr.w r2, r2, #1
800230e: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002310: e007 b.n 8002322 <HAL_TIM_PWM_Start+0x16a>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8002312: 687b ldr r3, [r7, #4]
8002314: 681b ldr r3, [r3, #0]
8002316: 681a ldr r2, [r3, #0]
8002318: 687b ldr r3, [r7, #4]
800231a: 681b ldr r3, [r3, #0]
800231c: f042 0201 orr.w r2, r2, #1
8002320: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8002322: 2300 movs r3, #0
}
8002324: 4618 mov r0, r3
8002326: 3710 adds r7, #16
8002328: 46bd mov sp, r7
800232a: bd80 pop {r7, pc}
800232c: 40010000 .word 0x40010000
8002330: 40010400 .word 0x40010400
8002334: 40000400 .word 0x40000400
8002338: 40000800 .word 0x40000800
800233c: 40000c00 .word 0x40000c00
8002340: 40014000 .word 0x40014000
8002344: 40001800 .word 0x40001800
08002348 <HAL_TIM_PWM_Stop>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8002348: b580 push {r7, lr}
800234a: b082 sub sp, #8
800234c: af00 add r7, sp, #0
800234e: 6078 str r0, [r7, #4]
8002350: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
8002352: 687b ldr r3, [r7, #4]
8002354: 681b ldr r3, [r3, #0]
8002356: 2200 movs r2, #0
8002358: 6839 ldr r1, [r7, #0]
800235a: 4618 mov r0, r3
800235c: f000 fe6e bl 800303c <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8002360: 687b ldr r3, [r7, #4]
8002362: 681b ldr r3, [r3, #0]
8002364: 4a2e ldr r2, [pc, #184] ; (8002420 <HAL_TIM_PWM_Stop+0xd8>)
8002366: 4293 cmp r3, r2
8002368: d004 beq.n 8002374 <HAL_TIM_PWM_Stop+0x2c>
800236a: 687b ldr r3, [r7, #4]
800236c: 681b ldr r3, [r3, #0]
800236e: 4a2d ldr r2, [pc, #180] ; (8002424 <HAL_TIM_PWM_Stop+0xdc>)
8002370: 4293 cmp r3, r2
8002372: d101 bne.n 8002378 <HAL_TIM_PWM_Stop+0x30>
8002374: 2301 movs r3, #1
8002376: e000 b.n 800237a <HAL_TIM_PWM_Stop+0x32>
8002378: 2300 movs r3, #0
800237a: 2b00 cmp r3, #0
800237c: d017 beq.n 80023ae <HAL_TIM_PWM_Stop+0x66>
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
800237e: 687b ldr r3, [r7, #4]
8002380: 681b ldr r3, [r3, #0]
8002382: 6a1a ldr r2, [r3, #32]
8002384: f241 1311 movw r3, #4369 ; 0x1111
8002388: 4013 ands r3, r2
800238a: 2b00 cmp r3, #0
800238c: d10f bne.n 80023ae <HAL_TIM_PWM_Stop+0x66>
800238e: 687b ldr r3, [r7, #4]
8002390: 681b ldr r3, [r3, #0]
8002392: 6a1a ldr r2, [r3, #32]
8002394: f240 4344 movw r3, #1092 ; 0x444
8002398: 4013 ands r3, r2
800239a: 2b00 cmp r3, #0
800239c: d107 bne.n 80023ae <HAL_TIM_PWM_Stop+0x66>
800239e: 687b ldr r3, [r7, #4]
80023a0: 681b ldr r3, [r3, #0]
80023a2: 6c5a ldr r2, [r3, #68] ; 0x44
80023a4: 687b ldr r3, [r7, #4]
80023a6: 681b ldr r3, [r3, #0]
80023a8: f422 4200 bic.w r2, r2, #32768 ; 0x8000
80023ac: 645a str r2, [r3, #68] ; 0x44
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
80023ae: 687b ldr r3, [r7, #4]
80023b0: 681b ldr r3, [r3, #0]
80023b2: 6a1a ldr r2, [r3, #32]
80023b4: f241 1311 movw r3, #4369 ; 0x1111
80023b8: 4013 ands r3, r2
80023ba: 2b00 cmp r3, #0
80023bc: d10f bne.n 80023de <HAL_TIM_PWM_Stop+0x96>
80023be: 687b ldr r3, [r7, #4]
80023c0: 681b ldr r3, [r3, #0]
80023c2: 6a1a ldr r2, [r3, #32]
80023c4: f240 4344 movw r3, #1092 ; 0x444
80023c8: 4013 ands r3, r2
80023ca: 2b00 cmp r3, #0
80023cc: d107 bne.n 80023de <HAL_TIM_PWM_Stop+0x96>
80023ce: 687b ldr r3, [r7, #4]
80023d0: 681b ldr r3, [r3, #0]
80023d2: 681a ldr r2, [r3, #0]
80023d4: 687b ldr r3, [r7, #4]
80023d6: 681b ldr r3, [r3, #0]
80023d8: f022 0201 bic.w r2, r2, #1
80023dc: 601a str r2, [r3, #0]
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
80023de: 683b ldr r3, [r7, #0]
80023e0: 2b00 cmp r3, #0
80023e2: d104 bne.n 80023ee <HAL_TIM_PWM_Stop+0xa6>
80023e4: 687b ldr r3, [r7, #4]
80023e6: 2201 movs r2, #1
80023e8: f883 203e strb.w r2, [r3, #62] ; 0x3e
80023ec: e013 b.n 8002416 <HAL_TIM_PWM_Stop+0xce>
80023ee: 683b ldr r3, [r7, #0]
80023f0: 2b04 cmp r3, #4
80023f2: d104 bne.n 80023fe <HAL_TIM_PWM_Stop+0xb6>
80023f4: 687b ldr r3, [r7, #4]
80023f6: 2201 movs r2, #1
80023f8: f883 203f strb.w r2, [r3, #63] ; 0x3f
80023fc: e00b b.n 8002416 <HAL_TIM_PWM_Stop+0xce>
80023fe: 683b ldr r3, [r7, #0]
8002400: 2b08 cmp r3, #8
8002402: d104 bne.n 800240e <HAL_TIM_PWM_Stop+0xc6>
8002404: 687b ldr r3, [r7, #4]
8002406: 2201 movs r2, #1
8002408: f883 2040 strb.w r2, [r3, #64] ; 0x40
800240c: e003 b.n 8002416 <HAL_TIM_PWM_Stop+0xce>
800240e: 687b ldr r3, [r7, #4]
8002410: 2201 movs r2, #1
8002412: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Return function status */
return HAL_OK;
8002416: 2300 movs r3, #0
}
8002418: 4618 mov r0, r3
800241a: 3708 adds r7, #8
800241c: 46bd mov sp, r7
800241e: bd80 pop {r7, pc}
8002420: 40010000 .word 0x40010000
8002424: 40010400 .word 0x40010400
08002428 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8002428: b580 push {r7, lr}
800242a: b082 sub sp, #8
800242c: af00 add r7, sp, #0
800242e: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8002430: 687b ldr r3, [r7, #4]
8002432: 681b ldr r3, [r3, #0]
8002434: 691b ldr r3, [r3, #16]
8002436: f003 0302 and.w r3, r3, #2
800243a: 2b02 cmp r3, #2
800243c: d122 bne.n 8002484 <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
800243e: 687b ldr r3, [r7, #4]
8002440: 681b ldr r3, [r3, #0]
8002442: 68db ldr r3, [r3, #12]
8002444: f003 0302 and.w r3, r3, #2
8002448: 2b02 cmp r3, #2
800244a: d11b bne.n 8002484 <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
800244c: 687b ldr r3, [r7, #4]
800244e: 681b ldr r3, [r3, #0]
8002450: f06f 0202 mvn.w r2, #2
8002454: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8002456: 687b ldr r3, [r7, #4]
8002458: 2201 movs r2, #1
800245a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
800245c: 687b ldr r3, [r7, #4]
800245e: 681b ldr r3, [r3, #0]
8002460: 699b ldr r3, [r3, #24]
8002462: f003 0303 and.w r3, r3, #3
8002466: 2b00 cmp r3, #0
8002468: d003 beq.n 8002472 <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800246a: 6878 ldr r0, [r7, #4]
800246c: f000 fadd bl 8002a2a <HAL_TIM_IC_CaptureCallback>
8002470: e005 b.n 800247e <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002472: 6878 ldr r0, [r7, #4]
8002474: f000 facf bl 8002a16 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002478: 6878 ldr r0, [r7, #4]
800247a: f000 fae0 bl 8002a3e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800247e: 687b ldr r3, [r7, #4]
8002480: 2200 movs r2, #0
8002482: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8002484: 687b ldr r3, [r7, #4]
8002486: 681b ldr r3, [r3, #0]
8002488: 691b ldr r3, [r3, #16]
800248a: f003 0304 and.w r3, r3, #4
800248e: 2b04 cmp r3, #4
8002490: d122 bne.n 80024d8 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8002492: 687b ldr r3, [r7, #4]
8002494: 681b ldr r3, [r3, #0]
8002496: 68db ldr r3, [r3, #12]
8002498: f003 0304 and.w r3, r3, #4
800249c: 2b04 cmp r3, #4
800249e: d11b bne.n 80024d8 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
80024a0: 687b ldr r3, [r7, #4]
80024a2: 681b ldr r3, [r3, #0]
80024a4: f06f 0204 mvn.w r2, #4
80024a8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
80024aa: 687b ldr r3, [r7, #4]
80024ac: 2202 movs r2, #2
80024ae: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
80024b0: 687b ldr r3, [r7, #4]
80024b2: 681b ldr r3, [r3, #0]
80024b4: 699b ldr r3, [r3, #24]
80024b6: f403 7340 and.w r3, r3, #768 ; 0x300
80024ba: 2b00 cmp r3, #0
80024bc: d003 beq.n 80024c6 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80024be: 6878 ldr r0, [r7, #4]
80024c0: f000 fab3 bl 8002a2a <HAL_TIM_IC_CaptureCallback>
80024c4: e005 b.n 80024d2 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80024c6: 6878 ldr r0, [r7, #4]
80024c8: f000 faa5 bl 8002a16 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80024cc: 6878 ldr r0, [r7, #4]
80024ce: f000 fab6 bl 8002a3e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80024d2: 687b ldr r3, [r7, #4]
80024d4: 2200 movs r2, #0
80024d6: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
80024d8: 687b ldr r3, [r7, #4]
80024da: 681b ldr r3, [r3, #0]
80024dc: 691b ldr r3, [r3, #16]
80024de: f003 0308 and.w r3, r3, #8
80024e2: 2b08 cmp r3, #8
80024e4: d122 bne.n 800252c <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
80024e6: 687b ldr r3, [r7, #4]
80024e8: 681b ldr r3, [r3, #0]
80024ea: 68db ldr r3, [r3, #12]
80024ec: f003 0308 and.w r3, r3, #8
80024f0: 2b08 cmp r3, #8
80024f2: d11b bne.n 800252c <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
80024f4: 687b ldr r3, [r7, #4]
80024f6: 681b ldr r3, [r3, #0]
80024f8: f06f 0208 mvn.w r2, #8
80024fc: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
80024fe: 687b ldr r3, [r7, #4]
8002500: 2204 movs r2, #4
8002502: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8002504: 687b ldr r3, [r7, #4]
8002506: 681b ldr r3, [r3, #0]
8002508: 69db ldr r3, [r3, #28]
800250a: f003 0303 and.w r3, r3, #3
800250e: 2b00 cmp r3, #0
8002510: d003 beq.n 800251a <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002512: 6878 ldr r0, [r7, #4]
8002514: f000 fa89 bl 8002a2a <HAL_TIM_IC_CaptureCallback>
8002518: e005 b.n 8002526 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800251a: 6878 ldr r0, [r7, #4]
800251c: f000 fa7b bl 8002a16 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002520: 6878 ldr r0, [r7, #4]
8002522: f000 fa8c bl 8002a3e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002526: 687b ldr r3, [r7, #4]
8002528: 2200 movs r2, #0
800252a: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
800252c: 687b ldr r3, [r7, #4]
800252e: 681b ldr r3, [r3, #0]
8002530: 691b ldr r3, [r3, #16]
8002532: f003 0310 and.w r3, r3, #16
8002536: 2b10 cmp r3, #16
8002538: d122 bne.n 8002580 <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
800253a: 687b ldr r3, [r7, #4]
800253c: 681b ldr r3, [r3, #0]
800253e: 68db ldr r3, [r3, #12]
8002540: f003 0310 and.w r3, r3, #16
8002544: 2b10 cmp r3, #16
8002546: d11b bne.n 8002580 <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8002548: 687b ldr r3, [r7, #4]
800254a: 681b ldr r3, [r3, #0]
800254c: f06f 0210 mvn.w r2, #16
8002550: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8002552: 687b ldr r3, [r7, #4]
8002554: 2208 movs r2, #8
8002556: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8002558: 687b ldr r3, [r7, #4]
800255a: 681b ldr r3, [r3, #0]
800255c: 69db ldr r3, [r3, #28]
800255e: f403 7340 and.w r3, r3, #768 ; 0x300
8002562: 2b00 cmp r3, #0
8002564: d003 beq.n 800256e <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002566: 6878 ldr r0, [r7, #4]
8002568: f000 fa5f bl 8002a2a <HAL_TIM_IC_CaptureCallback>
800256c: e005 b.n 800257a <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800256e: 6878 ldr r0, [r7, #4]
8002570: f000 fa51 bl 8002a16 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002574: 6878 ldr r0, [r7, #4]
8002576: f000 fa62 bl 8002a3e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800257a: 687b ldr r3, [r7, #4]
800257c: 2200 movs r2, #0
800257e: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8002580: 687b ldr r3, [r7, #4]
8002582: 681b ldr r3, [r3, #0]
8002584: 691b ldr r3, [r3, #16]
8002586: f003 0301 and.w r3, r3, #1
800258a: 2b01 cmp r3, #1
800258c: d10e bne.n 80025ac <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
800258e: 687b ldr r3, [r7, #4]
8002590: 681b ldr r3, [r3, #0]
8002592: 68db ldr r3, [r3, #12]
8002594: f003 0301 and.w r3, r3, #1
8002598: 2b01 cmp r3, #1
800259a: d107 bne.n 80025ac <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
800259c: 687b ldr r3, [r7, #4]
800259e: 681b ldr r3, [r3, #0]
80025a0: f06f 0201 mvn.w r2, #1
80025a4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
80025a6: 6878 ldr r0, [r7, #4]
80025a8: f000 fa2b bl 8002a02 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
80025ac: 687b ldr r3, [r7, #4]
80025ae: 681b ldr r3, [r3, #0]
80025b0: 691b ldr r3, [r3, #16]
80025b2: f003 0380 and.w r3, r3, #128 ; 0x80
80025b6: 2b80 cmp r3, #128 ; 0x80
80025b8: d10e bne.n 80025d8 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
80025ba: 687b ldr r3, [r7, #4]
80025bc: 681b ldr r3, [r3, #0]
80025be: 68db ldr r3, [r3, #12]
80025c0: f003 0380 and.w r3, r3, #128 ; 0x80
80025c4: 2b80 cmp r3, #128 ; 0x80
80025c6: d107 bne.n 80025d8 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
80025c8: 687b ldr r3, [r7, #4]
80025ca: 681b ldr r3, [r3, #0]
80025cc: f06f 0280 mvn.w r2, #128 ; 0x80
80025d0: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
80025d2: 6878 ldr r0, [r7, #4]
80025d4: f000 fe30 bl 8003238 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
80025d8: 687b ldr r3, [r7, #4]
80025da: 681b ldr r3, [r3, #0]
80025dc: 691b ldr r3, [r3, #16]
80025de: f003 0340 and.w r3, r3, #64 ; 0x40
80025e2: 2b40 cmp r3, #64 ; 0x40
80025e4: d10e bne.n 8002604 <HAL_TIM_IRQHandler+0x1dc>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
80025e6: 687b ldr r3, [r7, #4]
80025e8: 681b ldr r3, [r3, #0]
80025ea: 68db ldr r3, [r3, #12]
80025ec: f003 0340 and.w r3, r3, #64 ; 0x40
80025f0: 2b40 cmp r3, #64 ; 0x40
80025f2: d107 bne.n 8002604 <HAL_TIM_IRQHandler+0x1dc>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
80025f4: 687b ldr r3, [r7, #4]
80025f6: 681b ldr r3, [r3, #0]
80025f8: f06f 0240 mvn.w r2, #64 ; 0x40
80025fc: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
80025fe: 6878 ldr r0, [r7, #4]
8002600: f000 fa27 bl 8002a52 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8002604: 687b ldr r3, [r7, #4]
8002606: 681b ldr r3, [r3, #0]
8002608: 691b ldr r3, [r3, #16]
800260a: f003 0320 and.w r3, r3, #32
800260e: 2b20 cmp r3, #32
8002610: d10e bne.n 8002630 <HAL_TIM_IRQHandler+0x208>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8002612: 687b ldr r3, [r7, #4]
8002614: 681b ldr r3, [r3, #0]
8002616: 68db ldr r3, [r3, #12]
8002618: f003 0320 and.w r3, r3, #32
800261c: 2b20 cmp r3, #32
800261e: d107 bne.n 8002630 <HAL_TIM_IRQHandler+0x208>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8002620: 687b ldr r3, [r7, #4]
8002622: 681b ldr r3, [r3, #0]
8002624: f06f 0220 mvn.w r2, #32
8002628: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
800262a: 6878 ldr r0, [r7, #4]
800262c: f000 fdfa bl 8003224 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8002630: bf00 nop
8002632: 3708 adds r7, #8
8002634: 46bd mov sp, r7
8002636: bd80 pop {r7, pc}
08002638 <HAL_TIM_OC_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8002638: b580 push {r7, lr}
800263a: b086 sub sp, #24
800263c: af00 add r7, sp, #0
800263e: 60f8 str r0, [r7, #12]
8002640: 60b9 str r1, [r7, #8]
8002642: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8002644: 2300 movs r3, #0
8002646: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
/* Process Locked */
__HAL_LOCK(htim);
8002648: 68fb ldr r3, [r7, #12]
800264a: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800264e: 2b01 cmp r3, #1
8002650: d101 bne.n 8002656 <HAL_TIM_OC_ConfigChannel+0x1e>
8002652: 2302 movs r3, #2
8002654: e048 b.n 80026e8 <HAL_TIM_OC_ConfigChannel+0xb0>
8002656: 68fb ldr r3, [r7, #12]
8002658: 2201 movs r2, #1
800265a: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
800265e: 687b ldr r3, [r7, #4]
8002660: 2b0c cmp r3, #12
8002662: d839 bhi.n 80026d8 <HAL_TIM_OC_ConfigChannel+0xa0>
8002664: a201 add r2, pc, #4 ; (adr r2, 800266c <HAL_TIM_OC_ConfigChannel+0x34>)
8002666: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800266a: bf00 nop
800266c: 080026a1 .word 0x080026a1
8002670: 080026d9 .word 0x080026d9
8002674: 080026d9 .word 0x080026d9
8002678: 080026d9 .word 0x080026d9
800267c: 080026af .word 0x080026af
8002680: 080026d9 .word 0x080026d9
8002684: 080026d9 .word 0x080026d9
8002688: 080026d9 .word 0x080026d9
800268c: 080026bd .word 0x080026bd
8002690: 080026d9 .word 0x080026d9
8002694: 080026d9 .word 0x080026d9
8002698: 080026d9 .word 0x080026d9
800269c: 080026cb .word 0x080026cb
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the TIM Channel 1 in Output Compare */
TIM_OC1_SetConfig(htim->Instance, sConfig);
80026a0: 68fb ldr r3, [r7, #12]
80026a2: 681b ldr r3, [r3, #0]
80026a4: 68b9 ldr r1, [r7, #8]
80026a6: 4618 mov r0, r3
80026a8: f000 fa7e bl 8002ba8 <TIM_OC1_SetConfig>
break;
80026ac: e017 b.n 80026de <HAL_TIM_OC_ConfigChannel+0xa6>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the TIM Channel 2 in Output Compare */
TIM_OC2_SetConfig(htim->Instance, sConfig);
80026ae: 68fb ldr r3, [r7, #12]
80026b0: 681b ldr r3, [r3, #0]
80026b2: 68b9 ldr r1, [r7, #8]
80026b4: 4618 mov r0, r3
80026b6: f000 fae7 bl 8002c88 <TIM_OC2_SetConfig>
break;
80026ba: e010 b.n 80026de <HAL_TIM_OC_ConfigChannel+0xa6>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the TIM Channel 3 in Output Compare */
TIM_OC3_SetConfig(htim->Instance, sConfig);
80026bc: 68fb ldr r3, [r7, #12]
80026be: 681b ldr r3, [r3, #0]
80026c0: 68b9 ldr r1, [r7, #8]
80026c2: 4618 mov r0, r3
80026c4: f000 fb56 bl 8002d74 <TIM_OC3_SetConfig>
break;
80026c8: e009 b.n 80026de <HAL_TIM_OC_ConfigChannel+0xa6>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the TIM Channel 4 in Output Compare */
TIM_OC4_SetConfig(htim->Instance, sConfig);
80026ca: 68fb ldr r3, [r7, #12]
80026cc: 681b ldr r3, [r3, #0]
80026ce: 68b9 ldr r1, [r7, #8]
80026d0: 4618 mov r0, r3
80026d2: f000 fbc3 bl 8002e5c <TIM_OC4_SetConfig>
break;
80026d6: e002 b.n 80026de <HAL_TIM_OC_ConfigChannel+0xa6>
}
default:
status = HAL_ERROR;
80026d8: 2301 movs r3, #1
80026da: 75fb strb r3, [r7, #23]
break;
80026dc: bf00 nop
}
__HAL_UNLOCK(htim);
80026de: 68fb ldr r3, [r7, #12]
80026e0: 2200 movs r2, #0
80026e2: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
80026e6: 7dfb ldrb r3, [r7, #23]
}
80026e8: 4618 mov r0, r3
80026ea: 3718 adds r7, #24
80026ec: 46bd mov sp, r7
80026ee: bd80 pop {r7, pc}
080026f0 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
80026f0: b580 push {r7, lr}
80026f2: b086 sub sp, #24
80026f4: af00 add r7, sp, #0
80026f6: 60f8 str r0, [r7, #12]
80026f8: 60b9 str r1, [r7, #8]
80026fa: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80026fc: 2300 movs r3, #0
80026fe: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8002700: 68fb ldr r3, [r7, #12]
8002702: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002706: 2b01 cmp r3, #1
8002708: d101 bne.n 800270e <HAL_TIM_PWM_ConfigChannel+0x1e>
800270a: 2302 movs r3, #2
800270c: e0ae b.n 800286c <HAL_TIM_PWM_ConfigChannel+0x17c>
800270e: 68fb ldr r3, [r7, #12]
8002710: 2201 movs r2, #1
8002712: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
8002716: 687b ldr r3, [r7, #4]
8002718: 2b0c cmp r3, #12
800271a: f200 809f bhi.w 800285c <HAL_TIM_PWM_ConfigChannel+0x16c>
800271e: a201 add r2, pc, #4 ; (adr r2, 8002724 <HAL_TIM_PWM_ConfigChannel+0x34>)
8002720: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002724: 08002759 .word 0x08002759
8002728: 0800285d .word 0x0800285d
800272c: 0800285d .word 0x0800285d
8002730: 0800285d .word 0x0800285d
8002734: 08002799 .word 0x08002799
8002738: 0800285d .word 0x0800285d
800273c: 0800285d .word 0x0800285d
8002740: 0800285d .word 0x0800285d
8002744: 080027db .word 0x080027db
8002748: 0800285d .word 0x0800285d
800274c: 0800285d .word 0x0800285d
8002750: 0800285d .word 0x0800285d
8002754: 0800281b .word 0x0800281b
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8002758: 68fb ldr r3, [r7, #12]
800275a: 681b ldr r3, [r3, #0]
800275c: 68b9 ldr r1, [r7, #8]
800275e: 4618 mov r0, r3
8002760: f000 fa22 bl 8002ba8 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8002764: 68fb ldr r3, [r7, #12]
8002766: 681b ldr r3, [r3, #0]
8002768: 699a ldr r2, [r3, #24]
800276a: 68fb ldr r3, [r7, #12]
800276c: 681b ldr r3, [r3, #0]
800276e: f042 0208 orr.w r2, r2, #8
8002772: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8002774: 68fb ldr r3, [r7, #12]
8002776: 681b ldr r3, [r3, #0]
8002778: 699a ldr r2, [r3, #24]
800277a: 68fb ldr r3, [r7, #12]
800277c: 681b ldr r3, [r3, #0]
800277e: f022 0204 bic.w r2, r2, #4
8002782: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8002784: 68fb ldr r3, [r7, #12]
8002786: 681b ldr r3, [r3, #0]
8002788: 6999 ldr r1, [r3, #24]
800278a: 68bb ldr r3, [r7, #8]
800278c: 691a ldr r2, [r3, #16]
800278e: 68fb ldr r3, [r7, #12]
8002790: 681b ldr r3, [r3, #0]
8002792: 430a orrs r2, r1
8002794: 619a str r2, [r3, #24]
break;
8002796: e064 b.n 8002862 <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8002798: 68fb ldr r3, [r7, #12]
800279a: 681b ldr r3, [r3, #0]
800279c: 68b9 ldr r1, [r7, #8]
800279e: 4618 mov r0, r3
80027a0: f000 fa72 bl 8002c88 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
80027a4: 68fb ldr r3, [r7, #12]
80027a6: 681b ldr r3, [r3, #0]
80027a8: 699a ldr r2, [r3, #24]
80027aa: 68fb ldr r3, [r7, #12]
80027ac: 681b ldr r3, [r3, #0]
80027ae: f442 6200 orr.w r2, r2, #2048 ; 0x800
80027b2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
80027b4: 68fb ldr r3, [r7, #12]
80027b6: 681b ldr r3, [r3, #0]
80027b8: 699a ldr r2, [r3, #24]
80027ba: 68fb ldr r3, [r7, #12]
80027bc: 681b ldr r3, [r3, #0]
80027be: f422 6280 bic.w r2, r2, #1024 ; 0x400
80027c2: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
80027c4: 68fb ldr r3, [r7, #12]
80027c6: 681b ldr r3, [r3, #0]
80027c8: 6999 ldr r1, [r3, #24]
80027ca: 68bb ldr r3, [r7, #8]
80027cc: 691b ldr r3, [r3, #16]
80027ce: 021a lsls r2, r3, #8
80027d0: 68fb ldr r3, [r7, #12]
80027d2: 681b ldr r3, [r3, #0]
80027d4: 430a orrs r2, r1
80027d6: 619a str r2, [r3, #24]
break;
80027d8: e043 b.n 8002862 <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
80027da: 68fb ldr r3, [r7, #12]
80027dc: 681b ldr r3, [r3, #0]
80027de: 68b9 ldr r1, [r7, #8]
80027e0: 4618 mov r0, r3
80027e2: f000 fac7 bl 8002d74 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
80027e6: 68fb ldr r3, [r7, #12]
80027e8: 681b ldr r3, [r3, #0]
80027ea: 69da ldr r2, [r3, #28]
80027ec: 68fb ldr r3, [r7, #12]
80027ee: 681b ldr r3, [r3, #0]
80027f0: f042 0208 orr.w r2, r2, #8
80027f4: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
80027f6: 68fb ldr r3, [r7, #12]
80027f8: 681b ldr r3, [r3, #0]
80027fa: 69da ldr r2, [r3, #28]
80027fc: 68fb ldr r3, [r7, #12]
80027fe: 681b ldr r3, [r3, #0]
8002800: f022 0204 bic.w r2, r2, #4
8002804: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8002806: 68fb ldr r3, [r7, #12]
8002808: 681b ldr r3, [r3, #0]
800280a: 69d9 ldr r1, [r3, #28]
800280c: 68bb ldr r3, [r7, #8]
800280e: 691a ldr r2, [r3, #16]
8002810: 68fb ldr r3, [r7, #12]
8002812: 681b ldr r3, [r3, #0]
8002814: 430a orrs r2, r1
8002816: 61da str r2, [r3, #28]
break;
8002818: e023 b.n 8002862 <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
800281a: 68fb ldr r3, [r7, #12]
800281c: 681b ldr r3, [r3, #0]
800281e: 68b9 ldr r1, [r7, #8]
8002820: 4618 mov r0, r3
8002822: f000 fb1b bl 8002e5c <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8002826: 68fb ldr r3, [r7, #12]
8002828: 681b ldr r3, [r3, #0]
800282a: 69da ldr r2, [r3, #28]
800282c: 68fb ldr r3, [r7, #12]
800282e: 681b ldr r3, [r3, #0]
8002830: f442 6200 orr.w r2, r2, #2048 ; 0x800
8002834: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8002836: 68fb ldr r3, [r7, #12]
8002838: 681b ldr r3, [r3, #0]
800283a: 69da ldr r2, [r3, #28]
800283c: 68fb ldr r3, [r7, #12]
800283e: 681b ldr r3, [r3, #0]
8002840: f422 6280 bic.w r2, r2, #1024 ; 0x400
8002844: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8002846: 68fb ldr r3, [r7, #12]
8002848: 681b ldr r3, [r3, #0]
800284a: 69d9 ldr r1, [r3, #28]
800284c: 68bb ldr r3, [r7, #8]
800284e: 691b ldr r3, [r3, #16]
8002850: 021a lsls r2, r3, #8
8002852: 68fb ldr r3, [r7, #12]
8002854: 681b ldr r3, [r3, #0]
8002856: 430a orrs r2, r1
8002858: 61da str r2, [r3, #28]
break;
800285a: e002 b.n 8002862 <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
800285c: 2301 movs r3, #1
800285e: 75fb strb r3, [r7, #23]
break;
8002860: bf00 nop
}
__HAL_UNLOCK(htim);
8002862: 68fb ldr r3, [r7, #12]
8002864: 2200 movs r2, #0
8002866: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
800286a: 7dfb ldrb r3, [r7, #23]
}
800286c: 4618 mov r0, r3
800286e: 3718 adds r7, #24
8002870: 46bd mov sp, r7
8002872: bd80 pop {r7, pc}
08002874 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8002874: b580 push {r7, lr}
8002876: b084 sub sp, #16
8002878: af00 add r7, sp, #0
800287a: 6078 str r0, [r7, #4]
800287c: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
800287e: 2300 movs r3, #0
8002880: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
8002882: 687b ldr r3, [r7, #4]
8002884: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002888: 2b01 cmp r3, #1
800288a: d101 bne.n 8002890 <HAL_TIM_ConfigClockSource+0x1c>
800288c: 2302 movs r3, #2
800288e: e0b4 b.n 80029fa <HAL_TIM_ConfigClockSource+0x186>
8002890: 687b ldr r3, [r7, #4]
8002892: 2201 movs r2, #1
8002894: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8002898: 687b ldr r3, [r7, #4]
800289a: 2202 movs r2, #2
800289c: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
80028a0: 687b ldr r3, [r7, #4]
80028a2: 681b ldr r3, [r3, #0]
80028a4: 689b ldr r3, [r3, #8]
80028a6: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
80028a8: 68bb ldr r3, [r7, #8]
80028aa: f023 0377 bic.w r3, r3, #119 ; 0x77
80028ae: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
80028b0: 68bb ldr r3, [r7, #8]
80028b2: f423 437f bic.w r3, r3, #65280 ; 0xff00
80028b6: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
80028b8: 687b ldr r3, [r7, #4]
80028ba: 681b ldr r3, [r3, #0]
80028bc: 68ba ldr r2, [r7, #8]
80028be: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
80028c0: 683b ldr r3, [r7, #0]
80028c2: 681b ldr r3, [r3, #0]
80028c4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80028c8: d03e beq.n 8002948 <HAL_TIM_ConfigClockSource+0xd4>
80028ca: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80028ce: f200 8087 bhi.w 80029e0 <HAL_TIM_ConfigClockSource+0x16c>
80028d2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80028d6: f000 8086 beq.w 80029e6 <HAL_TIM_ConfigClockSource+0x172>
80028da: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80028de: d87f bhi.n 80029e0 <HAL_TIM_ConfigClockSource+0x16c>
80028e0: 2b70 cmp r3, #112 ; 0x70
80028e2: d01a beq.n 800291a <HAL_TIM_ConfigClockSource+0xa6>
80028e4: 2b70 cmp r3, #112 ; 0x70
80028e6: d87b bhi.n 80029e0 <HAL_TIM_ConfigClockSource+0x16c>
80028e8: 2b60 cmp r3, #96 ; 0x60
80028ea: d050 beq.n 800298e <HAL_TIM_ConfigClockSource+0x11a>
80028ec: 2b60 cmp r3, #96 ; 0x60
80028ee: d877 bhi.n 80029e0 <HAL_TIM_ConfigClockSource+0x16c>
80028f0: 2b50 cmp r3, #80 ; 0x50
80028f2: d03c beq.n 800296e <HAL_TIM_ConfigClockSource+0xfa>
80028f4: 2b50 cmp r3, #80 ; 0x50
80028f6: d873 bhi.n 80029e0 <HAL_TIM_ConfigClockSource+0x16c>
80028f8: 2b40 cmp r3, #64 ; 0x40
80028fa: d058 beq.n 80029ae <HAL_TIM_ConfigClockSource+0x13a>
80028fc: 2b40 cmp r3, #64 ; 0x40
80028fe: d86f bhi.n 80029e0 <HAL_TIM_ConfigClockSource+0x16c>
8002900: 2b30 cmp r3, #48 ; 0x30
8002902: d064 beq.n 80029ce <HAL_TIM_ConfigClockSource+0x15a>
8002904: 2b30 cmp r3, #48 ; 0x30
8002906: d86b bhi.n 80029e0 <HAL_TIM_ConfigClockSource+0x16c>
8002908: 2b20 cmp r3, #32
800290a: d060 beq.n 80029ce <HAL_TIM_ConfigClockSource+0x15a>
800290c: 2b20 cmp r3, #32
800290e: d867 bhi.n 80029e0 <HAL_TIM_ConfigClockSource+0x16c>
8002910: 2b00 cmp r3, #0
8002912: d05c beq.n 80029ce <HAL_TIM_ConfigClockSource+0x15a>
8002914: 2b10 cmp r3, #16
8002916: d05a beq.n 80029ce <HAL_TIM_ConfigClockSource+0x15a>
8002918: e062 b.n 80029e0 <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
800291a: 687b ldr r3, [r7, #4]
800291c: 6818 ldr r0, [r3, #0]
800291e: 683b ldr r3, [r7, #0]
8002920: 6899 ldr r1, [r3, #8]
8002922: 683b ldr r3, [r7, #0]
8002924: 685a ldr r2, [r3, #4]
8002926: 683b ldr r3, [r7, #0]
8002928: 68db ldr r3, [r3, #12]
800292a: f000 fb67 bl 8002ffc <TIM_ETR_SetConfig>
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
800292e: 687b ldr r3, [r7, #4]
8002930: 681b ldr r3, [r3, #0]
8002932: 689b ldr r3, [r3, #8]
8002934: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8002936: 68bb ldr r3, [r7, #8]
8002938: f043 0377 orr.w r3, r3, #119 ; 0x77
800293c: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800293e: 687b ldr r3, [r7, #4]
8002940: 681b ldr r3, [r3, #0]
8002942: 68ba ldr r2, [r7, #8]
8002944: 609a str r2, [r3, #8]
break;
8002946: e04f b.n 80029e8 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8002948: 687b ldr r3, [r7, #4]
800294a: 6818 ldr r0, [r3, #0]
800294c: 683b ldr r3, [r7, #0]
800294e: 6899 ldr r1, [r3, #8]
8002950: 683b ldr r3, [r7, #0]
8002952: 685a ldr r2, [r3, #4]
8002954: 683b ldr r3, [r7, #0]
8002956: 68db ldr r3, [r3, #12]
8002958: f000 fb50 bl 8002ffc <TIM_ETR_SetConfig>
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
800295c: 687b ldr r3, [r7, #4]
800295e: 681b ldr r3, [r3, #0]
8002960: 689a ldr r2, [r3, #8]
8002962: 687b ldr r3, [r7, #4]
8002964: 681b ldr r3, [r3, #0]
8002966: f442 4280 orr.w r2, r2, #16384 ; 0x4000
800296a: 609a str r2, [r3, #8]
break;
800296c: e03c b.n 80029e8 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800296e: 687b ldr r3, [r7, #4]
8002970: 6818 ldr r0, [r3, #0]
8002972: 683b ldr r3, [r7, #0]
8002974: 6859 ldr r1, [r3, #4]
8002976: 683b ldr r3, [r7, #0]
8002978: 68db ldr r3, [r3, #12]
800297a: 461a mov r2, r3
800297c: f000 fac4 bl 8002f08 <TIM_TI1_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8002980: 687b ldr r3, [r7, #4]
8002982: 681b ldr r3, [r3, #0]
8002984: 2150 movs r1, #80 ; 0x50
8002986: 4618 mov r0, r3
8002988: f000 fb1d bl 8002fc6 <TIM_ITRx_SetConfig>
break;
800298c: e02c b.n 80029e8 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
800298e: 687b ldr r3, [r7, #4]
8002990: 6818 ldr r0, [r3, #0]
8002992: 683b ldr r3, [r7, #0]
8002994: 6859 ldr r1, [r3, #4]
8002996: 683b ldr r3, [r7, #0]
8002998: 68db ldr r3, [r3, #12]
800299a: 461a mov r2, r3
800299c: f000 fae3 bl 8002f66 <TIM_TI2_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
80029a0: 687b ldr r3, [r7, #4]
80029a2: 681b ldr r3, [r3, #0]
80029a4: 2160 movs r1, #96 ; 0x60
80029a6: 4618 mov r0, r3
80029a8: f000 fb0d bl 8002fc6 <TIM_ITRx_SetConfig>
break;
80029ac: e01c b.n 80029e8 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80029ae: 687b ldr r3, [r7, #4]
80029b0: 6818 ldr r0, [r3, #0]
80029b2: 683b ldr r3, [r7, #0]
80029b4: 6859 ldr r1, [r3, #4]
80029b6: 683b ldr r3, [r7, #0]
80029b8: 68db ldr r3, [r3, #12]
80029ba: 461a mov r2, r3
80029bc: f000 faa4 bl 8002f08 <TIM_TI1_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
80029c0: 687b ldr r3, [r7, #4]
80029c2: 681b ldr r3, [r3, #0]
80029c4: 2140 movs r1, #64 ; 0x40
80029c6: 4618 mov r0, r3
80029c8: f000 fafd bl 8002fc6 <TIM_ITRx_SetConfig>
break;
80029cc: e00c b.n 80029e8 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
80029ce: 687b ldr r3, [r7, #4]
80029d0: 681a ldr r2, [r3, #0]
80029d2: 683b ldr r3, [r7, #0]
80029d4: 681b ldr r3, [r3, #0]
80029d6: 4619 mov r1, r3
80029d8: 4610 mov r0, r2
80029da: f000 faf4 bl 8002fc6 <TIM_ITRx_SetConfig>
break;
80029de: e003 b.n 80029e8 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
80029e0: 2301 movs r3, #1
80029e2: 73fb strb r3, [r7, #15]
break;
80029e4: e000 b.n 80029e8 <HAL_TIM_ConfigClockSource+0x174>
break;
80029e6: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
80029e8: 687b ldr r3, [r7, #4]
80029ea: 2201 movs r2, #1
80029ec: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
80029f0: 687b ldr r3, [r7, #4]
80029f2: 2200 movs r2, #0
80029f4: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
80029f8: 7bfb ldrb r3, [r7, #15]
}
80029fa: 4618 mov r0, r3
80029fc: 3710 adds r7, #16
80029fe: 46bd mov sp, r7
8002a00: bd80 pop {r7, pc}
08002a02 <HAL_TIM_PeriodElapsedCallback>:
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8002a02: b480 push {r7}
8002a04: b083 sub sp, #12
8002a06: af00 add r7, sp, #0
8002a08: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
8002a0a: bf00 nop
8002a0c: 370c adds r7, #12
8002a0e: 46bd mov sp, r7
8002a10: f85d 7b04 ldr.w r7, [sp], #4
8002a14: 4770 bx lr
08002a16 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8002a16: b480 push {r7}
8002a18: b083 sub sp, #12
8002a1a: af00 add r7, sp, #0
8002a1c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8002a1e: bf00 nop
8002a20: 370c adds r7, #12
8002a22: 46bd mov sp, r7
8002a24: f85d 7b04 ldr.w r7, [sp], #4
8002a28: 4770 bx lr
08002a2a <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8002a2a: b480 push {r7}
8002a2c: b083 sub sp, #12
8002a2e: af00 add r7, sp, #0
8002a30: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8002a32: bf00 nop
8002a34: 370c adds r7, #12
8002a36: 46bd mov sp, r7
8002a38: f85d 7b04 ldr.w r7, [sp], #4
8002a3c: 4770 bx lr
08002a3e <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8002a3e: b480 push {r7}
8002a40: b083 sub sp, #12
8002a42: af00 add r7, sp, #0
8002a44: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8002a46: bf00 nop
8002a48: 370c adds r7, #12
8002a4a: 46bd mov sp, r7
8002a4c: f85d 7b04 ldr.w r7, [sp], #4
8002a50: 4770 bx lr
08002a52 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8002a52: b480 push {r7}
8002a54: b083 sub sp, #12
8002a56: af00 add r7, sp, #0
8002a58: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8002a5a: bf00 nop
8002a5c: 370c adds r7, #12
8002a5e: 46bd mov sp, r7
8002a60: f85d 7b04 ldr.w r7, [sp], #4
8002a64: 4770 bx lr
...
08002a68 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
8002a68: b480 push {r7}
8002a6a: b085 sub sp, #20
8002a6c: af00 add r7, sp, #0
8002a6e: 6078 str r0, [r7, #4]
8002a70: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8002a72: 687b ldr r3, [r7, #4]
8002a74: 681b ldr r3, [r3, #0]
8002a76: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8002a78: 687b ldr r3, [r7, #4]
8002a7a: 4a40 ldr r2, [pc, #256] ; (8002b7c <TIM_Base_SetConfig+0x114>)
8002a7c: 4293 cmp r3, r2
8002a7e: d013 beq.n 8002aa8 <TIM_Base_SetConfig+0x40>
8002a80: 687b ldr r3, [r7, #4]
8002a82: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8002a86: d00f beq.n 8002aa8 <TIM_Base_SetConfig+0x40>
8002a88: 687b ldr r3, [r7, #4]
8002a8a: 4a3d ldr r2, [pc, #244] ; (8002b80 <TIM_Base_SetConfig+0x118>)
8002a8c: 4293 cmp r3, r2
8002a8e: d00b beq.n 8002aa8 <TIM_Base_SetConfig+0x40>
8002a90: 687b ldr r3, [r7, #4]
8002a92: 4a3c ldr r2, [pc, #240] ; (8002b84 <TIM_Base_SetConfig+0x11c>)
8002a94: 4293 cmp r3, r2
8002a96: d007 beq.n 8002aa8 <TIM_Base_SetConfig+0x40>
8002a98: 687b ldr r3, [r7, #4]
8002a9a: 4a3b ldr r2, [pc, #236] ; (8002b88 <TIM_Base_SetConfig+0x120>)
8002a9c: 4293 cmp r3, r2
8002a9e: d003 beq.n 8002aa8 <TIM_Base_SetConfig+0x40>
8002aa0: 687b ldr r3, [r7, #4]
8002aa2: 4a3a ldr r2, [pc, #232] ; (8002b8c <TIM_Base_SetConfig+0x124>)
8002aa4: 4293 cmp r3, r2
8002aa6: d108 bne.n 8002aba <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8002aa8: 68fb ldr r3, [r7, #12]
8002aaa: f023 0370 bic.w r3, r3, #112 ; 0x70
8002aae: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8002ab0: 683b ldr r3, [r7, #0]
8002ab2: 685b ldr r3, [r3, #4]
8002ab4: 68fa ldr r2, [r7, #12]
8002ab6: 4313 orrs r3, r2
8002ab8: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8002aba: 687b ldr r3, [r7, #4]
8002abc: 4a2f ldr r2, [pc, #188] ; (8002b7c <TIM_Base_SetConfig+0x114>)
8002abe: 4293 cmp r3, r2
8002ac0: d02b beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002ac2: 687b ldr r3, [r7, #4]
8002ac4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8002ac8: d027 beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002aca: 687b ldr r3, [r7, #4]
8002acc: 4a2c ldr r2, [pc, #176] ; (8002b80 <TIM_Base_SetConfig+0x118>)
8002ace: 4293 cmp r3, r2
8002ad0: d023 beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002ad2: 687b ldr r3, [r7, #4]
8002ad4: 4a2b ldr r2, [pc, #172] ; (8002b84 <TIM_Base_SetConfig+0x11c>)
8002ad6: 4293 cmp r3, r2
8002ad8: d01f beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002ada: 687b ldr r3, [r7, #4]
8002adc: 4a2a ldr r2, [pc, #168] ; (8002b88 <TIM_Base_SetConfig+0x120>)
8002ade: 4293 cmp r3, r2
8002ae0: d01b beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002ae2: 687b ldr r3, [r7, #4]
8002ae4: 4a29 ldr r2, [pc, #164] ; (8002b8c <TIM_Base_SetConfig+0x124>)
8002ae6: 4293 cmp r3, r2
8002ae8: d017 beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002aea: 687b ldr r3, [r7, #4]
8002aec: 4a28 ldr r2, [pc, #160] ; (8002b90 <TIM_Base_SetConfig+0x128>)
8002aee: 4293 cmp r3, r2
8002af0: d013 beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002af2: 687b ldr r3, [r7, #4]
8002af4: 4a27 ldr r2, [pc, #156] ; (8002b94 <TIM_Base_SetConfig+0x12c>)
8002af6: 4293 cmp r3, r2
8002af8: d00f beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002afa: 687b ldr r3, [r7, #4]
8002afc: 4a26 ldr r2, [pc, #152] ; (8002b98 <TIM_Base_SetConfig+0x130>)
8002afe: 4293 cmp r3, r2
8002b00: d00b beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002b02: 687b ldr r3, [r7, #4]
8002b04: 4a25 ldr r2, [pc, #148] ; (8002b9c <TIM_Base_SetConfig+0x134>)
8002b06: 4293 cmp r3, r2
8002b08: d007 beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002b0a: 687b ldr r3, [r7, #4]
8002b0c: 4a24 ldr r2, [pc, #144] ; (8002ba0 <TIM_Base_SetConfig+0x138>)
8002b0e: 4293 cmp r3, r2
8002b10: d003 beq.n 8002b1a <TIM_Base_SetConfig+0xb2>
8002b12: 687b ldr r3, [r7, #4]
8002b14: 4a23 ldr r2, [pc, #140] ; (8002ba4 <TIM_Base_SetConfig+0x13c>)
8002b16: 4293 cmp r3, r2
8002b18: d108 bne.n 8002b2c <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8002b1a: 68fb ldr r3, [r7, #12]
8002b1c: f423 7340 bic.w r3, r3, #768 ; 0x300
8002b20: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8002b22: 683b ldr r3, [r7, #0]
8002b24: 68db ldr r3, [r3, #12]
8002b26: 68fa ldr r2, [r7, #12]
8002b28: 4313 orrs r3, r2
8002b2a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8002b2c: 68fb ldr r3, [r7, #12]
8002b2e: f023 0280 bic.w r2, r3, #128 ; 0x80
8002b32: 683b ldr r3, [r7, #0]
8002b34: 695b ldr r3, [r3, #20]
8002b36: 4313 orrs r3, r2
8002b38: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8002b3a: 687b ldr r3, [r7, #4]
8002b3c: 68fa ldr r2, [r7, #12]
8002b3e: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8002b40: 683b ldr r3, [r7, #0]
8002b42: 689a ldr r2, [r3, #8]
8002b44: 687b ldr r3, [r7, #4]
8002b46: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8002b48: 683b ldr r3, [r7, #0]
8002b4a: 681a ldr r2, [r3, #0]
8002b4c: 687b ldr r3, [r7, #4]
8002b4e: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8002b50: 687b ldr r3, [r7, #4]
8002b52: 4a0a ldr r2, [pc, #40] ; (8002b7c <TIM_Base_SetConfig+0x114>)
8002b54: 4293 cmp r3, r2
8002b56: d003 beq.n 8002b60 <TIM_Base_SetConfig+0xf8>
8002b58: 687b ldr r3, [r7, #4]
8002b5a: 4a0c ldr r2, [pc, #48] ; (8002b8c <TIM_Base_SetConfig+0x124>)
8002b5c: 4293 cmp r3, r2
8002b5e: d103 bne.n 8002b68 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8002b60: 683b ldr r3, [r7, #0]
8002b62: 691a ldr r2, [r3, #16]
8002b64: 687b ldr r3, [r7, #4]
8002b66: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8002b68: 687b ldr r3, [r7, #4]
8002b6a: 2201 movs r2, #1
8002b6c: 615a str r2, [r3, #20]
}
8002b6e: bf00 nop
8002b70: 3714 adds r7, #20
8002b72: 46bd mov sp, r7
8002b74: f85d 7b04 ldr.w r7, [sp], #4
8002b78: 4770 bx lr
8002b7a: bf00 nop
8002b7c: 40010000 .word 0x40010000
8002b80: 40000400 .word 0x40000400
8002b84: 40000800 .word 0x40000800
8002b88: 40000c00 .word 0x40000c00
8002b8c: 40010400 .word 0x40010400
8002b90: 40014000 .word 0x40014000
8002b94: 40014400 .word 0x40014400
8002b98: 40014800 .word 0x40014800
8002b9c: 40001800 .word 0x40001800
8002ba0: 40001c00 .word 0x40001c00
8002ba4: 40002000 .word 0x40002000
08002ba8 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8002ba8: b480 push {r7}
8002baa: b087 sub sp, #28
8002bac: af00 add r7, sp, #0
8002bae: 6078 str r0, [r7, #4]
8002bb0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8002bb2: 687b ldr r3, [r7, #4]
8002bb4: 6a1b ldr r3, [r3, #32]
8002bb6: f023 0201 bic.w r2, r3, #1
8002bba: 687b ldr r3, [r7, #4]
8002bbc: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002bbe: 687b ldr r3, [r7, #4]
8002bc0: 6a1b ldr r3, [r3, #32]
8002bc2: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002bc4: 687b ldr r3, [r7, #4]
8002bc6: 685b ldr r3, [r3, #4]
8002bc8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8002bca: 687b ldr r3, [r7, #4]
8002bcc: 699b ldr r3, [r3, #24]
8002bce: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8002bd0: 68fb ldr r3, [r7, #12]
8002bd2: f023 0370 bic.w r3, r3, #112 ; 0x70
8002bd6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8002bd8: 68fb ldr r3, [r7, #12]
8002bda: f023 0303 bic.w r3, r3, #3
8002bde: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8002be0: 683b ldr r3, [r7, #0]
8002be2: 681b ldr r3, [r3, #0]
8002be4: 68fa ldr r2, [r7, #12]
8002be6: 4313 orrs r3, r2
8002be8: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8002bea: 697b ldr r3, [r7, #20]
8002bec: f023 0302 bic.w r3, r3, #2
8002bf0: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8002bf2: 683b ldr r3, [r7, #0]
8002bf4: 689b ldr r3, [r3, #8]
8002bf6: 697a ldr r2, [r7, #20]
8002bf8: 4313 orrs r3, r2
8002bfa: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8002bfc: 687b ldr r3, [r7, #4]
8002bfe: 4a20 ldr r2, [pc, #128] ; (8002c80 <TIM_OC1_SetConfig+0xd8>)
8002c00: 4293 cmp r3, r2
8002c02: d003 beq.n 8002c0c <TIM_OC1_SetConfig+0x64>
8002c04: 687b ldr r3, [r7, #4]
8002c06: 4a1f ldr r2, [pc, #124] ; (8002c84 <TIM_OC1_SetConfig+0xdc>)
8002c08: 4293 cmp r3, r2
8002c0a: d10c bne.n 8002c26 <TIM_OC1_SetConfig+0x7e>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8002c0c: 697b ldr r3, [r7, #20]
8002c0e: f023 0308 bic.w r3, r3, #8
8002c12: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8002c14: 683b ldr r3, [r7, #0]
8002c16: 68db ldr r3, [r3, #12]
8002c18: 697a ldr r2, [r7, #20]
8002c1a: 4313 orrs r3, r2
8002c1c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8002c1e: 697b ldr r3, [r7, #20]
8002c20: f023 0304 bic.w r3, r3, #4
8002c24: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002c26: 687b ldr r3, [r7, #4]
8002c28: 4a15 ldr r2, [pc, #84] ; (8002c80 <TIM_OC1_SetConfig+0xd8>)
8002c2a: 4293 cmp r3, r2
8002c2c: d003 beq.n 8002c36 <TIM_OC1_SetConfig+0x8e>
8002c2e: 687b ldr r3, [r7, #4]
8002c30: 4a14 ldr r2, [pc, #80] ; (8002c84 <TIM_OC1_SetConfig+0xdc>)
8002c32: 4293 cmp r3, r2
8002c34: d111 bne.n 8002c5a <TIM_OC1_SetConfig+0xb2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8002c36: 693b ldr r3, [r7, #16]
8002c38: f423 7380 bic.w r3, r3, #256 ; 0x100
8002c3c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8002c3e: 693b ldr r3, [r7, #16]
8002c40: f423 7300 bic.w r3, r3, #512 ; 0x200
8002c44: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8002c46: 683b ldr r3, [r7, #0]
8002c48: 695b ldr r3, [r3, #20]
8002c4a: 693a ldr r2, [r7, #16]
8002c4c: 4313 orrs r3, r2
8002c4e: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8002c50: 683b ldr r3, [r7, #0]
8002c52: 699b ldr r3, [r3, #24]
8002c54: 693a ldr r2, [r7, #16]
8002c56: 4313 orrs r3, r2
8002c58: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002c5a: 687b ldr r3, [r7, #4]
8002c5c: 693a ldr r2, [r7, #16]
8002c5e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8002c60: 687b ldr r3, [r7, #4]
8002c62: 68fa ldr r2, [r7, #12]
8002c64: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8002c66: 683b ldr r3, [r7, #0]
8002c68: 685a ldr r2, [r3, #4]
8002c6a: 687b ldr r3, [r7, #4]
8002c6c: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002c6e: 687b ldr r3, [r7, #4]
8002c70: 697a ldr r2, [r7, #20]
8002c72: 621a str r2, [r3, #32]
}
8002c74: bf00 nop
8002c76: 371c adds r7, #28
8002c78: 46bd mov sp, r7
8002c7a: f85d 7b04 ldr.w r7, [sp], #4
8002c7e: 4770 bx lr
8002c80: 40010000 .word 0x40010000
8002c84: 40010400 .word 0x40010400
08002c88 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8002c88: b480 push {r7}
8002c8a: b087 sub sp, #28
8002c8c: af00 add r7, sp, #0
8002c8e: 6078 str r0, [r7, #4]
8002c90: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8002c92: 687b ldr r3, [r7, #4]
8002c94: 6a1b ldr r3, [r3, #32]
8002c96: f023 0210 bic.w r2, r3, #16
8002c9a: 687b ldr r3, [r7, #4]
8002c9c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002c9e: 687b ldr r3, [r7, #4]
8002ca0: 6a1b ldr r3, [r3, #32]
8002ca2: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002ca4: 687b ldr r3, [r7, #4]
8002ca6: 685b ldr r3, [r3, #4]
8002ca8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8002caa: 687b ldr r3, [r7, #4]
8002cac: 699b ldr r3, [r3, #24]
8002cae: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8002cb0: 68fb ldr r3, [r7, #12]
8002cb2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8002cb6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8002cb8: 68fb ldr r3, [r7, #12]
8002cba: f423 7340 bic.w r3, r3, #768 ; 0x300
8002cbe: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8002cc0: 683b ldr r3, [r7, #0]
8002cc2: 681b ldr r3, [r3, #0]
8002cc4: 021b lsls r3, r3, #8
8002cc6: 68fa ldr r2, [r7, #12]
8002cc8: 4313 orrs r3, r2
8002cca: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8002ccc: 697b ldr r3, [r7, #20]
8002cce: f023 0320 bic.w r3, r3, #32
8002cd2: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8002cd4: 683b ldr r3, [r7, #0]
8002cd6: 689b ldr r3, [r3, #8]
8002cd8: 011b lsls r3, r3, #4
8002cda: 697a ldr r2, [r7, #20]
8002cdc: 4313 orrs r3, r2
8002cde: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8002ce0: 687b ldr r3, [r7, #4]
8002ce2: 4a22 ldr r2, [pc, #136] ; (8002d6c <TIM_OC2_SetConfig+0xe4>)
8002ce4: 4293 cmp r3, r2
8002ce6: d003 beq.n 8002cf0 <TIM_OC2_SetConfig+0x68>
8002ce8: 687b ldr r3, [r7, #4]
8002cea: 4a21 ldr r2, [pc, #132] ; (8002d70 <TIM_OC2_SetConfig+0xe8>)
8002cec: 4293 cmp r3, r2
8002cee: d10d bne.n 8002d0c <TIM_OC2_SetConfig+0x84>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8002cf0: 697b ldr r3, [r7, #20]
8002cf2: f023 0380 bic.w r3, r3, #128 ; 0x80
8002cf6: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8002cf8: 683b ldr r3, [r7, #0]
8002cfa: 68db ldr r3, [r3, #12]
8002cfc: 011b lsls r3, r3, #4
8002cfe: 697a ldr r2, [r7, #20]
8002d00: 4313 orrs r3, r2
8002d02: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8002d04: 697b ldr r3, [r7, #20]
8002d06: f023 0340 bic.w r3, r3, #64 ; 0x40
8002d0a: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002d0c: 687b ldr r3, [r7, #4]
8002d0e: 4a17 ldr r2, [pc, #92] ; (8002d6c <TIM_OC2_SetConfig+0xe4>)
8002d10: 4293 cmp r3, r2
8002d12: d003 beq.n 8002d1c <TIM_OC2_SetConfig+0x94>
8002d14: 687b ldr r3, [r7, #4]
8002d16: 4a16 ldr r2, [pc, #88] ; (8002d70 <TIM_OC2_SetConfig+0xe8>)
8002d18: 4293 cmp r3, r2
8002d1a: d113 bne.n 8002d44 <TIM_OC2_SetConfig+0xbc>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8002d1c: 693b ldr r3, [r7, #16]
8002d1e: f423 6380 bic.w r3, r3, #1024 ; 0x400
8002d22: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8002d24: 693b ldr r3, [r7, #16]
8002d26: f423 6300 bic.w r3, r3, #2048 ; 0x800
8002d2a: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8002d2c: 683b ldr r3, [r7, #0]
8002d2e: 695b ldr r3, [r3, #20]
8002d30: 009b lsls r3, r3, #2
8002d32: 693a ldr r2, [r7, #16]
8002d34: 4313 orrs r3, r2
8002d36: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8002d38: 683b ldr r3, [r7, #0]
8002d3a: 699b ldr r3, [r3, #24]
8002d3c: 009b lsls r3, r3, #2
8002d3e: 693a ldr r2, [r7, #16]
8002d40: 4313 orrs r3, r2
8002d42: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002d44: 687b ldr r3, [r7, #4]
8002d46: 693a ldr r2, [r7, #16]
8002d48: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8002d4a: 687b ldr r3, [r7, #4]
8002d4c: 68fa ldr r2, [r7, #12]
8002d4e: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8002d50: 683b ldr r3, [r7, #0]
8002d52: 685a ldr r2, [r3, #4]
8002d54: 687b ldr r3, [r7, #4]
8002d56: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002d58: 687b ldr r3, [r7, #4]
8002d5a: 697a ldr r2, [r7, #20]
8002d5c: 621a str r2, [r3, #32]
}
8002d5e: bf00 nop
8002d60: 371c adds r7, #28
8002d62: 46bd mov sp, r7
8002d64: f85d 7b04 ldr.w r7, [sp], #4
8002d68: 4770 bx lr
8002d6a: bf00 nop
8002d6c: 40010000 .word 0x40010000
8002d70: 40010400 .word 0x40010400
08002d74 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8002d74: b480 push {r7}
8002d76: b087 sub sp, #28
8002d78: af00 add r7, sp, #0
8002d7a: 6078 str r0, [r7, #4]
8002d7c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8002d7e: 687b ldr r3, [r7, #4]
8002d80: 6a1b ldr r3, [r3, #32]
8002d82: f423 7280 bic.w r2, r3, #256 ; 0x100
8002d86: 687b ldr r3, [r7, #4]
8002d88: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002d8a: 687b ldr r3, [r7, #4]
8002d8c: 6a1b ldr r3, [r3, #32]
8002d8e: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002d90: 687b ldr r3, [r7, #4]
8002d92: 685b ldr r3, [r3, #4]
8002d94: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8002d96: 687b ldr r3, [r7, #4]
8002d98: 69db ldr r3, [r3, #28]
8002d9a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8002d9c: 68fb ldr r3, [r7, #12]
8002d9e: f023 0370 bic.w r3, r3, #112 ; 0x70
8002da2: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8002da4: 68fb ldr r3, [r7, #12]
8002da6: f023 0303 bic.w r3, r3, #3
8002daa: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8002dac: 683b ldr r3, [r7, #0]
8002dae: 681b ldr r3, [r3, #0]
8002db0: 68fa ldr r2, [r7, #12]
8002db2: 4313 orrs r3, r2
8002db4: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8002db6: 697b ldr r3, [r7, #20]
8002db8: f423 7300 bic.w r3, r3, #512 ; 0x200
8002dbc: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8002dbe: 683b ldr r3, [r7, #0]
8002dc0: 689b ldr r3, [r3, #8]
8002dc2: 021b lsls r3, r3, #8
8002dc4: 697a ldr r2, [r7, #20]
8002dc6: 4313 orrs r3, r2
8002dc8: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8002dca: 687b ldr r3, [r7, #4]
8002dcc: 4a21 ldr r2, [pc, #132] ; (8002e54 <TIM_OC3_SetConfig+0xe0>)
8002dce: 4293 cmp r3, r2
8002dd0: d003 beq.n 8002dda <TIM_OC3_SetConfig+0x66>
8002dd2: 687b ldr r3, [r7, #4]
8002dd4: 4a20 ldr r2, [pc, #128] ; (8002e58 <TIM_OC3_SetConfig+0xe4>)
8002dd6: 4293 cmp r3, r2
8002dd8: d10d bne.n 8002df6 <TIM_OC3_SetConfig+0x82>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8002dda: 697b ldr r3, [r7, #20]
8002ddc: f423 6300 bic.w r3, r3, #2048 ; 0x800
8002de0: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8002de2: 683b ldr r3, [r7, #0]
8002de4: 68db ldr r3, [r3, #12]
8002de6: 021b lsls r3, r3, #8
8002de8: 697a ldr r2, [r7, #20]
8002dea: 4313 orrs r3, r2
8002dec: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8002dee: 697b ldr r3, [r7, #20]
8002df0: f423 6380 bic.w r3, r3, #1024 ; 0x400
8002df4: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002df6: 687b ldr r3, [r7, #4]
8002df8: 4a16 ldr r2, [pc, #88] ; (8002e54 <TIM_OC3_SetConfig+0xe0>)
8002dfa: 4293 cmp r3, r2
8002dfc: d003 beq.n 8002e06 <TIM_OC3_SetConfig+0x92>
8002dfe: 687b ldr r3, [r7, #4]
8002e00: 4a15 ldr r2, [pc, #84] ; (8002e58 <TIM_OC3_SetConfig+0xe4>)
8002e02: 4293 cmp r3, r2
8002e04: d113 bne.n 8002e2e <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8002e06: 693b ldr r3, [r7, #16]
8002e08: f423 5380 bic.w r3, r3, #4096 ; 0x1000
8002e0c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8002e0e: 693b ldr r3, [r7, #16]
8002e10: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8002e14: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8002e16: 683b ldr r3, [r7, #0]
8002e18: 695b ldr r3, [r3, #20]
8002e1a: 011b lsls r3, r3, #4
8002e1c: 693a ldr r2, [r7, #16]
8002e1e: 4313 orrs r3, r2
8002e20: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8002e22: 683b ldr r3, [r7, #0]
8002e24: 699b ldr r3, [r3, #24]
8002e26: 011b lsls r3, r3, #4
8002e28: 693a ldr r2, [r7, #16]
8002e2a: 4313 orrs r3, r2
8002e2c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002e2e: 687b ldr r3, [r7, #4]
8002e30: 693a ldr r2, [r7, #16]
8002e32: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8002e34: 687b ldr r3, [r7, #4]
8002e36: 68fa ldr r2, [r7, #12]
8002e38: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8002e3a: 683b ldr r3, [r7, #0]
8002e3c: 685a ldr r2, [r3, #4]
8002e3e: 687b ldr r3, [r7, #4]
8002e40: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002e42: 687b ldr r3, [r7, #4]
8002e44: 697a ldr r2, [r7, #20]
8002e46: 621a str r2, [r3, #32]
}
8002e48: bf00 nop
8002e4a: 371c adds r7, #28
8002e4c: 46bd mov sp, r7
8002e4e: f85d 7b04 ldr.w r7, [sp], #4
8002e52: 4770 bx lr
8002e54: 40010000 .word 0x40010000
8002e58: 40010400 .word 0x40010400
08002e5c <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8002e5c: b480 push {r7}
8002e5e: b087 sub sp, #28
8002e60: af00 add r7, sp, #0
8002e62: 6078 str r0, [r7, #4]
8002e64: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8002e66: 687b ldr r3, [r7, #4]
8002e68: 6a1b ldr r3, [r3, #32]
8002e6a: f423 5280 bic.w r2, r3, #4096 ; 0x1000
8002e6e: 687b ldr r3, [r7, #4]
8002e70: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002e72: 687b ldr r3, [r7, #4]
8002e74: 6a1b ldr r3, [r3, #32]
8002e76: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002e78: 687b ldr r3, [r7, #4]
8002e7a: 685b ldr r3, [r3, #4]
8002e7c: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8002e7e: 687b ldr r3, [r7, #4]
8002e80: 69db ldr r3, [r3, #28]
8002e82: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8002e84: 68fb ldr r3, [r7, #12]
8002e86: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8002e8a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8002e8c: 68fb ldr r3, [r7, #12]
8002e8e: f423 7340 bic.w r3, r3, #768 ; 0x300
8002e92: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8002e94: 683b ldr r3, [r7, #0]
8002e96: 681b ldr r3, [r3, #0]
8002e98: 021b lsls r3, r3, #8
8002e9a: 68fa ldr r2, [r7, #12]
8002e9c: 4313 orrs r3, r2
8002e9e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8002ea0: 693b ldr r3, [r7, #16]
8002ea2: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8002ea6: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8002ea8: 683b ldr r3, [r7, #0]
8002eaa: 689b ldr r3, [r3, #8]
8002eac: 031b lsls r3, r3, #12
8002eae: 693a ldr r2, [r7, #16]
8002eb0: 4313 orrs r3, r2
8002eb2: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002eb4: 687b ldr r3, [r7, #4]
8002eb6: 4a12 ldr r2, [pc, #72] ; (8002f00 <TIM_OC4_SetConfig+0xa4>)
8002eb8: 4293 cmp r3, r2
8002eba: d003 beq.n 8002ec4 <TIM_OC4_SetConfig+0x68>
8002ebc: 687b ldr r3, [r7, #4]
8002ebe: 4a11 ldr r2, [pc, #68] ; (8002f04 <TIM_OC4_SetConfig+0xa8>)
8002ec0: 4293 cmp r3, r2
8002ec2: d109 bne.n 8002ed8 <TIM_OC4_SetConfig+0x7c>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8002ec4: 697b ldr r3, [r7, #20]
8002ec6: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8002eca: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8002ecc: 683b ldr r3, [r7, #0]
8002ece: 695b ldr r3, [r3, #20]
8002ed0: 019b lsls r3, r3, #6
8002ed2: 697a ldr r2, [r7, #20]
8002ed4: 4313 orrs r3, r2
8002ed6: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002ed8: 687b ldr r3, [r7, #4]
8002eda: 697a ldr r2, [r7, #20]
8002edc: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8002ede: 687b ldr r3, [r7, #4]
8002ee0: 68fa ldr r2, [r7, #12]
8002ee2: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8002ee4: 683b ldr r3, [r7, #0]
8002ee6: 685a ldr r2, [r3, #4]
8002ee8: 687b ldr r3, [r7, #4]
8002eea: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002eec: 687b ldr r3, [r7, #4]
8002eee: 693a ldr r2, [r7, #16]
8002ef0: 621a str r2, [r3, #32]
}
8002ef2: bf00 nop
8002ef4: 371c adds r7, #28
8002ef6: 46bd mov sp, r7
8002ef8: f85d 7b04 ldr.w r7, [sp], #4
8002efc: 4770 bx lr
8002efe: bf00 nop
8002f00: 40010000 .word 0x40010000
8002f04: 40010400 .word 0x40010400
08002f08 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8002f08: b480 push {r7}
8002f0a: b087 sub sp, #28
8002f0c: af00 add r7, sp, #0
8002f0e: 60f8 str r0, [r7, #12]
8002f10: 60b9 str r1, [r7, #8]
8002f12: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8002f14: 68fb ldr r3, [r7, #12]
8002f16: 6a1b ldr r3, [r3, #32]
8002f18: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8002f1a: 68fb ldr r3, [r7, #12]
8002f1c: 6a1b ldr r3, [r3, #32]
8002f1e: f023 0201 bic.w r2, r3, #1
8002f22: 68fb ldr r3, [r7, #12]
8002f24: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8002f26: 68fb ldr r3, [r7, #12]
8002f28: 699b ldr r3, [r3, #24]
8002f2a: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8002f2c: 693b ldr r3, [r7, #16]
8002f2e: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8002f32: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8002f34: 687b ldr r3, [r7, #4]
8002f36: 011b lsls r3, r3, #4
8002f38: 693a ldr r2, [r7, #16]
8002f3a: 4313 orrs r3, r2
8002f3c: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8002f3e: 697b ldr r3, [r7, #20]
8002f40: f023 030a bic.w r3, r3, #10
8002f44: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8002f46: 697a ldr r2, [r7, #20]
8002f48: 68bb ldr r3, [r7, #8]
8002f4a: 4313 orrs r3, r2
8002f4c: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8002f4e: 68fb ldr r3, [r7, #12]
8002f50: 693a ldr r2, [r7, #16]
8002f52: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8002f54: 68fb ldr r3, [r7, #12]
8002f56: 697a ldr r2, [r7, #20]
8002f58: 621a str r2, [r3, #32]
}
8002f5a: bf00 nop
8002f5c: 371c adds r7, #28
8002f5e: 46bd mov sp, r7
8002f60: f85d 7b04 ldr.w r7, [sp], #4
8002f64: 4770 bx lr
08002f66 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8002f66: b480 push {r7}
8002f68: b087 sub sp, #28
8002f6a: af00 add r7, sp, #0
8002f6c: 60f8 str r0, [r7, #12]
8002f6e: 60b9 str r1, [r7, #8]
8002f70: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8002f72: 68fb ldr r3, [r7, #12]
8002f74: 6a1b ldr r3, [r3, #32]
8002f76: f023 0210 bic.w r2, r3, #16
8002f7a: 68fb ldr r3, [r7, #12]
8002f7c: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8002f7e: 68fb ldr r3, [r7, #12]
8002f80: 699b ldr r3, [r3, #24]
8002f82: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
8002f84: 68fb ldr r3, [r7, #12]
8002f86: 6a1b ldr r3, [r3, #32]
8002f88: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8002f8a: 697b ldr r3, [r7, #20]
8002f8c: f423 4370 bic.w r3, r3, #61440 ; 0xf000
8002f90: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
8002f92: 687b ldr r3, [r7, #4]
8002f94: 031b lsls r3, r3, #12
8002f96: 697a ldr r2, [r7, #20]
8002f98: 4313 orrs r3, r2
8002f9a: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8002f9c: 693b ldr r3, [r7, #16]
8002f9e: f023 03a0 bic.w r3, r3, #160 ; 0xa0
8002fa2: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
8002fa4: 68bb ldr r3, [r7, #8]
8002fa6: 011b lsls r3, r3, #4
8002fa8: 693a ldr r2, [r7, #16]
8002faa: 4313 orrs r3, r2
8002fac: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8002fae: 68fb ldr r3, [r7, #12]
8002fb0: 697a ldr r2, [r7, #20]
8002fb2: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8002fb4: 68fb ldr r3, [r7, #12]
8002fb6: 693a ldr r2, [r7, #16]
8002fb8: 621a str r2, [r3, #32]
}
8002fba: bf00 nop
8002fbc: 371c adds r7, #28
8002fbe: 46bd mov sp, r7
8002fc0: f85d 7b04 ldr.w r7, [sp], #4
8002fc4: 4770 bx lr
08002fc6 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8002fc6: b480 push {r7}
8002fc8: b085 sub sp, #20
8002fca: af00 add r7, sp, #0
8002fcc: 6078 str r0, [r7, #4]
8002fce: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8002fd0: 687b ldr r3, [r7, #4]
8002fd2: 689b ldr r3, [r3, #8]
8002fd4: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8002fd6: 68fb ldr r3, [r7, #12]
8002fd8: f023 0370 bic.w r3, r3, #112 ; 0x70
8002fdc: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8002fde: 683a ldr r2, [r7, #0]
8002fe0: 68fb ldr r3, [r7, #12]
8002fe2: 4313 orrs r3, r2
8002fe4: f043 0307 orr.w r3, r3, #7
8002fe8: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8002fea: 687b ldr r3, [r7, #4]
8002fec: 68fa ldr r2, [r7, #12]
8002fee: 609a str r2, [r3, #8]
}
8002ff0: bf00 nop
8002ff2: 3714 adds r7, #20
8002ff4: 46bd mov sp, r7
8002ff6: f85d 7b04 ldr.w r7, [sp], #4
8002ffa: 4770 bx lr
08002ffc <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8002ffc: b480 push {r7}
8002ffe: b087 sub sp, #28
8003000: af00 add r7, sp, #0
8003002: 60f8 str r0, [r7, #12]
8003004: 60b9 str r1, [r7, #8]
8003006: 607a str r2, [r7, #4]
8003008: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
800300a: 68fb ldr r3, [r7, #12]
800300c: 689b ldr r3, [r3, #8]
800300e: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8003010: 697b ldr r3, [r7, #20]
8003012: f423 437f bic.w r3, r3, #65280 ; 0xff00
8003016: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8003018: 683b ldr r3, [r7, #0]
800301a: 021a lsls r2, r3, #8
800301c: 687b ldr r3, [r7, #4]
800301e: 431a orrs r2, r3
8003020: 68bb ldr r3, [r7, #8]
8003022: 4313 orrs r3, r2
8003024: 697a ldr r2, [r7, #20]
8003026: 4313 orrs r3, r2
8003028: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800302a: 68fb ldr r3, [r7, #12]
800302c: 697a ldr r2, [r7, #20]
800302e: 609a str r2, [r3, #8]
}
8003030: bf00 nop
8003032: 371c adds r7, #28
8003034: 46bd mov sp, r7
8003036: f85d 7b04 ldr.w r7, [sp], #4
800303a: 4770 bx lr
0800303c <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
800303c: b480 push {r7}
800303e: b087 sub sp, #28
8003040: af00 add r7, sp, #0
8003042: 60f8 str r0, [r7, #12]
8003044: 60b9 str r1, [r7, #8]
8003046: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8003048: 68bb ldr r3, [r7, #8]
800304a: f003 031f and.w r3, r3, #31
800304e: 2201 movs r2, #1
8003050: fa02 f303 lsl.w r3, r2, r3
8003054: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8003056: 68fb ldr r3, [r7, #12]
8003058: 6a1a ldr r2, [r3, #32]
800305a: 697b ldr r3, [r7, #20]
800305c: 43db mvns r3, r3
800305e: 401a ands r2, r3
8003060: 68fb ldr r3, [r7, #12]
8003062: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8003064: 68fb ldr r3, [r7, #12]
8003066: 6a1a ldr r2, [r3, #32]
8003068: 68bb ldr r3, [r7, #8]
800306a: f003 031f and.w r3, r3, #31
800306e: 6879 ldr r1, [r7, #4]
8003070: fa01 f303 lsl.w r3, r1, r3
8003074: 431a orrs r2, r3
8003076: 68fb ldr r3, [r7, #12]
8003078: 621a str r2, [r3, #32]
}
800307a: bf00 nop
800307c: 371c adds r7, #28
800307e: 46bd mov sp, r7
8003080: f85d 7b04 ldr.w r7, [sp], #4
8003084: 4770 bx lr
...
08003088 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
8003088: b480 push {r7}
800308a: b085 sub sp, #20
800308c: af00 add r7, sp, #0
800308e: 6078 str r0, [r7, #4]
8003090: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8003092: 687b ldr r3, [r7, #4]
8003094: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8003098: 2b01 cmp r3, #1
800309a: d101 bne.n 80030a0 <HAL_TIMEx_MasterConfigSynchronization+0x18>
800309c: 2302 movs r3, #2
800309e: e05a b.n 8003156 <HAL_TIMEx_MasterConfigSynchronization+0xce>
80030a0: 687b ldr r3, [r7, #4]
80030a2: 2201 movs r2, #1
80030a4: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80030a8: 687b ldr r3, [r7, #4]
80030aa: 2202 movs r2, #2
80030ac: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80030b0: 687b ldr r3, [r7, #4]
80030b2: 681b ldr r3, [r3, #0]
80030b4: 685b ldr r3, [r3, #4]
80030b6: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80030b8: 687b ldr r3, [r7, #4]
80030ba: 681b ldr r3, [r3, #0]
80030bc: 689b ldr r3, [r3, #8]
80030be: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
80030c0: 68fb ldr r3, [r7, #12]
80030c2: f023 0370 bic.w r3, r3, #112 ; 0x70
80030c6: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
80030c8: 683b ldr r3, [r7, #0]
80030ca: 681b ldr r3, [r3, #0]
80030cc: 68fa ldr r2, [r7, #12]
80030ce: 4313 orrs r3, r2
80030d0: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
80030d2: 687b ldr r3, [r7, #4]
80030d4: 681b ldr r3, [r3, #0]
80030d6: 68fa ldr r2, [r7, #12]
80030d8: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80030da: 687b ldr r3, [r7, #4]
80030dc: 681b ldr r3, [r3, #0]
80030de: 4a21 ldr r2, [pc, #132] ; (8003164 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
80030e0: 4293 cmp r3, r2
80030e2: d022 beq.n 800312a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80030e4: 687b ldr r3, [r7, #4]
80030e6: 681b ldr r3, [r3, #0]
80030e8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80030ec: d01d beq.n 800312a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80030ee: 687b ldr r3, [r7, #4]
80030f0: 681b ldr r3, [r3, #0]
80030f2: 4a1d ldr r2, [pc, #116] ; (8003168 <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
80030f4: 4293 cmp r3, r2
80030f6: d018 beq.n 800312a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80030f8: 687b ldr r3, [r7, #4]
80030fa: 681b ldr r3, [r3, #0]
80030fc: 4a1b ldr r2, [pc, #108] ; (800316c <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
80030fe: 4293 cmp r3, r2
8003100: d013 beq.n 800312a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8003102: 687b ldr r3, [r7, #4]
8003104: 681b ldr r3, [r3, #0]
8003106: 4a1a ldr r2, [pc, #104] ; (8003170 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
8003108: 4293 cmp r3, r2
800310a: d00e beq.n 800312a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
800310c: 687b ldr r3, [r7, #4]
800310e: 681b ldr r3, [r3, #0]
8003110: 4a18 ldr r2, [pc, #96] ; (8003174 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
8003112: 4293 cmp r3, r2
8003114: d009 beq.n 800312a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8003116: 687b ldr r3, [r7, #4]
8003118: 681b ldr r3, [r3, #0]
800311a: 4a17 ldr r2, [pc, #92] ; (8003178 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
800311c: 4293 cmp r3, r2
800311e: d004 beq.n 800312a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8003120: 687b ldr r3, [r7, #4]
8003122: 681b ldr r3, [r3, #0]
8003124: 4a15 ldr r2, [pc, #84] ; (800317c <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
8003126: 4293 cmp r3, r2
8003128: d10c bne.n 8003144 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800312a: 68bb ldr r3, [r7, #8]
800312c: f023 0380 bic.w r3, r3, #128 ; 0x80
8003130: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8003132: 683b ldr r3, [r7, #0]
8003134: 685b ldr r3, [r3, #4]
8003136: 68ba ldr r2, [r7, #8]
8003138: 4313 orrs r3, r2
800313a: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800313c: 687b ldr r3, [r7, #4]
800313e: 681b ldr r3, [r3, #0]
8003140: 68ba ldr r2, [r7, #8]
8003142: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8003144: 687b ldr r3, [r7, #4]
8003146: 2201 movs r2, #1
8003148: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800314c: 687b ldr r3, [r7, #4]
800314e: 2200 movs r2, #0
8003150: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8003154: 2300 movs r3, #0
}
8003156: 4618 mov r0, r3
8003158: 3714 adds r7, #20
800315a: 46bd mov sp, r7
800315c: f85d 7b04 ldr.w r7, [sp], #4
8003160: 4770 bx lr
8003162: bf00 nop
8003164: 40010000 .word 0x40010000
8003168: 40000400 .word 0x40000400
800316c: 40000800 .word 0x40000800
8003170: 40000c00 .word 0x40000c00
8003174: 40010400 .word 0x40010400
8003178: 40014000 .word 0x40014000
800317c: 40001800 .word 0x40001800
08003180 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
8003180: b480 push {r7}
8003182: b085 sub sp, #20
8003184: af00 add r7, sp, #0
8003186: 6078 str r0, [r7, #4]
8003188: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
800318a: 2300 movs r3, #0
800318c: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
800318e: 687b ldr r3, [r7, #4]
8003190: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8003194: 2b01 cmp r3, #1
8003196: d101 bne.n 800319c <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
8003198: 2302 movs r3, #2
800319a: e03d b.n 8003218 <HAL_TIMEx_ConfigBreakDeadTime+0x98>
800319c: 687b ldr r3, [r7, #4]
800319e: 2201 movs r2, #1
80031a0: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
80031a4: 68fb ldr r3, [r7, #12]
80031a6: f023 02ff bic.w r2, r3, #255 ; 0xff
80031aa: 683b ldr r3, [r7, #0]
80031ac: 68db ldr r3, [r3, #12]
80031ae: 4313 orrs r3, r2
80031b0: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
80031b2: 68fb ldr r3, [r7, #12]
80031b4: f423 7240 bic.w r2, r3, #768 ; 0x300
80031b8: 683b ldr r3, [r7, #0]
80031ba: 689b ldr r3, [r3, #8]
80031bc: 4313 orrs r3, r2
80031be: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
80031c0: 68fb ldr r3, [r7, #12]
80031c2: f423 6280 bic.w r2, r3, #1024 ; 0x400
80031c6: 683b ldr r3, [r7, #0]
80031c8: 685b ldr r3, [r3, #4]
80031ca: 4313 orrs r3, r2
80031cc: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
80031ce: 68fb ldr r3, [r7, #12]
80031d0: f423 6200 bic.w r2, r3, #2048 ; 0x800
80031d4: 683b ldr r3, [r7, #0]
80031d6: 681b ldr r3, [r3, #0]
80031d8: 4313 orrs r3, r2
80031da: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
80031dc: 68fb ldr r3, [r7, #12]
80031de: f423 5280 bic.w r2, r3, #4096 ; 0x1000
80031e2: 683b ldr r3, [r7, #0]
80031e4: 691b ldr r3, [r3, #16]
80031e6: 4313 orrs r3, r2
80031e8: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
80031ea: 68fb ldr r3, [r7, #12]
80031ec: f423 5200 bic.w r2, r3, #8192 ; 0x2000
80031f0: 683b ldr r3, [r7, #0]
80031f2: 695b ldr r3, [r3, #20]
80031f4: 4313 orrs r3, r2
80031f6: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
80031f8: 68fb ldr r3, [r7, #12]
80031fa: f423 4280 bic.w r2, r3, #16384 ; 0x4000
80031fe: 683b ldr r3, [r7, #0]
8003200: 69db ldr r3, [r3, #28]
8003202: 4313 orrs r3, r2
8003204: 60fb str r3, [r7, #12]
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
8003206: 687b ldr r3, [r7, #4]
8003208: 681b ldr r3, [r3, #0]
800320a: 68fa ldr r2, [r7, #12]
800320c: 645a str r2, [r3, #68] ; 0x44
__HAL_UNLOCK(htim);
800320e: 687b ldr r3, [r7, #4]
8003210: 2200 movs r2, #0
8003212: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8003216: 2300 movs r3, #0
}
8003218: 4618 mov r0, r3
800321a: 3714 adds r7, #20
800321c: 46bd mov sp, r7
800321e: f85d 7b04 ldr.w r7, [sp], #4
8003222: 4770 bx lr
08003224 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8003224: b480 push {r7}
8003226: b083 sub sp, #12
8003228: af00 add r7, sp, #0
800322a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
800322c: bf00 nop
800322e: 370c adds r7, #12
8003230: 46bd mov sp, r7
8003232: f85d 7b04 ldr.w r7, [sp], #4
8003236: 4770 bx lr
08003238 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8003238: b480 push {r7}
800323a: b083 sub sp, #12
800323c: af00 add r7, sp, #0
800323e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8003240: bf00 nop
8003242: 370c adds r7, #12
8003244: 46bd mov sp, r7
8003246: f85d 7b04 ldr.w r7, [sp], #4
800324a: 4770 bx lr
0800324c <memset>:
800324c: 4402 add r2, r0
800324e: 4603 mov r3, r0
8003250: 4293 cmp r3, r2
8003252: d100 bne.n 8003256 <memset+0xa>
8003254: 4770 bx lr
8003256: f803 1b01 strb.w r1, [r3], #1
800325a: e7f9 b.n 8003250 <memset+0x4>
0800325c <__libc_init_array>:
800325c: b570 push {r4, r5, r6, lr}
800325e: 4d0d ldr r5, [pc, #52] ; (8003294 <__libc_init_array+0x38>)
8003260: 4c0d ldr r4, [pc, #52] ; (8003298 <__libc_init_array+0x3c>)
8003262: 1b64 subs r4, r4, r5
8003264: 10a4 asrs r4, r4, #2
8003266: 2600 movs r6, #0
8003268: 42a6 cmp r6, r4
800326a: d109 bne.n 8003280 <__libc_init_array+0x24>
800326c: 4d0b ldr r5, [pc, #44] ; (800329c <__libc_init_array+0x40>)
800326e: 4c0c ldr r4, [pc, #48] ; (80032a0 <__libc_init_array+0x44>)
8003270: f000 f818 bl 80032a4 <_init>
8003274: 1b64 subs r4, r4, r5
8003276: 10a4 asrs r4, r4, #2
8003278: 2600 movs r6, #0
800327a: 42a6 cmp r6, r4
800327c: d105 bne.n 800328a <__libc_init_array+0x2e>
800327e: bd70 pop {r4, r5, r6, pc}
8003280: f855 3b04 ldr.w r3, [r5], #4
8003284: 4798 blx r3
8003286: 3601 adds r6, #1
8003288: e7ee b.n 8003268 <__libc_init_array+0xc>
800328a: f855 3b04 ldr.w r3, [r5], #4
800328e: 4798 blx r3
8003290: 3601 adds r6, #1
8003292: e7f2 b.n 800327a <__libc_init_array+0x1e>
8003294: 080032d4 .word 0x080032d4
8003298: 080032d4 .word 0x080032d4
800329c: 080032d4 .word 0x080032d4
80032a0: 080032d8 .word 0x080032d8
080032a4 <_init>:
80032a4: b5f8 push {r3, r4, r5, r6, r7, lr}
80032a6: bf00 nop
80032a8: bcf8 pop {r3, r4, r5, r6, r7}
80032aa: bc08 pop {r3}
80032ac: 469e mov lr, r3
80032ae: 4770 bx lr
080032b0 <_fini>:
80032b0: b5f8 push {r3, r4, r5, r6, r7, lr}
80032b2: bf00 nop
80032b4: bcf8 pop {r3, r4, r5, r6, r7}
80032b6: bc08 pop {r3}
80032b8: 469e mov lr, r3
80032ba: 4770 bx lr
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