STM_gen.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000188 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00002e08 08000188 08000188 00010188 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000010 08002f90 08002f90 00012f90 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08002fa0 08002fa0 00020010 2**0 CONTENTS 4 .ARM 00000008 08002fa0 08002fa0 00012fa0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08002fa8 08002fa8 00020010 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08002fa8 08002fa8 00012fa8 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08002fac 08002fac 00012fac 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000010 20000000 08002fb0 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .ccmram 00000000 10000000 10000000 00020010 2**0 CONTENTS 10 .bss 000000cc 20000010 20000010 00020010 2**2 ALLOC 11 ._user_heap_stack 00000604 200000dc 200000dc 00020010 2**0 ALLOC 12 .ARM.attributes 00000030 00000000 00000000 00020010 2**0 CONTENTS, READONLY 13 .comment 00000043 00000000 00000000 00020040 2**0 CONTENTS, READONLY 14 .debug_info 00009539 00000000 00000000 00020083 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_abbrev 000016c1 00000000 00000000 000295bc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_loclists 000001d4 00000000 00000000 0002ac7d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_aranges 00000968 00000000 00000000 0002ae58 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_rnglists 00000761 00000000 00000000 0002b7c0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_macro 000205a2 00000000 00000000 0002bf21 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .debug_line 0000a638 00000000 00000000 0004c4c3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_str 000c4917 00000000 00000000 00056afb 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_frame 00002728 00000000 00000000 0011b414 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 23 .debug_line_str 0000004b 00000000 00000000 0011db3c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000188 <__do_global_dtors_aux>: 8000188: b510 push {r4, lr} 800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>) 800018c: 7823 ldrb r3, [r4, #0] 800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16> 8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>) 8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12> 8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>) 8000196: f3af 8000 nop.w 800019a: 2301 movs r3, #1 800019c: 7023 strb r3, [r4, #0] 800019e: bd10 pop {r4, pc} 80001a0: 20000010 .word 0x20000010 80001a4: 00000000 .word 0x00000000 80001a8: 08002f78 .word 0x08002f78 080001ac : 80001ac: b508 push {r3, lr} 80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc ) 80001b0: b11b cbz r3, 80001ba 80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 ) 80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 ) 80001b6: f3af 8000 nop.w 80001ba: bd08 pop {r3, pc} 80001bc: 00000000 .word 0x00000000 80001c0: 20000014 .word 0x20000014 80001c4: 08002f78 .word 0x08002f78 080001c8 <__aeabi_uldivmod>: 80001c8: b953 cbnz r3, 80001e0 <__aeabi_uldivmod+0x18> 80001ca: b94a cbnz r2, 80001e0 <__aeabi_uldivmod+0x18> 80001cc: 2900 cmp r1, #0 80001ce: bf08 it eq 80001d0: 2800 cmpeq r0, #0 80001d2: bf1c itt ne 80001d4: f04f 31ff movne.w r1, #4294967295 80001d8: f04f 30ff movne.w r0, #4294967295 80001dc: f000 b970 b.w 80004c0 <__aeabi_idiv0> 80001e0: f1ad 0c08 sub.w ip, sp, #8 80001e4: e96d ce04 strd ip, lr, [sp, #-16]! 80001e8: f000 f806 bl 80001f8 <__udivmoddi4> 80001ec: f8dd e004 ldr.w lr, [sp, #4] 80001f0: e9dd 2302 ldrd r2, r3, [sp, #8] 80001f4: b004 add sp, #16 80001f6: 4770 bx lr 080001f8 <__udivmoddi4>: 80001f8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80001fc: 9e08 ldr r6, [sp, #32] 80001fe: 460d mov r5, r1 8000200: 4604 mov r4, r0 8000202: 460f mov r7, r1 8000204: 2b00 cmp r3, #0 8000206: d14a bne.n 800029e <__udivmoddi4+0xa6> 8000208: 428a cmp r2, r1 800020a: 4694 mov ip, r2 800020c: d965 bls.n 80002da <__udivmoddi4+0xe2> 800020e: fab2 f382 clz r3, r2 8000212: b143 cbz r3, 8000226 <__udivmoddi4+0x2e> 8000214: fa02 fc03 lsl.w ip, r2, r3 8000218: f1c3 0220 rsb r2, r3, #32 800021c: 409f lsls r7, r3 800021e: fa20 f202 lsr.w r2, r0, r2 8000222: 4317 orrs r7, r2 8000224: 409c lsls r4, r3 8000226: ea4f 4e1c mov.w lr, ip, lsr #16 800022a: fa1f f58c uxth.w r5, ip 800022e: fbb7 f1fe udiv r1, r7, lr 8000232: 0c22 lsrs r2, r4, #16 8000234: fb0e 7711 mls r7, lr, r1, r7 8000238: ea42 4207 orr.w r2, r2, r7, lsl #16 800023c: fb01 f005 mul.w r0, r1, r5 8000240: 4290 cmp r0, r2 8000242: d90a bls.n 800025a <__udivmoddi4+0x62> 8000244: eb1c 0202 adds.w r2, ip, r2 8000248: f101 37ff add.w r7, r1, #4294967295 800024c: f080 811c bcs.w 8000488 <__udivmoddi4+0x290> 8000250: 4290 cmp r0, r2 8000252: f240 8119 bls.w 8000488 <__udivmoddi4+0x290> 8000256: 3902 subs r1, #2 8000258: 4462 add r2, ip 800025a: 1a12 subs r2, r2, r0 800025c: b2a4 uxth r4, r4 800025e: fbb2 f0fe udiv r0, r2, lr 8000262: fb0e 2210 mls r2, lr, r0, r2 8000266: ea44 4402 orr.w r4, r4, r2, lsl #16 800026a: fb00 f505 mul.w r5, r0, r5 800026e: 42a5 cmp r5, r4 8000270: d90a bls.n 8000288 <__udivmoddi4+0x90> 8000272: eb1c 0404 adds.w r4, ip, r4 8000276: f100 32ff add.w r2, r0, #4294967295 800027a: f080 8107 bcs.w 800048c <__udivmoddi4+0x294> 800027e: 42a5 cmp r5, r4 8000280: f240 8104 bls.w 800048c <__udivmoddi4+0x294> 8000284: 4464 add r4, ip 8000286: 3802 subs r0, #2 8000288: ea40 4001 orr.w r0, r0, r1, lsl #16 800028c: 1b64 subs r4, r4, r5 800028e: 2100 movs r1, #0 8000290: b11e cbz r6, 800029a <__udivmoddi4+0xa2> 8000292: 40dc lsrs r4, r3 8000294: 2300 movs r3, #0 8000296: e9c6 4300 strd r4, r3, [r6] 800029a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800029e: 428b cmp r3, r1 80002a0: d908 bls.n 80002b4 <__udivmoddi4+0xbc> 80002a2: 2e00 cmp r6, #0 80002a4: f000 80ed beq.w 8000482 <__udivmoddi4+0x28a> 80002a8: 2100 movs r1, #0 80002aa: e9c6 0500 strd r0, r5, [r6] 80002ae: 4608 mov r0, r1 80002b0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002b4: fab3 f183 clz r1, r3 80002b8: 2900 cmp r1, #0 80002ba: d149 bne.n 8000350 <__udivmoddi4+0x158> 80002bc: 42ab cmp r3, r5 80002be: d302 bcc.n 80002c6 <__udivmoddi4+0xce> 80002c0: 4282 cmp r2, r0 80002c2: f200 80f8 bhi.w 80004b6 <__udivmoddi4+0x2be> 80002c6: 1a84 subs r4, r0, r2 80002c8: eb65 0203 sbc.w r2, r5, r3 80002cc: 2001 movs r0, #1 80002ce: 4617 mov r7, r2 80002d0: 2e00 cmp r6, #0 80002d2: d0e2 beq.n 800029a <__udivmoddi4+0xa2> 80002d4: e9c6 4700 strd r4, r7, [r6] 80002d8: e7df b.n 800029a <__udivmoddi4+0xa2> 80002da: b902 cbnz r2, 80002de <__udivmoddi4+0xe6> 80002dc: deff udf #255 ; 0xff 80002de: fab2 f382 clz r3, r2 80002e2: 2b00 cmp r3, #0 80002e4: f040 8090 bne.w 8000408 <__udivmoddi4+0x210> 80002e8: 1a8a subs r2, r1, r2 80002ea: ea4f 471c mov.w r7, ip, lsr #16 80002ee: fa1f fe8c uxth.w lr, ip 80002f2: 2101 movs r1, #1 80002f4: fbb2 f5f7 udiv r5, r2, r7 80002f8: fb07 2015 mls r0, r7, r5, r2 80002fc: 0c22 lsrs r2, r4, #16 80002fe: ea42 4200 orr.w r2, r2, r0, lsl #16 8000302: fb0e f005 mul.w r0, lr, r5 8000306: 4290 cmp r0, r2 8000308: d908 bls.n 800031c <__udivmoddi4+0x124> 800030a: eb1c 0202 adds.w r2, ip, r2 800030e: f105 38ff add.w r8, r5, #4294967295 8000312: d202 bcs.n 800031a <__udivmoddi4+0x122> 8000314: 4290 cmp r0, r2 8000316: f200 80cb bhi.w 80004b0 <__udivmoddi4+0x2b8> 800031a: 4645 mov r5, r8 800031c: 1a12 subs r2, r2, r0 800031e: b2a4 uxth r4, r4 8000320: fbb2 f0f7 udiv r0, r2, r7 8000324: fb07 2210 mls r2, r7, r0, r2 8000328: ea44 4402 orr.w r4, r4, r2, lsl #16 800032c: fb0e fe00 mul.w lr, lr, r0 8000330: 45a6 cmp lr, r4 8000332: d908 bls.n 8000346 <__udivmoddi4+0x14e> 8000334: eb1c 0404 adds.w r4, ip, r4 8000338: f100 32ff add.w r2, r0, #4294967295 800033c: d202 bcs.n 8000344 <__udivmoddi4+0x14c> 800033e: 45a6 cmp lr, r4 8000340: f200 80bb bhi.w 80004ba <__udivmoddi4+0x2c2> 8000344: 4610 mov r0, r2 8000346: eba4 040e sub.w r4, r4, lr 800034a: ea40 4005 orr.w r0, r0, r5, lsl #16 800034e: e79f b.n 8000290 <__udivmoddi4+0x98> 8000350: f1c1 0720 rsb r7, r1, #32 8000354: 408b lsls r3, r1 8000356: fa22 fc07 lsr.w ip, r2, r7 800035a: ea4c 0c03 orr.w ip, ip, r3 800035e: fa05 f401 lsl.w r4, r5, r1 8000362: fa20 f307 lsr.w r3, r0, r7 8000366: 40fd lsrs r5, r7 8000368: ea4f 491c mov.w r9, ip, lsr #16 800036c: 4323 orrs r3, r4 800036e: fbb5 f8f9 udiv r8, r5, r9 8000372: fa1f fe8c uxth.w lr, ip 8000376: fb09 5518 mls r5, r9, r8, r5 800037a: 0c1c lsrs r4, r3, #16 800037c: ea44 4405 orr.w r4, r4, r5, lsl #16 8000380: fb08 f50e mul.w r5, r8, lr 8000384: 42a5 cmp r5, r4 8000386: fa02 f201 lsl.w r2, r2, r1 800038a: fa00 f001 lsl.w r0, r0, r1 800038e: d90b bls.n 80003a8 <__udivmoddi4+0x1b0> 8000390: eb1c 0404 adds.w r4, ip, r4 8000394: f108 3aff add.w sl, r8, #4294967295 8000398: f080 8088 bcs.w 80004ac <__udivmoddi4+0x2b4> 800039c: 42a5 cmp r5, r4 800039e: f240 8085 bls.w 80004ac <__udivmoddi4+0x2b4> 80003a2: f1a8 0802 sub.w r8, r8, #2 80003a6: 4464 add r4, ip 80003a8: 1b64 subs r4, r4, r5 80003aa: b29d uxth r5, r3 80003ac: fbb4 f3f9 udiv r3, r4, r9 80003b0: fb09 4413 mls r4, r9, r3, r4 80003b4: ea45 4404 orr.w r4, r5, r4, lsl #16 80003b8: fb03 fe0e mul.w lr, r3, lr 80003bc: 45a6 cmp lr, r4 80003be: d908 bls.n 80003d2 <__udivmoddi4+0x1da> 80003c0: eb1c 0404 adds.w r4, ip, r4 80003c4: f103 35ff add.w r5, r3, #4294967295 80003c8: d26c bcs.n 80004a4 <__udivmoddi4+0x2ac> 80003ca: 45a6 cmp lr, r4 80003cc: d96a bls.n 80004a4 <__udivmoddi4+0x2ac> 80003ce: 3b02 subs r3, #2 80003d0: 4464 add r4, ip 80003d2: ea43 4308 orr.w r3, r3, r8, lsl #16 80003d6: fba3 9502 umull r9, r5, r3, r2 80003da: eba4 040e sub.w r4, r4, lr 80003de: 42ac cmp r4, r5 80003e0: 46c8 mov r8, r9 80003e2: 46ae mov lr, r5 80003e4: d356 bcc.n 8000494 <__udivmoddi4+0x29c> 80003e6: d053 beq.n 8000490 <__udivmoddi4+0x298> 80003e8: b156 cbz r6, 8000400 <__udivmoddi4+0x208> 80003ea: ebb0 0208 subs.w r2, r0, r8 80003ee: eb64 040e sbc.w r4, r4, lr 80003f2: fa04 f707 lsl.w r7, r4, r7 80003f6: 40ca lsrs r2, r1 80003f8: 40cc lsrs r4, r1 80003fa: 4317 orrs r7, r2 80003fc: e9c6 7400 strd r7, r4, [r6] 8000400: 4618 mov r0, r3 8000402: 2100 movs r1, #0 8000404: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8000408: f1c3 0120 rsb r1, r3, #32 800040c: fa02 fc03 lsl.w ip, r2, r3 8000410: fa20 f201 lsr.w r2, r0, r1 8000414: fa25 f101 lsr.w r1, r5, r1 8000418: 409d lsls r5, r3 800041a: 432a orrs r2, r5 800041c: ea4f 471c mov.w r7, ip, lsr #16 8000420: fa1f fe8c uxth.w lr, ip 8000424: fbb1 f0f7 udiv r0, r1, r7 8000428: fb07 1510 mls r5, r7, r0, r1 800042c: 0c11 lsrs r1, r2, #16 800042e: ea41 4105 orr.w r1, r1, r5, lsl #16 8000432: fb00 f50e mul.w r5, r0, lr 8000436: 428d cmp r5, r1 8000438: fa04 f403 lsl.w r4, r4, r3 800043c: d908 bls.n 8000450 <__udivmoddi4+0x258> 800043e: eb1c 0101 adds.w r1, ip, r1 8000442: f100 38ff add.w r8, r0, #4294967295 8000446: d22f bcs.n 80004a8 <__udivmoddi4+0x2b0> 8000448: 428d cmp r5, r1 800044a: d92d bls.n 80004a8 <__udivmoddi4+0x2b0> 800044c: 3802 subs r0, #2 800044e: 4461 add r1, ip 8000450: 1b49 subs r1, r1, r5 8000452: b292 uxth r2, r2 8000454: fbb1 f5f7 udiv r5, r1, r7 8000458: fb07 1115 mls r1, r7, r5, r1 800045c: ea42 4201 orr.w r2, r2, r1, lsl #16 8000460: fb05 f10e mul.w r1, r5, lr 8000464: 4291 cmp r1, r2 8000466: d908 bls.n 800047a <__udivmoddi4+0x282> 8000468: eb1c 0202 adds.w r2, ip, r2 800046c: f105 38ff add.w r8, r5, #4294967295 8000470: d216 bcs.n 80004a0 <__udivmoddi4+0x2a8> 8000472: 4291 cmp r1, r2 8000474: d914 bls.n 80004a0 <__udivmoddi4+0x2a8> 8000476: 3d02 subs r5, #2 8000478: 4462 add r2, ip 800047a: 1a52 subs r2, r2, r1 800047c: ea45 4100 orr.w r1, r5, r0, lsl #16 8000480: e738 b.n 80002f4 <__udivmoddi4+0xfc> 8000482: 4631 mov r1, r6 8000484: 4630 mov r0, r6 8000486: e708 b.n 800029a <__udivmoddi4+0xa2> 8000488: 4639 mov r1, r7 800048a: e6e6 b.n 800025a <__udivmoddi4+0x62> 800048c: 4610 mov r0, r2 800048e: e6fb b.n 8000288 <__udivmoddi4+0x90> 8000490: 4548 cmp r0, r9 8000492: d2a9 bcs.n 80003e8 <__udivmoddi4+0x1f0> 8000494: ebb9 0802 subs.w r8, r9, r2 8000498: eb65 0e0c sbc.w lr, r5, ip 800049c: 3b01 subs r3, #1 800049e: e7a3 b.n 80003e8 <__udivmoddi4+0x1f0> 80004a0: 4645 mov r5, r8 80004a2: e7ea b.n 800047a <__udivmoddi4+0x282> 80004a4: 462b mov r3, r5 80004a6: e794 b.n 80003d2 <__udivmoddi4+0x1da> 80004a8: 4640 mov r0, r8 80004aa: e7d1 b.n 8000450 <__udivmoddi4+0x258> 80004ac: 46d0 mov r8, sl 80004ae: e77b b.n 80003a8 <__udivmoddi4+0x1b0> 80004b0: 3d02 subs r5, #2 80004b2: 4462 add r2, ip 80004b4: e732 b.n 800031c <__udivmoddi4+0x124> 80004b6: 4608 mov r0, r1 80004b8: e70a b.n 80002d0 <__udivmoddi4+0xd8> 80004ba: 4464 add r4, ip 80004bc: 3802 subs r0, #2 80004be: e742 b.n 8000346 <__udivmoddi4+0x14e> 080004c0 <__aeabi_idiv0>: 80004c0: 4770 bx lr 80004c2: bf00 nop 080004c4 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80004c4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 80004c8: b08b sub sp, #44 ; 0x2c GPIO_InitTypeDef GPIO_InitStruct = {0}; 80004ca: 2400 movs r4, #0 80004cc: 9405 str r4, [sp, #20] 80004ce: 9406 str r4, [sp, #24] 80004d0: 9407 str r4, [sp, #28] 80004d2: 9408 str r4, [sp, #32] 80004d4: 9409 str r4, [sp, #36] ; 0x24 /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 80004d6: 9401 str r4, [sp, #4] 80004d8: 4b2b ldr r3, [pc, #172] ; (8000588 ) 80004da: 6b1a ldr r2, [r3, #48] ; 0x30 80004dc: f042 0280 orr.w r2, r2, #128 ; 0x80 80004e0: 631a str r2, [r3, #48] ; 0x30 80004e2: 6b1a ldr r2, [r3, #48] ; 0x30 80004e4: f002 0280 and.w r2, r2, #128 ; 0x80 80004e8: 9201 str r2, [sp, #4] 80004ea: 9a01 ldr r2, [sp, #4] __HAL_RCC_GPIOC_CLK_ENABLE(); 80004ec: 9402 str r4, [sp, #8] 80004ee: 6b1a ldr r2, [r3, #48] ; 0x30 80004f0: f042 0204 orr.w r2, r2, #4 80004f4: 631a str r2, [r3, #48] ; 0x30 80004f6: 6b1a ldr r2, [r3, #48] ; 0x30 80004f8: f002 0204 and.w r2, r2, #4 80004fc: 9202 str r2, [sp, #8] 80004fe: 9a02 ldr r2, [sp, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000500: 9403 str r4, [sp, #12] 8000502: 6b1a ldr r2, [r3, #48] ; 0x30 8000504: f042 0201 orr.w r2, r2, #1 8000508: 631a str r2, [r3, #48] ; 0x30 800050a: 6b1a ldr r2, [r3, #48] ; 0x30 800050c: f002 0201 and.w r2, r2, #1 8000510: 9203 str r2, [sp, #12] 8000512: 9a03 ldr r2, [sp, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000514: 9404 str r4, [sp, #16] 8000516: 6b1a ldr r2, [r3, #48] ; 0x30 8000518: f042 0210 orr.w r2, r2, #16 800051c: 631a str r2, [r3, #48] ; 0x30 800051e: 6b1b ldr r3, [r3, #48] ; 0x30 8000520: f003 0310 and.w r3, r3, #16 8000524: 9304 str r3, [sp, #16] 8000526: 9b04 ldr r3, [sp, #16] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1, GPIO_PIN_RESET); 8000528: f8df 9064 ldr.w r9, [pc, #100] ; 8000590 800052c: 4622 mov r2, r4 800052e: 2102 movs r1, #2 8000530: 4648 mov r0, r9 8000532: f000 fee1 bl 80012f8 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1|GPIO_PIN_3, GPIO_PIN_RESET); 8000536: 4d15 ldr r5, [pc, #84] ; (800058c ) 8000538: 4622 mov r2, r4 800053a: 210a movs r1, #10 800053c: 4628 mov r0, r5 800053e: f000 fedb bl 80012f8 /*Configure GPIO pin : PC1 */ GPIO_InitStruct.Pin = GPIO_PIN_1; 8000542: f04f 0802 mov.w r8, #2 8000546: f8cd 8014 str.w r8, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800054a: 2601 movs r6, #1 800054c: 9606 str r6, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800054e: 9407 str r4, [sp, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000550: 2703 movs r7, #3 8000552: 9708 str r7, [sp, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000554: a905 add r1, sp, #20 8000556: 4648 mov r0, r9 8000558: f000 fd32 bl 8000fc0 /*Configure GPIO pin : PA1 */ GPIO_InitStruct.Pin = GPIO_PIN_1; 800055c: f8cd 8014 str.w r8, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000560: 9606 str r6, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000562: 9407 str r4, [sp, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000564: 9408 str r4, [sp, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000566: a905 add r1, sp, #20 8000568: 4628 mov r0, r5 800056a: f000 fd29 bl 8000fc0 /*Configure GPIO pin : PA3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; 800056e: 2308 movs r3, #8 8000570: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000572: 9606 str r6, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000574: 9407 str r4, [sp, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000576: 9708 str r7, [sp, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000578: a905 add r1, sp, #20 800057a: 4628 mov r0, r5 800057c: f000 fd20 bl 8000fc0 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000580: b00b add sp, #44 ; 0x2c 8000582: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8000586: bf00 nop 8000588: 40023800 .word 0x40023800 800058c: 40020000 .word 0x40020000 8000590: 40020800 .word 0x40020800 08000594 : \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000594: b672 cpsid i void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000596: e7fe b.n 8000596 08000598 : { 8000598: b500 push {lr} 800059a: b08f sub sp, #60 ; 0x3c TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800059c: 2300 movs r3, #0 800059e: 930a str r3, [sp, #40] ; 0x28 80005a0: 930b str r3, [sp, #44] ; 0x2c 80005a2: 930c str r3, [sp, #48] ; 0x30 80005a4: 930d str r3, [sp, #52] ; 0x34 TIM_MasterConfigTypeDef sMasterConfig = {0}; 80005a6: 9308 str r3, [sp, #32] 80005a8: 9309 str r3, [sp, #36] ; 0x24 TIM_OC_InitTypeDef sConfigOC = {0}; 80005aa: 9301 str r3, [sp, #4] 80005ac: 9302 str r3, [sp, #8] 80005ae: 9303 str r3, [sp, #12] 80005b0: 9304 str r3, [sp, #16] 80005b2: 9305 str r3, [sp, #20] 80005b4: 9306 str r3, [sp, #24] 80005b6: 9307 str r3, [sp, #28] htim2.Instance = TIM2; 80005b8: 481f ldr r0, [pc, #124] ; (8000638 ) 80005ba: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 80005be: 6002 str r2, [r0, #0] htim2.Init.Prescaler = 0; 80005c0: 6043 str r3, [r0, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80005c2: 6083 str r3, [r0, #8] htim2.Init.Period = 65535; 80005c4: f64f 72ff movw r2, #65535 ; 0xffff 80005c8: 60c2 str r2, [r0, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80005ca: 6103 str r3, [r0, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80005cc: 6183 str r3, [r0, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 80005ce: f001 faeb bl 8001ba8 80005d2: bb30 cbnz r0, 8000622 sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80005d4: f44f 5380 mov.w r3, #4096 ; 0x1000 80005d8: 930a str r3, [sp, #40] ; 0x28 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 80005da: a90a add r1, sp, #40 ; 0x28 80005dc: 4816 ldr r0, [pc, #88] ; (8000638 ) 80005de: f001 ffb3 bl 8002548 80005e2: bb00 cbnz r0, 8000626 if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 80005e4: 4814 ldr r0, [pc, #80] ; (8000638 ) 80005e6: f001 fbf8 bl 8001dda 80005ea: b9f0 cbnz r0, 800062a sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80005ec: 2300 movs r3, #0 80005ee: 9308 str r3, [sp, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80005f0: 9309 str r3, [sp, #36] ; 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 80005f2: a908 add r1, sp, #32 80005f4: 4810 ldr r0, [pc, #64] ; (8000638 ) 80005f6: f002 fbb1 bl 8002d5c 80005fa: b9c0 cbnz r0, 800062e sConfigOC.OCMode = TIM_OCMODE_PWM1; 80005fc: 2360 movs r3, #96 ; 0x60 80005fe: 9301 str r3, [sp, #4] sConfigOC.Pulse = 10000; 8000600: f242 7310 movw r3, #10000 ; 0x2710 8000604: 9302 str r3, [sp, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8000606: 2200 movs r2, #0 8000608: 9203 str r2, [sp, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800060a: 9205 str r2, [sp, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800060c: a901 add r1, sp, #4 800060e: 480a ldr r0, [pc, #40] ; (8000638 ) 8000610: f001 fed8 bl 80023c4 8000614: b968 cbnz r0, 8000632 HAL_TIM_MspPostInit(&htim2); 8000616: 4808 ldr r0, [pc, #32] ; (8000638 ) 8000618: f000 fa3e bl 8000a98 } 800061c: b00f add sp, #60 ; 0x3c 800061e: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 8000622: f7ff ffb7 bl 8000594 Error_Handler(); 8000626: f7ff ffb5 bl 8000594 Error_Handler(); 800062a: f7ff ffb3 bl 8000594 Error_Handler(); 800062e: f7ff ffb1 bl 8000594 Error_Handler(); 8000632: f7ff ffaf bl 8000594 8000636: bf00 nop 8000638: 20000074 .word 0x20000074 0800063c : { 800063c: b510 push {r4, lr} 800063e: b096 sub sp, #88 ; 0x58 TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8000640: 2400 movs r4, #0 8000642: 9412 str r4, [sp, #72] ; 0x48 8000644: 9413 str r4, [sp, #76] ; 0x4c 8000646: 9414 str r4, [sp, #80] ; 0x50 8000648: 9415 str r4, [sp, #84] ; 0x54 TIM_MasterConfigTypeDef sMasterConfig = {0}; 800064a: 9410 str r4, [sp, #64] ; 0x40 800064c: 9411 str r4, [sp, #68] ; 0x44 TIM_OC_InitTypeDef sConfigOC = {0}; 800064e: 9409 str r4, [sp, #36] ; 0x24 8000650: 940a str r4, [sp, #40] ; 0x28 8000652: 940b str r4, [sp, #44] ; 0x2c 8000654: 940c str r4, [sp, #48] ; 0x30 8000656: 940d str r4, [sp, #52] ; 0x34 8000658: 940e str r4, [sp, #56] ; 0x38 800065a: 940f str r4, [sp, #60] ; 0x3c TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 800065c: 2220 movs r2, #32 800065e: 4621 mov r1, r4 8000660: a801 add r0, sp, #4 8000662: f002 fc5d bl 8002f20 htim1.Instance = TIM1; 8000666: 482a ldr r0, [pc, #168] ; (8000710 ) 8000668: 4b2a ldr r3, [pc, #168] ; (8000714 ) 800066a: 6003 str r3, [r0, #0] htim1.Init.Prescaler = 23999; 800066c: f645 53bf movw r3, #23999 ; 0x5dbf 8000670: 6043 str r3, [r0, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000672: 6084 str r4, [r0, #8] htim1.Init.Period = 999; 8000674: f240 33e7 movw r3, #999 ; 0x3e7 8000678: 60c3 str r3, [r0, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800067a: 6104 str r4, [r0, #16] htim1.Init.RepetitionCounter = 0; 800067c: 6144 str r4, [r0, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800067e: 6184 str r4, [r0, #24] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 8000680: f001 fa92 bl 8001ba8 8000684: 2800 cmp r0, #0 8000686: d136 bne.n 80006f6 sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000688: f44f 5380 mov.w r3, #4096 ; 0x1000 800068c: 9312 str r3, [sp, #72] ; 0x48 if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 800068e: a912 add r1, sp, #72 ; 0x48 8000690: 481f ldr r0, [pc, #124] ; (8000710 ) 8000692: f001 ff59 bl 8002548 8000696: 2800 cmp r0, #0 8000698: d12f bne.n 80006fa if (HAL_TIM_OC_Init(&htim1) != HAL_OK) 800069a: 481d ldr r0, [pc, #116] ; (8000710 ) 800069c: f001 fb44 bl 8001d28 80006a0: 2800 cmp r0, #0 80006a2: d12c bne.n 80006fe sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80006a4: 2300 movs r3, #0 80006a6: 9310 str r3, [sp, #64] ; 0x40 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80006a8: 9311 str r3, [sp, #68] ; 0x44 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 80006aa: a910 add r1, sp, #64 ; 0x40 80006ac: 4818 ldr r0, [pc, #96] ; (8000710 ) 80006ae: f002 fb55 bl 8002d5c 80006b2: bb30 cbnz r0, 8000702 sConfigOC.OCMode = TIM_OCMODE_TIMING; 80006b4: 2200 movs r2, #0 80006b6: 9209 str r2, [sp, #36] ; 0x24 sConfigOC.Pulse = 0; 80006b8: 920a str r2, [sp, #40] ; 0x28 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80006ba: 920b str r2, [sp, #44] ; 0x2c sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 80006bc: 920c str r2, [sp, #48] ; 0x30 sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80006be: 920d str r2, [sp, #52] ; 0x34 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 80006c0: 920e str r2, [sp, #56] ; 0x38 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 80006c2: 920f str r2, [sp, #60] ; 0x3c if (HAL_TIM_OC_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80006c4: a909 add r1, sp, #36 ; 0x24 80006c6: 4812 ldr r0, [pc, #72] ; (8000710 ) 80006c8: f001 fe20 bl 800230c 80006cc: b9d8 cbnz r0, 8000706 sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 80006ce: 2300 movs r3, #0 80006d0: 9301 str r3, [sp, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 80006d2: 9302 str r3, [sp, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 80006d4: 9303 str r3, [sp, #12] sBreakDeadTimeConfig.DeadTime = 0; 80006d6: 9304 str r3, [sp, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 80006d8: 9305 str r3, [sp, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 80006da: f44f 5200 mov.w r2, #8192 ; 0x2000 80006de: 9206 str r2, [sp, #24] sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 80006e0: 9308 str r3, [sp, #32] if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 80006e2: a901 add r1, sp, #4 80006e4: 480a ldr r0, [pc, #40] ; (8000710 ) 80006e6: f002 fbb5 bl 8002e54 80006ea: b970 cbnz r0, 800070a HAL_TIM_MspPostInit(&htim1); 80006ec: 4808 ldr r0, [pc, #32] ; (8000710 ) 80006ee: f000 f9d3 bl 8000a98 } 80006f2: b016 add sp, #88 ; 0x58 80006f4: bd10 pop {r4, pc} Error_Handler(); 80006f6: f7ff ff4d bl 8000594 Error_Handler(); 80006fa: f7ff ff4b bl 8000594 Error_Handler(); 80006fe: f7ff ff49 bl 8000594 Error_Handler(); 8000702: f7ff ff47 bl 8000594 Error_Handler(); 8000706: f7ff ff45 bl 8000594 Error_Handler(); 800070a: f7ff ff43 bl 8000594 800070e: bf00 nop 8000710: 2000002c .word 0x2000002c 8000714: 40010000 .word 0x40010000 08000718 : { 8000718: b500 push {lr} 800071a: b095 sub sp, #84 ; 0x54 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800071c: 2230 movs r2, #48 ; 0x30 800071e: 2100 movs r1, #0 8000720: a808 add r0, sp, #32 8000722: f002 fbfd bl 8002f20 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000726: 2300 movs r3, #0 8000728: 9303 str r3, [sp, #12] 800072a: 9304 str r3, [sp, #16] 800072c: 9305 str r3, [sp, #20] 800072e: 9306 str r3, [sp, #24] 8000730: 9307 str r3, [sp, #28] __HAL_RCC_PWR_CLK_ENABLE(); 8000732: 9301 str r3, [sp, #4] 8000734: 4a18 ldr r2, [pc, #96] ; (8000798 ) 8000736: 6c11 ldr r1, [r2, #64] ; 0x40 8000738: f041 5180 orr.w r1, r1, #268435456 ; 0x10000000 800073c: 6411 str r1, [r2, #64] ; 0x40 800073e: 6c12 ldr r2, [r2, #64] ; 0x40 8000740: f002 5280 and.w r2, r2, #268435456 ; 0x10000000 8000744: 9201 str r2, [sp, #4] 8000746: 9a01 ldr r2, [sp, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8000748: 9302 str r3, [sp, #8] 800074a: 4a14 ldr r2, [pc, #80] ; (800079c ) 800074c: 6811 ldr r1, [r2, #0] 800074e: f441 4180 orr.w r1, r1, #16384 ; 0x4000 8000752: 6011 str r1, [r2, #0] 8000754: 6812 ldr r2, [r2, #0] 8000756: f402 4280 and.w r2, r2, #16384 ; 0x4000 800075a: 9202 str r2, [sp, #8] 800075c: 9a02 ldr r2, [sp, #8] RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 800075e: 2201 movs r2, #1 8000760: 9208 str r2, [sp, #32] RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; 8000762: f44f 22a0 mov.w r2, #327680 ; 0x50000 8000766: 9209 str r2, [sp, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8000768: 930e str r3, [sp, #56] ; 0x38 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800076a: a808 add r0, sp, #32 800076c: f000 fdf8 bl 8001360 8000770: b970 cbnz r0, 8000790 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000772: 230f movs r3, #15 8000774: 9303 str r3, [sp, #12] RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; 8000776: 2301 movs r3, #1 8000778: 9304 str r3, [sp, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800077a: 2100 movs r1, #0 800077c: 9105 str r1, [sp, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 800077e: 9106 str r1, [sp, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000780: 9107 str r1, [sp, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8000782: a803 add r0, sp, #12 8000784: f001 f864 bl 8001850 8000788: b920 cbnz r0, 8000794 } 800078a: b015 add sp, #84 ; 0x54 800078c: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 8000790: f7ff ff00 bl 8000594 Error_Handler(); 8000794: f7ff fefe bl 8000594 8000798: 40023800 .word 0x40023800 800079c: 40007000 .word 0x40007000 080007a0
: { 80007a0: b538 push {r3, r4, r5, lr} HAL_Init(); 80007a2: f000 fa89 bl 8000cb8 SystemClock_Config(); 80007a6: f7ff ffb7 bl 8000718 MX_GPIO_Init(); 80007aa: f7ff fe8b bl 80004c4 MX_TIM2_Init(); 80007ae: f7ff fef3 bl 8000598 MX_TIM1_Init(); 80007b2: f7ff ff43 bl 800063c modes[0].time_mode = 2; // время работы в данном режиме, секунды (задается) 80007b6: 4b43 ldr r3, [pc, #268] ; (80008c4 ) 80007b8: 2102 movs r1, #2 80007ba: 7019 strb r1, [r3, #0] modes[0].pwm_value = 35000; // скважность для данного режими (задается) 80007bc: f648 02b8 movw r2, #35000 ; 0x88b8 80007c0: 805a strh r2, [r3, #2] modes[0].f = 40; // частота импульсной последовательности, Гц (задается) 80007c2: 2228 movs r2, #40 ; 0x28 80007c4: 711a strb r2, [r3, #4] modes[1].time_mode = 5; 80007c6: 2205 movs r2, #5 80007c8: 729a strb r2, [r3, #10] modes[1].pwm_value = 20000; 80007ca: f644 6220 movw r2, #20000 ; 0x4e20 80007ce: 819a strh r2, [r3, #12] modes[1].f = 20; 80007d0: 2214 movs r2, #20 80007d2: 739a strb r2, [r3, #14] HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1, GPIO_PIN_RESET); 80007d4: 2200 movs r2, #0 80007d6: 483c ldr r0, [pc, #240] ; (80008c8 ) 80007d8: f000 fd8e bl 80012f8 for (int i = 0; i < CHANNELS; i++) { 80007dc: 2000 movs r0, #0 80007de: e012 b.n 8000806 int F_tmp = F_CPU / modes[i].coef; 80007e0: eb00 0280 add.w r2, r0, r0, lsl #2 80007e4: 0051 lsls r1, r2, #1 80007e6: 4a37 ldr r2, [pc, #220] ; (80008c4 ) 80007e8: 440a add r2, r1 80007ea: 7954 ldrb r4, [r2, #5] 80007ec: 4937 ldr r1, [pc, #220] ; (80008cc ) 80007ee: fb91 f1f4 sdiv r1, r1, r4 modes[i].freq_pwm_new = (F_tmp * T) / 1000; 80007f2: fb01 f303 mul.w r3, r1, r3 80007f6: 4936 ldr r1, [pc, #216] ; (80008d0 ) 80007f8: fb81 4103 smull r4, r1, r1, r3 80007fc: 17db asrs r3, r3, #31 80007fe: ebc3 13a1 rsb r3, r3, r1, asr #6 8000802: 80d3 strh r3, [r2, #6] for (int i = 0; i < CHANNELS; i++) { 8000804: 3001 adds r0, #1 8000806: 2801 cmp r0, #1 8000808: dc2b bgt.n 8000862 uint8_t T = 1000 / modes[i].f; // период следования импульсов 800080a: eb00 0380 add.w r3, r0, r0, lsl #2 800080e: 005a lsls r2, r3, #1 8000810: 4b2c ldr r3, [pc, #176] ; (80008c4 ) 8000812: 4413 add r3, r2 8000814: 791a ldrb r2, [r3, #4] 8000816: f44f 737a mov.w r3, #1000 ; 0x3e8 800081a: fb93 f3f2 sdiv r3, r3, r2 uint32_t freq_T_check = (F_CPU * T) / 1000; 800081e: b2db uxtb r3, r3 8000820: f645 52c0 movw r2, #24000 ; 0x5dc0 8000824: fb03 f202 mul.w r2, r3, r2 if (freq_T_check >= MAX_PWM_FREQ) { 8000828: f64f 71fe movw r1, #65534 ; 0xfffe 800082c: 428a cmp r2, r1 800082e: d9e9 bls.n 8000804 modes[i].coef = freq_T_check / MAX_PWM_FREQ; // предделитель 8000830: 4928 ldr r1, [pc, #160] ; (80008d4 ) 8000832: fba1 4102 umull r4, r1, r1, r2 8000836: ea4f 3cd1 mov.w ip, r1, lsr #15 800083a: 4661 mov r1, ip 800083c: eb00 0e80 add.w lr, r0, r0, lsl #2 8000840: ea4f 044e mov.w r4, lr, lsl #1 8000844: 4d1f ldr r5, [pc, #124] ; (80008c4 ) 8000846: eb05 0e04 add.w lr, r5, r4 800084a: f88e c005 strb.w ip, [lr, #5] if (freq_T_check % MAX_PWM_FREQ != 0) { 800084e: ebcc 4c0c rsb ip, ip, ip, lsl #16 8000852: 4562 cmp r2, ip 8000854: d0c4 beq.n 80007e0 modes[i].coef++; 8000856: 240a movs r4, #10 8000858: fb04 5200 mla r2, r4, r0, r5 800085c: 3101 adds r1, #1 800085e: 7151 strb r1, [r2, #5] 8000860: e7be b.n 80007e0 modes[0].pwm_value_res = (modes[0].pwm_value * modes[0].freq_pwm_new) / MAX_PWM_FREQ; // пересчет скважности для 1 канала 8000862: 4a18 ldr r2, [pc, #96] ; (80008c4 ) 8000864: 8853 ldrh r3, [r2, #2] 8000866: 88d1 ldrh r1, [r2, #6] 8000868: fb01 f303 mul.w r3, r1, r3 800086c: 4919 ldr r1, [pc, #100] ; (80008d4 ) 800086e: fb81 4003 smull r4, r0, r1, r3 8000872: 4418 add r0, r3 8000874: 17db asrs r3, r3, #31 8000876: ebc3 33e0 rsb r3, r3, r0, asr #15 800087a: 8113 strh r3, [r2, #8] modes[1].pwm_value_res = (modes[1].pwm_value * modes[1].freq_pwm_new) / MAX_PWM_FREQ; // пересчет скважности для 2 канала 800087c: 8993 ldrh r3, [r2, #12] 800087e: 8a10 ldrh r0, [r2, #16] 8000880: fb00 f303 mul.w r3, r0, r3 8000884: fb81 0103 smull r0, r1, r1, r3 8000888: 4419 add r1, r3 800088a: 17db asrs r3, r3, #31 800088c: ebc3 33e1 rsb r3, r3, r1, asr #15 8000890: 8253 strh r3, [r2, #18] HAL_TIM_Base_Start_IT(&htim1); 8000892: 4811 ldr r0, [pc, #68] ; (80008d8 ) 8000894: f001 f9d8 bl 8001c48 8000898: e005 b.n 80008a6 if (channel == 1 && settings_set == 0) { 800089a: 4a10 ldr r2, [pc, #64] ; (80008dc ) 800089c: 6812 ldr r2, [r2, #0] 800089e: b932 cbnz r2, 80008ae settings_set = 1; // канал 1 настроен 80008a0: 4b0e ldr r3, [pc, #56] ; (80008dc ) 80008a2: 2201 movs r2, #1 80008a4: 601a str r2, [r3, #0] if (channel == 1 && settings_set == 0) { 80008a6: 4b0e ldr r3, [pc, #56] ; (80008e0 ) 80008a8: 681b ldr r3, [r3, #0] 80008aa: 2b01 cmp r3, #1 80008ac: d0f5 beq.n 800089a else if (channel == 2 && settings_set == 0) { 80008ae: 2b02 cmp r3, #2 80008b0: d1f9 bne.n 80008a6 80008b2: 4b0a ldr r3, [pc, #40] ; (80008dc ) 80008b4: 681b ldr r3, [r3, #0] 80008b6: 2b00 cmp r3, #0 80008b8: d1f5 bne.n 80008a6 settings_set = 1; // канал 2 настроен 80008ba: 4b08 ldr r3, [pc, #32] ; (80008dc ) 80008bc: 2201 movs r2, #1 80008be: 601a str r2, [r3, #0] 80008c0: e7f1 b.n 80008a6 80008c2: bf00 nop 80008c4: 200000bc .word 0x200000bc 80008c8: 40020800 .word 0x40020800 80008cc: 016e3600 .word 0x016e3600 80008d0: 10624dd3 .word 0x10624dd3 80008d4: 80008001 .word 0x80008001 80008d8: 2000002c .word 0x2000002c 80008dc: 200000d0 .word 0x200000d0 80008e0: 20000000 .word 0x20000000 080008e4 : void PWM_Init(uint8_t prescaler, uint16_t period, uint16_t pwm_value) { 80008e4: b570 push {r4, r5, r6, lr} 80008e6: b08e sub sp, #56 ; 0x38 80008e8: 4604 mov r4, r0 80008ea: 4616 mov r6, r2 TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80008ec: 2300 movs r3, #0 80008ee: 930a str r3, [sp, #40] ; 0x28 80008f0: 930b str r3, [sp, #44] ; 0x2c 80008f2: 930c str r3, [sp, #48] ; 0x30 80008f4: 930d str r3, [sp, #52] ; 0x34 TIM_MasterConfigTypeDef sMasterConfig = {0}; 80008f6: 9308 str r3, [sp, #32] 80008f8: 9309 str r3, [sp, #36] ; 0x24 TIM_OC_InitTypeDef sConfigOC = {0}; 80008fa: 9301 str r3, [sp, #4] 80008fc: 9302 str r3, [sp, #8] 80008fe: 9303 str r3, [sp, #12] 8000900: 9304 str r3, [sp, #16] 8000902: 9305 str r3, [sp, #20] 8000904: 9306 str r3, [sp, #24] 8000906: 9307 str r3, [sp, #28] htim2.Instance = TIM2; 8000908: 481f ldr r0, [pc, #124] ; (8000988 ) 800090a: f04f 4580 mov.w r5, #1073741824 ; 0x40000000 800090e: 6005 str r5, [r0, #0] htim2.Init.Prescaler = prescaler; 8000910: 6044 str r4, [r0, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8000912: 6083 str r3, [r0, #8] htim2.Init.Period = period; 8000914: 60c1 str r1, [r0, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000916: 6103 str r3, [r0, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000918: 6183 str r3, [r0, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 800091a: f001 f945 bl 8001ba8 800091e: bb40 cbnz r0, 8000972 sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000920: f44f 5380 mov.w r3, #4096 ; 0x1000 8000924: 930a str r3, [sp, #40] ; 0x28 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 8000926: a90a add r1, sp, #40 ; 0x28 8000928: 4817 ldr r0, [pc, #92] ; (8000988 ) 800092a: f001 fe0d bl 8002548 800092e: bb10 cbnz r0, 8000976 if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 8000930: 4815 ldr r0, [pc, #84] ; (8000988 ) 8000932: f001 fa52 bl 8001dda 8000936: bb00 cbnz r0, 800097a sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000938: 2300 movs r3, #0 800093a: 9308 str r3, [sp, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800093c: 9309 str r3, [sp, #36] ; 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 800093e: a908 add r1, sp, #32 8000940: 4811 ldr r0, [pc, #68] ; (8000988 ) 8000942: f002 fa0b bl 8002d5c 8000946: b9d0 cbnz r0, 800097e sConfigOC.OCMode = TIM_OCMODE_PWM1; 8000948: 2360 movs r3, #96 ; 0x60 800094a: 9301 str r3, [sp, #4] sConfigOC.Pulse = pwm_value; 800094c: 9602 str r6, [sp, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800094e: 2200 movs r2, #0 8000950: 9203 str r2, [sp, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8000952: 9205 str r2, [sp, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8000954: a901 add r1, sp, #4 8000956: 480c ldr r0, [pc, #48] ; (8000988 ) 8000958: f001 fd34 bl 80023c4 800095c: b988 cbnz r0, 8000982 HAL_TIM_MspPostInit(&htim2); 800095e: 4c0a ldr r4, [pc, #40] ; (8000988 ) 8000960: 4620 mov r0, r4 8000962: f000 f899 bl 8000a98 HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); 8000966: 2100 movs r1, #0 8000968: 4620 mov r0, r4 800096a: f001 fa8f bl 8001e8c } 800096e: b00e add sp, #56 ; 0x38 8000970: bd70 pop {r4, r5, r6, pc} Error_Handler(); 8000972: f7ff fe0f bl 8000594 Error_Handler(); 8000976: f7ff fe0d bl 8000594 Error_Handler(); 800097a: f7ff fe0b bl 8000594 Error_Handler(); 800097e: f7ff fe09 bl 8000594 Error_Handler(); 8000982: f7ff fe07 bl 8000594 8000986: bf00 nop 8000988: 20000074 .word 0x20000074 0800098c : void Channel_Swap(Mode *mode_ptr, int channel_new, int *channel_var, int settings_flag, int *settings_var) { 800098c: b5f8 push {r3, r4, r5, r6, r7, lr} 800098e: 4604 mov r4, r0 8000990: 460f mov r7, r1 8000992: 4616 mov r6, r2 8000994: 461d mov r5, r3 PWM_Init(mode_ptr->coef-1, mode_ptr->freq_pwm_new-1, mode_ptr->pwm_value_res); 8000996: 7940 ldrb r0, [r0, #5] 8000998: 88e1 ldrh r1, [r4, #6] 800099a: 3901 subs r1, #1 800099c: 3801 subs r0, #1 800099e: 8922 ldrh r2, [r4, #8] 80009a0: b289 uxth r1, r1 80009a2: b2c0 uxtb r0, r0 80009a4: f7ff ff9e bl 80008e4 __HAL_TIM_SET_AUTORELOAD(&htim1, (mode_ptr->time_mode * F_CPU_TIM1 - 1)); 80009a8: 7820 ldrb r0, [r4, #0] 80009aa: f44f 717a mov.w r1, #1000 ; 0x3e8 80009ae: fb01 f000 mul.w r0, r1, r0 80009b2: 4b06 ldr r3, [pc, #24] ; (80009cc ) 80009b4: 681a ldr r2, [r3, #0] 80009b6: 3801 subs r0, #1 80009b8: 62d0 str r0, [r2, #44] ; 0x2c 80009ba: 7820 ldrb r0, [r4, #0] 80009bc: fb01 f000 mul.w r0, r1, r0 80009c0: 3801 subs r0, #1 80009c2: 60d8 str r0, [r3, #12] *channel_var = channel_new; 80009c4: 6037 str r7, [r6, #0] *settings_var = settings_flag; 80009c6: 9b06 ldr r3, [sp, #24] 80009c8: 601d str r5, [r3, #0] } 80009ca: bdf8 pop {r3, r4, r5, r6, r7, pc} 80009cc: 2000002c .word 0x2000002c 080009d0 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80009d0: b480 push {r7} 80009d2: b083 sub sp, #12 80009d4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80009d6: 2300 movs r3, #0 80009d8: 607b str r3, [r7, #4] 80009da: 4b10 ldr r3, [pc, #64] ; (8000a1c ) 80009dc: 6c5b ldr r3, [r3, #68] ; 0x44 80009de: 4a0f ldr r2, [pc, #60] ; (8000a1c ) 80009e0: f443 4380 orr.w r3, r3, #16384 ; 0x4000 80009e4: 6453 str r3, [r2, #68] ; 0x44 80009e6: 4b0d ldr r3, [pc, #52] ; (8000a1c ) 80009e8: 6c5b ldr r3, [r3, #68] ; 0x44 80009ea: f403 4380 and.w r3, r3, #16384 ; 0x4000 80009ee: 607b str r3, [r7, #4] 80009f0: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 80009f2: 2300 movs r3, #0 80009f4: 603b str r3, [r7, #0] 80009f6: 4b09 ldr r3, [pc, #36] ; (8000a1c ) 80009f8: 6c1b ldr r3, [r3, #64] ; 0x40 80009fa: 4a08 ldr r2, [pc, #32] ; (8000a1c ) 80009fc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000a00: 6413 str r3, [r2, #64] ; 0x40 8000a02: 4b06 ldr r3, [pc, #24] ; (8000a1c ) 8000a04: 6c1b ldr r3, [r3, #64] ; 0x40 8000a06: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000a0a: 603b str r3, [r7, #0] 8000a0c: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000a0e: bf00 nop 8000a10: 370c adds r7, #12 8000a12: 46bd mov sp, r7 8000a14: f85d 7b04 ldr.w r7, [sp], #4 8000a18: 4770 bx lr 8000a1a: bf00 nop 8000a1c: 40023800 .word 0x40023800 08000a20 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8000a20: b580 push {r7, lr} 8000a22: b084 sub sp, #16 8000a24: af00 add r7, sp, #0 8000a26: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM1) 8000a28: 687b ldr r3, [r7, #4] 8000a2a: 681b ldr r3, [r3, #0] 8000a2c: 4a18 ldr r2, [pc, #96] ; (8000a90 ) 8000a2e: 4293 cmp r3, r2 8000a30: d116 bne.n 8000a60 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 8000a32: 2300 movs r3, #0 8000a34: 60fb str r3, [r7, #12] 8000a36: 4b17 ldr r3, [pc, #92] ; (8000a94 ) 8000a38: 6c5b ldr r3, [r3, #68] ; 0x44 8000a3a: 4a16 ldr r2, [pc, #88] ; (8000a94 ) 8000a3c: f043 0301 orr.w r3, r3, #1 8000a40: 6453 str r3, [r2, #68] ; 0x44 8000a42: 4b14 ldr r3, [pc, #80] ; (8000a94 ) 8000a44: 6c5b ldr r3, [r3, #68] ; 0x44 8000a46: f003 0301 and.w r3, r3, #1 8000a4a: 60fb str r3, [r7, #12] 8000a4c: 68fb ldr r3, [r7, #12] /* TIM1 interrupt Init */ HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 0, 0); 8000a4e: 2200 movs r2, #0 8000a50: 2100 movs r1, #0 8000a52: 2019 movs r0, #25 8000a54: f000 fa7d bl 8000f52 HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); 8000a58: 2019 movs r0, #25 8000a5a: f000 fa96 bl 8000f8a /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 8000a5e: e012 b.n 8000a86 else if(htim_base->Instance==TIM2) 8000a60: 687b ldr r3, [r7, #4] 8000a62: 681b ldr r3, [r3, #0] 8000a64: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8000a68: d10d bne.n 8000a86 __HAL_RCC_TIM2_CLK_ENABLE(); 8000a6a: 2300 movs r3, #0 8000a6c: 60bb str r3, [r7, #8] 8000a6e: 4b09 ldr r3, [pc, #36] ; (8000a94 ) 8000a70: 6c1b ldr r3, [r3, #64] ; 0x40 8000a72: 4a08 ldr r2, [pc, #32] ; (8000a94 ) 8000a74: f043 0301 orr.w r3, r3, #1 8000a78: 6413 str r3, [r2, #64] ; 0x40 8000a7a: 4b06 ldr r3, [pc, #24] ; (8000a94 ) 8000a7c: 6c1b ldr r3, [r3, #64] ; 0x40 8000a7e: f003 0301 and.w r3, r3, #1 8000a82: 60bb str r3, [r7, #8] 8000a84: 68bb ldr r3, [r7, #8] } 8000a86: bf00 nop 8000a88: 3710 adds r7, #16 8000a8a: 46bd mov sp, r7 8000a8c: bd80 pop {r7, pc} 8000a8e: bf00 nop 8000a90: 40010000 .word 0x40010000 8000a94: 40023800 .word 0x40023800 08000a98 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 8000a98: b580 push {r7, lr} 8000a9a: b08a sub sp, #40 ; 0x28 8000a9c: af00 add r7, sp, #0 8000a9e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000aa0: f107 0314 add.w r3, r7, #20 8000aa4: 2200 movs r2, #0 8000aa6: 601a str r2, [r3, #0] 8000aa8: 605a str r2, [r3, #4] 8000aaa: 609a str r2, [r3, #8] 8000aac: 60da str r2, [r3, #12] 8000aae: 611a str r2, [r3, #16] if(htim->Instance==TIM1) 8000ab0: 687b ldr r3, [r7, #4] 8000ab2: 681b ldr r3, [r3, #0] 8000ab4: 4a24 ldr r2, [pc, #144] ; (8000b48 ) 8000ab6: 4293 cmp r3, r2 8000ab8: d11f bne.n 8000afa { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOE_CLK_ENABLE(); 8000aba: 2300 movs r3, #0 8000abc: 613b str r3, [r7, #16] 8000abe: 4b23 ldr r3, [pc, #140] ; (8000b4c ) 8000ac0: 6b1b ldr r3, [r3, #48] ; 0x30 8000ac2: 4a22 ldr r2, [pc, #136] ; (8000b4c ) 8000ac4: f043 0310 orr.w r3, r3, #16 8000ac8: 6313 str r3, [r2, #48] ; 0x30 8000aca: 4b20 ldr r3, [pc, #128] ; (8000b4c ) 8000acc: 6b1b ldr r3, [r3, #48] ; 0x30 8000ace: f003 0310 and.w r3, r3, #16 8000ad2: 613b str r3, [r7, #16] 8000ad4: 693b ldr r3, [r7, #16] /**TIM1 GPIO Configuration PE9 ------> TIM1_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8000ad6: f44f 7300 mov.w r3, #512 ; 0x200 8000ada: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000adc: 2302 movs r3, #2 8000ade: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000ae0: 2300 movs r3, #0 8000ae2: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000ae4: 2300 movs r3, #0 8000ae6: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 8000ae8: 2301 movs r3, #1 8000aea: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8000aec: f107 0314 add.w r3, r7, #20 8000af0: 4619 mov r1, r3 8000af2: 4817 ldr r0, [pc, #92] ; (8000b50 ) 8000af4: f000 fa64 bl 8000fc0 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8000af8: e022 b.n 8000b40 else if(htim->Instance==TIM2) 8000afa: 687b ldr r3, [r7, #4] 8000afc: 681b ldr r3, [r3, #0] 8000afe: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8000b02: d11d bne.n 8000b40 __HAL_RCC_GPIOA_CLK_ENABLE(); 8000b04: 2300 movs r3, #0 8000b06: 60fb str r3, [r7, #12] 8000b08: 4b10 ldr r3, [pc, #64] ; (8000b4c ) 8000b0a: 6b1b ldr r3, [r3, #48] ; 0x30 8000b0c: 4a0f ldr r2, [pc, #60] ; (8000b4c ) 8000b0e: f043 0301 orr.w r3, r3, #1 8000b12: 6313 str r3, [r2, #48] ; 0x30 8000b14: 4b0d ldr r3, [pc, #52] ; (8000b4c ) 8000b16: 6b1b ldr r3, [r3, #48] ; 0x30 8000b18: f003 0301 and.w r3, r3, #1 8000b1c: 60fb str r3, [r7, #12] 8000b1e: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_0; 8000b20: 2301 movs r3, #1 8000b22: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000b24: 2302 movs r3, #2 8000b26: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 8000b28: 2302 movs r3, #2 8000b2a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000b2c: 2300 movs r3, #0 8000b2e: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8000b30: 2301 movs r3, #1 8000b32: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000b34: f107 0314 add.w r3, r7, #20 8000b38: 4619 mov r1, r3 8000b3a: 4806 ldr r0, [pc, #24] ; (8000b54 ) 8000b3c: f000 fa40 bl 8000fc0 } 8000b40: bf00 nop 8000b42: 3728 adds r7, #40 ; 0x28 8000b44: 46bd mov sp, r7 8000b46: bd80 pop {r7, pc} 8000b48: 40010000 .word 0x40010000 8000b4c: 40023800 .word 0x40023800 8000b50: 40021000 .word 0x40021000 8000b54: 40020000 .word 0x40020000 08000b58 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000b58: b480 push {r7} 8000b5a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000b5c: e7fe b.n 8000b5c 08000b5e : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000b5e: b480 push {r7} 8000b60: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000b62: e7fe b.n 8000b62 08000b64 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000b64: b480 push {r7} 8000b66: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000b68: e7fe b.n 8000b68 08000b6a : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000b6a: b480 push {r7} 8000b6c: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000b6e: e7fe b.n 8000b6e 08000b70 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000b70: b480 push {r7} 8000b72: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000b74: e7fe b.n 8000b74 08000b76 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000b76: b480 push {r7} 8000b78: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000b7a: bf00 nop 8000b7c: 46bd mov sp, r7 8000b7e: f85d 7b04 ldr.w r7, [sp], #4 8000b82: 4770 bx lr 08000b84 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000b84: b480 push {r7} 8000b86: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000b88: bf00 nop 8000b8a: 46bd mov sp, r7 8000b8c: f85d 7b04 ldr.w r7, [sp], #4 8000b90: 4770 bx lr 08000b92 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000b92: b480 push {r7} 8000b94: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000b96: bf00 nop 8000b98: 46bd mov sp, r7 8000b9a: f85d 7b04 ldr.w r7, [sp], #4 8000b9e: 4770 bx lr 08000ba0 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000ba0: b580 push {r7, lr} 8000ba2: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000ba4: f000 f8da bl 8000d5c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000ba8: bf00 nop 8000baa: bd80 pop {r7, pc} 08000bac : /** * @brief This function handles TIM1 update interrupt and TIM10 global interrupt. */ void TIM1_UP_TIM10_IRQHandler(void) { 8000bac: b580 push {r7, lr} 8000bae: b082 sub sp, #8 8000bb0: af02 add r7, sp, #8 /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */ HAL_TIM_PWM_Stop(&htim2, TIM_CHANNEL_1); 8000bb2: 2100 movs r1, #0 8000bb4: 481a ldr r0, [pc, #104] ; (8000c20 ) 8000bb6: f001 fa31 bl 800201c if (channel == 1) { // если сейчас канал 1 8000bba: 4b1a ldr r3, [pc, #104] ; (8000c24 ) 8000bbc: 681b ldr r3, [r3, #0] 8000bbe: 2b01 cmp r3, #1 8000bc0: d118 bne.n 8000bf4 if (tmp == 0) { // стартовая настройка 8000bc2: 4b19 ldr r3, [pc, #100] ; (8000c28 ) 8000bc4: 681b ldr r3, [r3, #0] 8000bc6: 2b00 cmp r3, #0 8000bc8: d10b bne.n 8000be2 // PWM_Init(modes[0].coef-1, modes[0].freq_pwm_new-1, modes[0].pwm_value_res); // __HAL_TIM_SET_AUTORELOAD(&htim1, (modes[0].time_mode * F_CPU_TIM1 - 1)); // channel = 1; // settings_set = 1; // нужно настроить канал Channel_Swap(&modes[0], 1, &channel, 1, &settings_set); 8000bca: 4b18 ldr r3, [pc, #96] ; (8000c2c ) 8000bcc: 9300 str r3, [sp, #0] 8000bce: 2301 movs r3, #1 8000bd0: 4a14 ldr r2, [pc, #80] ; (8000c24 ) 8000bd2: 2101 movs r1, #1 8000bd4: 4816 ldr r0, [pc, #88] ; (8000c30 ) 8000bd6: f7ff fed9 bl 800098c tmp = 1; 8000bda: 4b13 ldr r3, [pc, #76] ; (8000c28 ) 8000bdc: 2201 movs r2, #1 8000bde: 601a str r2, [r3, #0] 8000be0: e014 b.n 8000c0c } else { // PWM_Init(modes[1].coef-1, modes[1].freq_pwm_new-1, modes[1].pwm_value_res); // __HAL_TIM_SET_AUTORELOAD(&htim1, (modes[1].time_mode * F_CPU_TIM1 - 1)); // channel = 2; // settings_set = 0; // нужно настроить канал Channel_Swap(&modes[1], 2, &channel, 0, &settings_set); 8000be2: 4b12 ldr r3, [pc, #72] ; (8000c2c ) 8000be4: 9300 str r3, [sp, #0] 8000be6: 2300 movs r3, #0 8000be8: 4a0e ldr r2, [pc, #56] ; (8000c24 ) 8000bea: 2102 movs r1, #2 8000bec: 4811 ldr r0, [pc, #68] ; (8000c34 ) 8000bee: f7ff fecd bl 800098c 8000bf2: e00b b.n 8000c0c } } else if (channel == 2) { // если сейчас канал 2 8000bf4: 4b0b ldr r3, [pc, #44] ; (8000c24 ) 8000bf6: 681b ldr r3, [r3, #0] 8000bf8: 2b02 cmp r3, #2 8000bfa: d107 bne.n 8000c0c // PWM_Init(modes[0].coef-1, modes[0].freq_pwm_new-1, modes[0].pwm_value_res); // __HAL_TIM_SET_AUTORELOAD(&htim1, (modes[0].time_mode * F_CPU_TIM1 - 1)); // channel = 1; // settings_set = 0; // нужно настроить канал Channel_Swap(&modes[0], 1, &channel, 0, &settings_set); 8000bfc: 4b0b ldr r3, [pc, #44] ; (8000c2c ) 8000bfe: 9300 str r3, [sp, #0] 8000c00: 2300 movs r3, #0 8000c02: 4a08 ldr r2, [pc, #32] ; (8000c24 ) 8000c04: 2101 movs r1, #1 8000c06: 480a ldr r0, [pc, #40] ; (8000c30 ) 8000c08: f7ff fec0 bl 800098c } HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_1); 8000c0c: 2102 movs r1, #2 8000c0e: 480a ldr r0, [pc, #40] ; (8000c38 ) 8000c10: f000 fb8b bl 800132a /* USER CODE END TIM1_UP_TIM10_IRQn 0 */ HAL_TIM_IRQHandler(&htim1); 8000c14: 4809 ldr r0, [pc, #36] ; (8000c3c ) 8000c16: f001 fa71 bl 80020fc /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */ /* USER CODE END TIM1_UP_TIM10_IRQn 1 */ } 8000c1a: bf00 nop 8000c1c: 46bd mov sp, r7 8000c1e: bd80 pop {r7, pc} 8000c20: 20000074 .word 0x20000074 8000c24: 20000000 .word 0x20000000 8000c28: 200000d4 .word 0x200000d4 8000c2c: 200000d0 .word 0x200000d0 8000c30: 200000bc .word 0x200000bc 8000c34: 200000c6 .word 0x200000c6 8000c38: 40020800 .word 0x40020800 8000c3c: 2000002c .word 0x2000002c 08000c40 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8000c40: b480 push {r7} 8000c42: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8000c44: 4b06 ldr r3, [pc, #24] ; (8000c60 ) 8000c46: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8000c4a: 4a05 ldr r2, [pc, #20] ; (8000c60 ) 8000c4c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8000c50: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000c54: bf00 nop 8000c56: 46bd mov sp, r7 8000c58: f85d 7b04 ldr.w r7, [sp], #4 8000c5c: 4770 bx lr 8000c5e: bf00 nop 8000c60: e000ed00 .word 0xe000ed00 08000c64 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8000c64: f8df d034 ldr.w sp, [pc, #52] ; 8000c9c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000c68: 480d ldr r0, [pc, #52] ; (8000ca0 ) ldr r1, =_edata 8000c6a: 490e ldr r1, [pc, #56] ; (8000ca4 ) ldr r2, =_sidata 8000c6c: 4a0e ldr r2, [pc, #56] ; (8000ca8 ) movs r3, #0 8000c6e: 2300 movs r3, #0 b LoopCopyDataInit 8000c70: e002 b.n 8000c78 08000c72 : CopyDataInit: ldr r4, [r2, r3] 8000c72: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000c74: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000c76: 3304 adds r3, #4 08000c78 : LoopCopyDataInit: adds r4, r0, r3 8000c78: 18c4 adds r4, r0, r3 cmp r4, r1 8000c7a: 428c cmp r4, r1 bcc CopyDataInit 8000c7c: d3f9 bcc.n 8000c72 /* Zero fill the bss segment. */ ldr r2, =_sbss 8000c7e: 4a0b ldr r2, [pc, #44] ; (8000cac ) ldr r4, =_ebss 8000c80: 4c0b ldr r4, [pc, #44] ; (8000cb0 ) movs r3, #0 8000c82: 2300 movs r3, #0 b LoopFillZerobss 8000c84: e001 b.n 8000c8a 08000c86 : FillZerobss: str r3, [r2] 8000c86: 6013 str r3, [r2, #0] adds r2, r2, #4 8000c88: 3204 adds r2, #4 08000c8a : LoopFillZerobss: cmp r2, r4 8000c8a: 42a2 cmp r2, r4 bcc FillZerobss 8000c8c: d3fb bcc.n 8000c86 /* Call the clock system initialization function.*/ bl SystemInit 8000c8e: f7ff ffd7 bl 8000c40 /* Call static constructors */ bl __libc_init_array 8000c92: f002 f94d bl 8002f30 <__libc_init_array> /* Call the application's entry point.*/ bl main 8000c96: f7ff fd83 bl 80007a0
bx lr 8000c9a: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8000c9c: 20020000 .word 0x20020000 ldr r0, =_sdata 8000ca0: 20000000 .word 0x20000000 ldr r1, =_edata 8000ca4: 20000010 .word 0x20000010 ldr r2, =_sidata 8000ca8: 08002fb0 .word 0x08002fb0 ldr r2, =_sbss 8000cac: 20000010 .word 0x20000010 ldr r4, =_ebss 8000cb0: 200000dc .word 0x200000dc 08000cb4 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000cb4: e7fe b.n 8000cb4 ... 08000cb8 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000cb8: b580 push {r7, lr} 8000cba: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8000cbc: 4b0e ldr r3, [pc, #56] ; (8000cf8 ) 8000cbe: 681b ldr r3, [r3, #0] 8000cc0: 4a0d ldr r2, [pc, #52] ; (8000cf8 ) 8000cc2: f443 7300 orr.w r3, r3, #512 ; 0x200 8000cc6: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 8000cc8: 4b0b ldr r3, [pc, #44] ; (8000cf8 ) 8000cca: 681b ldr r3, [r3, #0] 8000ccc: 4a0a ldr r2, [pc, #40] ; (8000cf8 ) 8000cce: f443 6380 orr.w r3, r3, #1024 ; 0x400 8000cd2: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000cd4: 4b08 ldr r3, [pc, #32] ; (8000cf8 ) 8000cd6: 681b ldr r3, [r3, #0] 8000cd8: 4a07 ldr r2, [pc, #28] ; (8000cf8 ) 8000cda: f443 7380 orr.w r3, r3, #256 ; 0x100 8000cde: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000ce0: 2003 movs r0, #3 8000ce2: f000 f92b bl 8000f3c /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000ce6: 200f movs r0, #15 8000ce8: f000 f808 bl 8000cfc /* Init the low level hardware */ HAL_MspInit(); 8000cec: f7ff fe70 bl 80009d0 /* Return function status */ return HAL_OK; 8000cf0: 2300 movs r3, #0 } 8000cf2: 4618 mov r0, r3 8000cf4: bd80 pop {r7, pc} 8000cf6: bf00 nop 8000cf8: 40023c00 .word 0x40023c00 08000cfc : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000cfc: b580 push {r7, lr} 8000cfe: b082 sub sp, #8 8000d00: af00 add r7, sp, #0 8000d02: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000d04: 4b12 ldr r3, [pc, #72] ; (8000d50 ) 8000d06: 681a ldr r2, [r3, #0] 8000d08: 4b12 ldr r3, [pc, #72] ; (8000d54 ) 8000d0a: 781b ldrb r3, [r3, #0] 8000d0c: 4619 mov r1, r3 8000d0e: f44f 737a mov.w r3, #1000 ; 0x3e8 8000d12: fbb3 f3f1 udiv r3, r3, r1 8000d16: fbb2 f3f3 udiv r3, r2, r3 8000d1a: 4618 mov r0, r3 8000d1c: f000 f943 bl 8000fa6 8000d20: 4603 mov r3, r0 8000d22: 2b00 cmp r3, #0 8000d24: d001 beq.n 8000d2a { return HAL_ERROR; 8000d26: 2301 movs r3, #1 8000d28: e00e b.n 8000d48 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000d2a: 687b ldr r3, [r7, #4] 8000d2c: 2b0f cmp r3, #15 8000d2e: d80a bhi.n 8000d46 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000d30: 2200 movs r2, #0 8000d32: 6879 ldr r1, [r7, #4] 8000d34: f04f 30ff mov.w r0, #4294967295 8000d38: f000 f90b bl 8000f52 uwTickPrio = TickPriority; 8000d3c: 4a06 ldr r2, [pc, #24] ; (8000d58 ) 8000d3e: 687b ldr r3, [r7, #4] 8000d40: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8000d42: 2300 movs r3, #0 8000d44: e000 b.n 8000d48 return HAL_ERROR; 8000d46: 2301 movs r3, #1 } 8000d48: 4618 mov r0, r3 8000d4a: 3708 adds r7, #8 8000d4c: 46bd mov sp, r7 8000d4e: bd80 pop {r7, pc} 8000d50: 20000004 .word 0x20000004 8000d54: 2000000c .word 0x2000000c 8000d58: 20000008 .word 0x20000008 08000d5c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000d5c: b480 push {r7} 8000d5e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000d60: 4b06 ldr r3, [pc, #24] ; (8000d7c ) 8000d62: 781b ldrb r3, [r3, #0] 8000d64: 461a mov r2, r3 8000d66: 4b06 ldr r3, [pc, #24] ; (8000d80 ) 8000d68: 681b ldr r3, [r3, #0] 8000d6a: 4413 add r3, r2 8000d6c: 4a04 ldr r2, [pc, #16] ; (8000d80 ) 8000d6e: 6013 str r3, [r2, #0] } 8000d70: bf00 nop 8000d72: 46bd mov sp, r7 8000d74: f85d 7b04 ldr.w r7, [sp], #4 8000d78: 4770 bx lr 8000d7a: bf00 nop 8000d7c: 2000000c .word 0x2000000c 8000d80: 200000d8 .word 0x200000d8 08000d84 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000d84: b480 push {r7} 8000d86: af00 add r7, sp, #0 return uwTick; 8000d88: 4b03 ldr r3, [pc, #12] ; (8000d98 ) 8000d8a: 681b ldr r3, [r3, #0] } 8000d8c: 4618 mov r0, r3 8000d8e: 46bd mov sp, r7 8000d90: f85d 7b04 ldr.w r7, [sp], #4 8000d94: 4770 bx lr 8000d96: bf00 nop 8000d98: 200000d8 .word 0x200000d8 08000d9c <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000d9c: b480 push {r7} 8000d9e: b085 sub sp, #20 8000da0: af00 add r7, sp, #0 8000da2: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000da4: 687b ldr r3, [r7, #4] 8000da6: f003 0307 and.w r3, r3, #7 8000daa: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000dac: 4b0c ldr r3, [pc, #48] ; (8000de0 <__NVIC_SetPriorityGrouping+0x44>) 8000dae: 68db ldr r3, [r3, #12] 8000db0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8000db2: 68ba ldr r2, [r7, #8] 8000db4: f64f 03ff movw r3, #63743 ; 0xf8ff 8000db8: 4013 ands r3, r2 8000dba: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000dbc: 68fb ldr r3, [r7, #12] 8000dbe: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000dc0: 68bb ldr r3, [r7, #8] 8000dc2: 4313 orrs r3, r2 reg_value = (reg_value | 8000dc4: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8000dc8: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000dcc: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8000dce: 4a04 ldr r2, [pc, #16] ; (8000de0 <__NVIC_SetPriorityGrouping+0x44>) 8000dd0: 68bb ldr r3, [r7, #8] 8000dd2: 60d3 str r3, [r2, #12] } 8000dd4: bf00 nop 8000dd6: 3714 adds r7, #20 8000dd8: 46bd mov sp, r7 8000dda: f85d 7b04 ldr.w r7, [sp], #4 8000dde: 4770 bx lr 8000de0: e000ed00 .word 0xe000ed00 08000de4 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000de4: b480 push {r7} 8000de6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000de8: 4b04 ldr r3, [pc, #16] ; (8000dfc <__NVIC_GetPriorityGrouping+0x18>) 8000dea: 68db ldr r3, [r3, #12] 8000dec: 0a1b lsrs r3, r3, #8 8000dee: f003 0307 and.w r3, r3, #7 } 8000df2: 4618 mov r0, r3 8000df4: 46bd mov sp, r7 8000df6: f85d 7b04 ldr.w r7, [sp], #4 8000dfa: 4770 bx lr 8000dfc: e000ed00 .word 0xe000ed00 08000e00 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8000e00: b480 push {r7} 8000e02: b083 sub sp, #12 8000e04: af00 add r7, sp, #0 8000e06: 4603 mov r3, r0 8000e08: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000e0a: f997 3007 ldrsb.w r3, [r7, #7] 8000e0e: 2b00 cmp r3, #0 8000e10: db0b blt.n 8000e2a <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8000e12: 79fb ldrb r3, [r7, #7] 8000e14: f003 021f and.w r2, r3, #31 8000e18: 4907 ldr r1, [pc, #28] ; (8000e38 <__NVIC_EnableIRQ+0x38>) 8000e1a: f997 3007 ldrsb.w r3, [r7, #7] 8000e1e: 095b lsrs r3, r3, #5 8000e20: 2001 movs r0, #1 8000e22: fa00 f202 lsl.w r2, r0, r2 8000e26: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8000e2a: bf00 nop 8000e2c: 370c adds r7, #12 8000e2e: 46bd mov sp, r7 8000e30: f85d 7b04 ldr.w r7, [sp], #4 8000e34: 4770 bx lr 8000e36: bf00 nop 8000e38: e000e100 .word 0xe000e100 08000e3c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000e3c: b480 push {r7} 8000e3e: b083 sub sp, #12 8000e40: af00 add r7, sp, #0 8000e42: 4603 mov r3, r0 8000e44: 6039 str r1, [r7, #0] 8000e46: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000e48: f997 3007 ldrsb.w r3, [r7, #7] 8000e4c: 2b00 cmp r3, #0 8000e4e: db0a blt.n 8000e66 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000e50: 683b ldr r3, [r7, #0] 8000e52: b2da uxtb r2, r3 8000e54: 490c ldr r1, [pc, #48] ; (8000e88 <__NVIC_SetPriority+0x4c>) 8000e56: f997 3007 ldrsb.w r3, [r7, #7] 8000e5a: 0112 lsls r2, r2, #4 8000e5c: b2d2 uxtb r2, r2 8000e5e: 440b add r3, r1 8000e60: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8000e64: e00a b.n 8000e7c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000e66: 683b ldr r3, [r7, #0] 8000e68: b2da uxtb r2, r3 8000e6a: 4908 ldr r1, [pc, #32] ; (8000e8c <__NVIC_SetPriority+0x50>) 8000e6c: 79fb ldrb r3, [r7, #7] 8000e6e: f003 030f and.w r3, r3, #15 8000e72: 3b04 subs r3, #4 8000e74: 0112 lsls r2, r2, #4 8000e76: b2d2 uxtb r2, r2 8000e78: 440b add r3, r1 8000e7a: 761a strb r2, [r3, #24] } 8000e7c: bf00 nop 8000e7e: 370c adds r7, #12 8000e80: 46bd mov sp, r7 8000e82: f85d 7b04 ldr.w r7, [sp], #4 8000e86: 4770 bx lr 8000e88: e000e100 .word 0xe000e100 8000e8c: e000ed00 .word 0xe000ed00 08000e90 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8000e90: b480 push {r7} 8000e92: b089 sub sp, #36 ; 0x24 8000e94: af00 add r7, sp, #0 8000e96: 60f8 str r0, [r7, #12] 8000e98: 60b9 str r1, [r7, #8] 8000e9a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000e9c: 68fb ldr r3, [r7, #12] 8000e9e: f003 0307 and.w r3, r3, #7 8000ea2: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000ea4: 69fb ldr r3, [r7, #28] 8000ea6: f1c3 0307 rsb r3, r3, #7 8000eaa: 2b04 cmp r3, #4 8000eac: bf28 it cs 8000eae: 2304 movcs r3, #4 8000eb0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8000eb2: 69fb ldr r3, [r7, #28] 8000eb4: 3304 adds r3, #4 8000eb6: 2b06 cmp r3, #6 8000eb8: d902 bls.n 8000ec0 8000eba: 69fb ldr r3, [r7, #28] 8000ebc: 3b03 subs r3, #3 8000ebe: e000 b.n 8000ec2 8000ec0: 2300 movs r3, #0 8000ec2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000ec4: f04f 32ff mov.w r2, #4294967295 8000ec8: 69bb ldr r3, [r7, #24] 8000eca: fa02 f303 lsl.w r3, r2, r3 8000ece: 43da mvns r2, r3 8000ed0: 68bb ldr r3, [r7, #8] 8000ed2: 401a ands r2, r3 8000ed4: 697b ldr r3, [r7, #20] 8000ed6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000ed8: f04f 31ff mov.w r1, #4294967295 8000edc: 697b ldr r3, [r7, #20] 8000ede: fa01 f303 lsl.w r3, r1, r3 8000ee2: 43d9 mvns r1, r3 8000ee4: 687b ldr r3, [r7, #4] 8000ee6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000ee8: 4313 orrs r3, r2 ); } 8000eea: 4618 mov r0, r3 8000eec: 3724 adds r7, #36 ; 0x24 8000eee: 46bd mov sp, r7 8000ef0: f85d 7b04 ldr.w r7, [sp], #4 8000ef4: 4770 bx lr ... 08000ef8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000ef8: b580 push {r7, lr} 8000efa: b082 sub sp, #8 8000efc: af00 add r7, sp, #0 8000efe: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000f00: 687b ldr r3, [r7, #4] 8000f02: 3b01 subs r3, #1 8000f04: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8000f08: d301 bcc.n 8000f0e { return (1UL); /* Reload value impossible */ 8000f0a: 2301 movs r3, #1 8000f0c: e00f b.n 8000f2e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000f0e: 4a0a ldr r2, [pc, #40] ; (8000f38 ) 8000f10: 687b ldr r3, [r7, #4] 8000f12: 3b01 subs r3, #1 8000f14: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000f16: 210f movs r1, #15 8000f18: f04f 30ff mov.w r0, #4294967295 8000f1c: f7ff ff8e bl 8000e3c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000f20: 4b05 ldr r3, [pc, #20] ; (8000f38 ) 8000f22: 2200 movs r2, #0 8000f24: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000f26: 4b04 ldr r3, [pc, #16] ; (8000f38 ) 8000f28: 2207 movs r2, #7 8000f2a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000f2c: 2300 movs r3, #0 } 8000f2e: 4618 mov r0, r3 8000f30: 3708 adds r7, #8 8000f32: 46bd mov sp, r7 8000f34: bd80 pop {r7, pc} 8000f36: bf00 nop 8000f38: e000e010 .word 0xe000e010 08000f3c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000f3c: b580 push {r7, lr} 8000f3e: b082 sub sp, #8 8000f40: af00 add r7, sp, #0 8000f42: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000f44: 6878 ldr r0, [r7, #4] 8000f46: f7ff ff29 bl 8000d9c <__NVIC_SetPriorityGrouping> } 8000f4a: bf00 nop 8000f4c: 3708 adds r7, #8 8000f4e: 46bd mov sp, r7 8000f50: bd80 pop {r7, pc} 08000f52 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000f52: b580 push {r7, lr} 8000f54: b086 sub sp, #24 8000f56: af00 add r7, sp, #0 8000f58: 4603 mov r3, r0 8000f5a: 60b9 str r1, [r7, #8] 8000f5c: 607a str r2, [r7, #4] 8000f5e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8000f60: 2300 movs r3, #0 8000f62: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000f64: f7ff ff3e bl 8000de4 <__NVIC_GetPriorityGrouping> 8000f68: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8000f6a: 687a ldr r2, [r7, #4] 8000f6c: 68b9 ldr r1, [r7, #8] 8000f6e: 6978 ldr r0, [r7, #20] 8000f70: f7ff ff8e bl 8000e90 8000f74: 4602 mov r2, r0 8000f76: f997 300f ldrsb.w r3, [r7, #15] 8000f7a: 4611 mov r1, r2 8000f7c: 4618 mov r0, r3 8000f7e: f7ff ff5d bl 8000e3c <__NVIC_SetPriority> } 8000f82: bf00 nop 8000f84: 3718 adds r7, #24 8000f86: 46bd mov sp, r7 8000f88: bd80 pop {r7, pc} 08000f8a : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8000f8a: b580 push {r7, lr} 8000f8c: b082 sub sp, #8 8000f8e: af00 add r7, sp, #0 8000f90: 4603 mov r3, r0 8000f92: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8000f94: f997 3007 ldrsb.w r3, [r7, #7] 8000f98: 4618 mov r0, r3 8000f9a: f7ff ff31 bl 8000e00 <__NVIC_EnableIRQ> } 8000f9e: bf00 nop 8000fa0: 3708 adds r7, #8 8000fa2: 46bd mov sp, r7 8000fa4: bd80 pop {r7, pc} 08000fa6 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8000fa6: b580 push {r7, lr} 8000fa8: b082 sub sp, #8 8000faa: af00 add r7, sp, #0 8000fac: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000fae: 6878 ldr r0, [r7, #4] 8000fb0: f7ff ffa2 bl 8000ef8 8000fb4: 4603 mov r3, r0 } 8000fb6: 4618 mov r0, r3 8000fb8: 3708 adds r7, #8 8000fba: 46bd mov sp, r7 8000fbc: bd80 pop {r7, pc} ... 08000fc0 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000fc0: b480 push {r7} 8000fc2: b089 sub sp, #36 ; 0x24 8000fc4: af00 add r7, sp, #0 8000fc6: 6078 str r0, [r7, #4] 8000fc8: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 8000fca: 2300 movs r3, #0 8000fcc: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 8000fce: 2300 movs r3, #0 8000fd0: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8000fd2: 2300 movs r3, #0 8000fd4: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8000fd6: 2300 movs r3, #0 8000fd8: 61fb str r3, [r7, #28] 8000fda: e16b b.n 80012b4 { /* Get the IO position */ ioposition = 0x01U << position; 8000fdc: 2201 movs r2, #1 8000fde: 69fb ldr r3, [r7, #28] 8000fe0: fa02 f303 lsl.w r3, r2, r3 8000fe4: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8000fe6: 683b ldr r3, [r7, #0] 8000fe8: 681b ldr r3, [r3, #0] 8000fea: 697a ldr r2, [r7, #20] 8000fec: 4013 ands r3, r2 8000fee: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8000ff0: 693a ldr r2, [r7, #16] 8000ff2: 697b ldr r3, [r7, #20] 8000ff4: 429a cmp r2, r3 8000ff6: f040 815a bne.w 80012ae { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8000ffa: 683b ldr r3, [r7, #0] 8000ffc: 685b ldr r3, [r3, #4] 8000ffe: f003 0303 and.w r3, r3, #3 8001002: 2b01 cmp r3, #1 8001004: d005 beq.n 8001012 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001006: 683b ldr r3, [r7, #0] 8001008: 685b ldr r3, [r3, #4] 800100a: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 800100e: 2b02 cmp r3, #2 8001010: d130 bne.n 8001074 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001012: 687b ldr r3, [r7, #4] 8001014: 689b ldr r3, [r3, #8] 8001016: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8001018: 69fb ldr r3, [r7, #28] 800101a: 005b lsls r3, r3, #1 800101c: 2203 movs r2, #3 800101e: fa02 f303 lsl.w r3, r2, r3 8001022: 43db mvns r3, r3 8001024: 69ba ldr r2, [r7, #24] 8001026: 4013 ands r3, r2 8001028: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800102a: 683b ldr r3, [r7, #0] 800102c: 68da ldr r2, [r3, #12] 800102e: 69fb ldr r3, [r7, #28] 8001030: 005b lsls r3, r3, #1 8001032: fa02 f303 lsl.w r3, r2, r3 8001036: 69ba ldr r2, [r7, #24] 8001038: 4313 orrs r3, r2 800103a: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800103c: 687b ldr r3, [r7, #4] 800103e: 69ba ldr r2, [r7, #24] 8001040: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001042: 687b ldr r3, [r7, #4] 8001044: 685b ldr r3, [r3, #4] 8001046: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8001048: 2201 movs r2, #1 800104a: 69fb ldr r3, [r7, #28] 800104c: fa02 f303 lsl.w r3, r2, r3 8001050: 43db mvns r3, r3 8001052: 69ba ldr r2, [r7, #24] 8001054: 4013 ands r3, r2 8001056: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001058: 683b ldr r3, [r7, #0] 800105a: 685b ldr r3, [r3, #4] 800105c: 091b lsrs r3, r3, #4 800105e: f003 0201 and.w r2, r3, #1 8001062: 69fb ldr r3, [r7, #28] 8001064: fa02 f303 lsl.w r3, r2, r3 8001068: 69ba ldr r2, [r7, #24] 800106a: 4313 orrs r3, r2 800106c: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800106e: 687b ldr r3, [r7, #4] 8001070: 69ba ldr r2, [r7, #24] 8001072: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001074: 683b ldr r3, [r7, #0] 8001076: 685b ldr r3, [r3, #4] 8001078: f003 0303 and.w r3, r3, #3 800107c: 2b03 cmp r3, #3 800107e: d017 beq.n 80010b0 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8001080: 687b ldr r3, [r7, #4] 8001082: 68db ldr r3, [r3, #12] 8001084: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8001086: 69fb ldr r3, [r7, #28] 8001088: 005b lsls r3, r3, #1 800108a: 2203 movs r2, #3 800108c: fa02 f303 lsl.w r3, r2, r3 8001090: 43db mvns r3, r3 8001092: 69ba ldr r2, [r7, #24] 8001094: 4013 ands r3, r2 8001096: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8001098: 683b ldr r3, [r7, #0] 800109a: 689a ldr r2, [r3, #8] 800109c: 69fb ldr r3, [r7, #28] 800109e: 005b lsls r3, r3, #1 80010a0: fa02 f303 lsl.w r3, r2, r3 80010a4: 69ba ldr r2, [r7, #24] 80010a6: 4313 orrs r3, r2 80010a8: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 80010aa: 687b ldr r3, [r7, #4] 80010ac: 69ba ldr r2, [r7, #24] 80010ae: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80010b0: 683b ldr r3, [r7, #0] 80010b2: 685b ldr r3, [r3, #4] 80010b4: f003 0303 and.w r3, r3, #3 80010b8: 2b02 cmp r3, #2 80010ba: d123 bne.n 8001104 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 80010bc: 69fb ldr r3, [r7, #28] 80010be: 08da lsrs r2, r3, #3 80010c0: 687b ldr r3, [r7, #4] 80010c2: 3208 adds r2, #8 80010c4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80010c8: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 80010ca: 69fb ldr r3, [r7, #28] 80010cc: f003 0307 and.w r3, r3, #7 80010d0: 009b lsls r3, r3, #2 80010d2: 220f movs r2, #15 80010d4: fa02 f303 lsl.w r3, r2, r3 80010d8: 43db mvns r3, r3 80010da: 69ba ldr r2, [r7, #24] 80010dc: 4013 ands r3, r2 80010de: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 80010e0: 683b ldr r3, [r7, #0] 80010e2: 691a ldr r2, [r3, #16] 80010e4: 69fb ldr r3, [r7, #28] 80010e6: f003 0307 and.w r3, r3, #7 80010ea: 009b lsls r3, r3, #2 80010ec: fa02 f303 lsl.w r3, r2, r3 80010f0: 69ba ldr r2, [r7, #24] 80010f2: 4313 orrs r3, r2 80010f4: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 80010f6: 69fb ldr r3, [r7, #28] 80010f8: 08da lsrs r2, r3, #3 80010fa: 687b ldr r3, [r7, #4] 80010fc: 3208 adds r2, #8 80010fe: 69b9 ldr r1, [r7, #24] 8001100: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001104: 687b ldr r3, [r7, #4] 8001106: 681b ldr r3, [r3, #0] 8001108: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 800110a: 69fb ldr r3, [r7, #28] 800110c: 005b lsls r3, r3, #1 800110e: 2203 movs r2, #3 8001110: fa02 f303 lsl.w r3, r2, r3 8001114: 43db mvns r3, r3 8001116: 69ba ldr r2, [r7, #24] 8001118: 4013 ands r3, r2 800111a: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800111c: 683b ldr r3, [r7, #0] 800111e: 685b ldr r3, [r3, #4] 8001120: f003 0203 and.w r2, r3, #3 8001124: 69fb ldr r3, [r7, #28] 8001126: 005b lsls r3, r3, #1 8001128: fa02 f303 lsl.w r3, r2, r3 800112c: 69ba ldr r2, [r7, #24] 800112e: 4313 orrs r3, r2 8001130: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8001132: 687b ldr r3, [r7, #4] 8001134: 69ba ldr r2, [r7, #24] 8001136: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8001138: 683b ldr r3, [r7, #0] 800113a: 685b ldr r3, [r3, #4] 800113c: f403 3340 and.w r3, r3, #196608 ; 0x30000 8001140: 2b00 cmp r3, #0 8001142: f000 80b4 beq.w 80012ae { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001146: 2300 movs r3, #0 8001148: 60fb str r3, [r7, #12] 800114a: 4b60 ldr r3, [pc, #384] ; (80012cc ) 800114c: 6c5b ldr r3, [r3, #68] ; 0x44 800114e: 4a5f ldr r2, [pc, #380] ; (80012cc ) 8001150: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8001154: 6453 str r3, [r2, #68] ; 0x44 8001156: 4b5d ldr r3, [pc, #372] ; (80012cc ) 8001158: 6c5b ldr r3, [r3, #68] ; 0x44 800115a: f403 4380 and.w r3, r3, #16384 ; 0x4000 800115e: 60fb str r3, [r7, #12] 8001160: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8001162: 4a5b ldr r2, [pc, #364] ; (80012d0 ) 8001164: 69fb ldr r3, [r7, #28] 8001166: 089b lsrs r3, r3, #2 8001168: 3302 adds r3, #2 800116a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800116e: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8001170: 69fb ldr r3, [r7, #28] 8001172: f003 0303 and.w r3, r3, #3 8001176: 009b lsls r3, r3, #2 8001178: 220f movs r2, #15 800117a: fa02 f303 lsl.w r3, r2, r3 800117e: 43db mvns r3, r3 8001180: 69ba ldr r2, [r7, #24] 8001182: 4013 ands r3, r2 8001184: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8001186: 687b ldr r3, [r7, #4] 8001188: 4a52 ldr r2, [pc, #328] ; (80012d4 ) 800118a: 4293 cmp r3, r2 800118c: d02b beq.n 80011e6 800118e: 687b ldr r3, [r7, #4] 8001190: 4a51 ldr r2, [pc, #324] ; (80012d8 ) 8001192: 4293 cmp r3, r2 8001194: d025 beq.n 80011e2 8001196: 687b ldr r3, [r7, #4] 8001198: 4a50 ldr r2, [pc, #320] ; (80012dc ) 800119a: 4293 cmp r3, r2 800119c: d01f beq.n 80011de 800119e: 687b ldr r3, [r7, #4] 80011a0: 4a4f ldr r2, [pc, #316] ; (80012e0 ) 80011a2: 4293 cmp r3, r2 80011a4: d019 beq.n 80011da 80011a6: 687b ldr r3, [r7, #4] 80011a8: 4a4e ldr r2, [pc, #312] ; (80012e4 ) 80011aa: 4293 cmp r3, r2 80011ac: d013 beq.n 80011d6 80011ae: 687b ldr r3, [r7, #4] 80011b0: 4a4d ldr r2, [pc, #308] ; (80012e8 ) 80011b2: 4293 cmp r3, r2 80011b4: d00d beq.n 80011d2 80011b6: 687b ldr r3, [r7, #4] 80011b8: 4a4c ldr r2, [pc, #304] ; (80012ec ) 80011ba: 4293 cmp r3, r2 80011bc: d007 beq.n 80011ce 80011be: 687b ldr r3, [r7, #4] 80011c0: 4a4b ldr r2, [pc, #300] ; (80012f0 ) 80011c2: 4293 cmp r3, r2 80011c4: d101 bne.n 80011ca 80011c6: 2307 movs r3, #7 80011c8: e00e b.n 80011e8 80011ca: 2308 movs r3, #8 80011cc: e00c b.n 80011e8 80011ce: 2306 movs r3, #6 80011d0: e00a b.n 80011e8 80011d2: 2305 movs r3, #5 80011d4: e008 b.n 80011e8 80011d6: 2304 movs r3, #4 80011d8: e006 b.n 80011e8 80011da: 2303 movs r3, #3 80011dc: e004 b.n 80011e8 80011de: 2302 movs r3, #2 80011e0: e002 b.n 80011e8 80011e2: 2301 movs r3, #1 80011e4: e000 b.n 80011e8 80011e6: 2300 movs r3, #0 80011e8: 69fa ldr r2, [r7, #28] 80011ea: f002 0203 and.w r2, r2, #3 80011ee: 0092 lsls r2, r2, #2 80011f0: 4093 lsls r3, r2 80011f2: 69ba ldr r2, [r7, #24] 80011f4: 4313 orrs r3, r2 80011f6: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 80011f8: 4935 ldr r1, [pc, #212] ; (80012d0 ) 80011fa: 69fb ldr r3, [r7, #28] 80011fc: 089b lsrs r3, r3, #2 80011fe: 3302 adds r3, #2 8001200: 69ba ldr r2, [r7, #24] 8001202: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8001206: 4b3b ldr r3, [pc, #236] ; (80012f4 ) 8001208: 689b ldr r3, [r3, #8] 800120a: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800120c: 693b ldr r3, [r7, #16] 800120e: 43db mvns r3, r3 8001210: 69ba ldr r2, [r7, #24] 8001212: 4013 ands r3, r2 8001214: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8001216: 683b ldr r3, [r7, #0] 8001218: 685b ldr r3, [r3, #4] 800121a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 800121e: 2b00 cmp r3, #0 8001220: d003 beq.n 800122a { temp |= iocurrent; 8001222: 69ba ldr r2, [r7, #24] 8001224: 693b ldr r3, [r7, #16] 8001226: 4313 orrs r3, r2 8001228: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 800122a: 4a32 ldr r2, [pc, #200] ; (80012f4 ) 800122c: 69bb ldr r3, [r7, #24] 800122e: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8001230: 4b30 ldr r3, [pc, #192] ; (80012f4 ) 8001232: 68db ldr r3, [r3, #12] 8001234: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001236: 693b ldr r3, [r7, #16] 8001238: 43db mvns r3, r3 800123a: 69ba ldr r2, [r7, #24] 800123c: 4013 ands r3, r2 800123e: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8001240: 683b ldr r3, [r7, #0] 8001242: 685b ldr r3, [r3, #4] 8001244: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001248: 2b00 cmp r3, #0 800124a: d003 beq.n 8001254 { temp |= iocurrent; 800124c: 69ba ldr r2, [r7, #24] 800124e: 693b ldr r3, [r7, #16] 8001250: 4313 orrs r3, r2 8001252: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8001254: 4a27 ldr r2, [pc, #156] ; (80012f4 ) 8001256: 69bb ldr r3, [r7, #24] 8001258: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 800125a: 4b26 ldr r3, [pc, #152] ; (80012f4 ) 800125c: 685b ldr r3, [r3, #4] 800125e: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001260: 693b ldr r3, [r7, #16] 8001262: 43db mvns r3, r3 8001264: 69ba ldr r2, [r7, #24] 8001266: 4013 ands r3, r2 8001268: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800126a: 683b ldr r3, [r7, #0] 800126c: 685b ldr r3, [r3, #4] 800126e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001272: 2b00 cmp r3, #0 8001274: d003 beq.n 800127e { temp |= iocurrent; 8001276: 69ba ldr r2, [r7, #24] 8001278: 693b ldr r3, [r7, #16] 800127a: 4313 orrs r3, r2 800127c: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 800127e: 4a1d ldr r2, [pc, #116] ; (80012f4 ) 8001280: 69bb ldr r3, [r7, #24] 8001282: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8001284: 4b1b ldr r3, [pc, #108] ; (80012f4 ) 8001286: 681b ldr r3, [r3, #0] 8001288: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800128a: 693b ldr r3, [r7, #16] 800128c: 43db mvns r3, r3 800128e: 69ba ldr r2, [r7, #24] 8001290: 4013 ands r3, r2 8001292: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8001294: 683b ldr r3, [r7, #0] 8001296: 685b ldr r3, [r3, #4] 8001298: f403 3380 and.w r3, r3, #65536 ; 0x10000 800129c: 2b00 cmp r3, #0 800129e: d003 beq.n 80012a8 { temp |= iocurrent; 80012a0: 69ba ldr r2, [r7, #24] 80012a2: 693b ldr r3, [r7, #16] 80012a4: 4313 orrs r3, r2 80012a6: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 80012a8: 4a12 ldr r2, [pc, #72] ; (80012f4 ) 80012aa: 69bb ldr r3, [r7, #24] 80012ac: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 80012ae: 69fb ldr r3, [r7, #28] 80012b0: 3301 adds r3, #1 80012b2: 61fb str r3, [r7, #28] 80012b4: 69fb ldr r3, [r7, #28] 80012b6: 2b0f cmp r3, #15 80012b8: f67f ae90 bls.w 8000fdc } } } } 80012bc: bf00 nop 80012be: bf00 nop 80012c0: 3724 adds r7, #36 ; 0x24 80012c2: 46bd mov sp, r7 80012c4: f85d 7b04 ldr.w r7, [sp], #4 80012c8: 4770 bx lr 80012ca: bf00 nop 80012cc: 40023800 .word 0x40023800 80012d0: 40013800 .word 0x40013800 80012d4: 40020000 .word 0x40020000 80012d8: 40020400 .word 0x40020400 80012dc: 40020800 .word 0x40020800 80012e0: 40020c00 .word 0x40020c00 80012e4: 40021000 .word 0x40021000 80012e8: 40021400 .word 0x40021400 80012ec: 40021800 .word 0x40021800 80012f0: 40021c00 .word 0x40021c00 80012f4: 40013c00 .word 0x40013c00 080012f8 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80012f8: b480 push {r7} 80012fa: b083 sub sp, #12 80012fc: af00 add r7, sp, #0 80012fe: 6078 str r0, [r7, #4] 8001300: 460b mov r3, r1 8001302: 807b strh r3, [r7, #2] 8001304: 4613 mov r3, r2 8001306: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8001308: 787b ldrb r3, [r7, #1] 800130a: 2b00 cmp r3, #0 800130c: d003 beq.n 8001316 { GPIOx->BSRR = GPIO_Pin; 800130e: 887a ldrh r2, [r7, #2] 8001310: 687b ldr r3, [r7, #4] 8001312: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8001314: e003 b.n 800131e GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8001316: 887b ldrh r3, [r7, #2] 8001318: 041a lsls r2, r3, #16 800131a: 687b ldr r3, [r7, #4] 800131c: 619a str r2, [r3, #24] } 800131e: bf00 nop 8001320: 370c adds r7, #12 8001322: 46bd mov sp, r7 8001324: f85d 7b04 ldr.w r7, [sp], #4 8001328: 4770 bx lr 0800132a : * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. * @param GPIO_Pin Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 800132a: b480 push {r7} 800132c: b085 sub sp, #20 800132e: af00 add r7, sp, #0 8001330: 6078 str r0, [r7, #4] 8001332: 460b mov r3, r1 8001334: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 8001336: 687b ldr r3, [r7, #4] 8001338: 695b ldr r3, [r3, #20] 800133a: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 800133c: 887a ldrh r2, [r7, #2] 800133e: 68fb ldr r3, [r7, #12] 8001340: 4013 ands r3, r2 8001342: 041a lsls r2, r3, #16 8001344: 68fb ldr r3, [r7, #12] 8001346: 43d9 mvns r1, r3 8001348: 887b ldrh r3, [r7, #2] 800134a: 400b ands r3, r1 800134c: 431a orrs r2, r3 800134e: 687b ldr r3, [r7, #4] 8001350: 619a str r2, [r3, #24] } 8001352: bf00 nop 8001354: 3714 adds r7, #20 8001356: 46bd mov sp, r7 8001358: f85d 7b04 ldr.w r7, [sp], #4 800135c: 4770 bx lr ... 08001360 : * supported by this API. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8001360: b580 push {r7, lr} 8001362: b086 sub sp, #24 8001364: af00 add r7, sp, #0 8001366: 6078 str r0, [r7, #4] uint32_t tickstart, pll_config; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8001368: 687b ldr r3, [r7, #4] 800136a: 2b00 cmp r3, #0 800136c: d101 bne.n 8001372 { return HAL_ERROR; 800136e: 2301 movs r3, #1 8001370: e267 b.n 8001842 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8001372: 687b ldr r3, [r7, #4] 8001374: 681b ldr r3, [r3, #0] 8001376: f003 0301 and.w r3, r3, #1 800137a: 2b00 cmp r3, #0 800137c: d075 beq.n 800146a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ 800137e: 4b88 ldr r3, [pc, #544] ; (80015a0 ) 8001380: 689b ldr r3, [r3, #8] 8001382: f003 030c and.w r3, r3, #12 8001386: 2b04 cmp r3, #4 8001388: d00c beq.n 80013a4 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 800138a: 4b85 ldr r3, [pc, #532] ; (80015a0 ) 800138c: 689b ldr r3, [r3, #8] 800138e: f003 030c and.w r3, r3, #12 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ 8001392: 2b08 cmp r3, #8 8001394: d112 bne.n 80013bc ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8001396: 4b82 ldr r3, [pc, #520] ; (80015a0 ) 8001398: 685b ldr r3, [r3, #4] 800139a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 800139e: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 80013a2: d10b bne.n 80013bc { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80013a4: 4b7e ldr r3, [pc, #504] ; (80015a0 ) 80013a6: 681b ldr r3, [r3, #0] 80013a8: f403 3300 and.w r3, r3, #131072 ; 0x20000 80013ac: 2b00 cmp r3, #0 80013ae: d05b beq.n 8001468 80013b0: 687b ldr r3, [r7, #4] 80013b2: 685b ldr r3, [r3, #4] 80013b4: 2b00 cmp r3, #0 80013b6: d157 bne.n 8001468 { return HAL_ERROR; 80013b8: 2301 movs r3, #1 80013ba: e242 b.n 8001842 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80013bc: 687b ldr r3, [r7, #4] 80013be: 685b ldr r3, [r3, #4] 80013c0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80013c4: d106 bne.n 80013d4 80013c6: 4b76 ldr r3, [pc, #472] ; (80015a0 ) 80013c8: 681b ldr r3, [r3, #0] 80013ca: 4a75 ldr r2, [pc, #468] ; (80015a0 ) 80013cc: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80013d0: 6013 str r3, [r2, #0] 80013d2: e01d b.n 8001410 80013d4: 687b ldr r3, [r7, #4] 80013d6: 685b ldr r3, [r3, #4] 80013d8: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80013dc: d10c bne.n 80013f8 80013de: 4b70 ldr r3, [pc, #448] ; (80015a0 ) 80013e0: 681b ldr r3, [r3, #0] 80013e2: 4a6f ldr r2, [pc, #444] ; (80015a0 ) 80013e4: f443 2380 orr.w r3, r3, #262144 ; 0x40000 80013e8: 6013 str r3, [r2, #0] 80013ea: 4b6d ldr r3, [pc, #436] ; (80015a0 ) 80013ec: 681b ldr r3, [r3, #0] 80013ee: 4a6c ldr r2, [pc, #432] ; (80015a0 ) 80013f0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80013f4: 6013 str r3, [r2, #0] 80013f6: e00b b.n 8001410 80013f8: 4b69 ldr r3, [pc, #420] ; (80015a0 ) 80013fa: 681b ldr r3, [r3, #0] 80013fc: 4a68 ldr r2, [pc, #416] ; (80015a0 ) 80013fe: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8001402: 6013 str r3, [r2, #0] 8001404: 4b66 ldr r3, [pc, #408] ; (80015a0 ) 8001406: 681b ldr r3, [r3, #0] 8001408: 4a65 ldr r2, [pc, #404] ; (80015a0 ) 800140a: f423 2380 bic.w r3, r3, #262144 ; 0x40000 800140e: 6013 str r3, [r2, #0] /* Check the HSE State */ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 8001410: 687b ldr r3, [r7, #4] 8001412: 685b ldr r3, [r3, #4] 8001414: 2b00 cmp r3, #0 8001416: d013 beq.n 8001440 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001418: f7ff fcb4 bl 8000d84 800141c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800141e: e008 b.n 8001432 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8001420: f7ff fcb0 bl 8000d84 8001424: 4602 mov r2, r0 8001426: 693b ldr r3, [r7, #16] 8001428: 1ad3 subs r3, r2, r3 800142a: 2b64 cmp r3, #100 ; 0x64 800142c: d901 bls.n 8001432 { return HAL_TIMEOUT; 800142e: 2303 movs r3, #3 8001430: e207 b.n 8001842 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001432: 4b5b ldr r3, [pc, #364] ; (80015a0 ) 8001434: 681b ldr r3, [r3, #0] 8001436: f403 3300 and.w r3, r3, #131072 ; 0x20000 800143a: 2b00 cmp r3, #0 800143c: d0f0 beq.n 8001420 800143e: e014 b.n 800146a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001440: f7ff fca0 bl 8000d84 8001444: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001446: e008 b.n 800145a { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8001448: f7ff fc9c bl 8000d84 800144c: 4602 mov r2, r0 800144e: 693b ldr r3, [r7, #16] 8001450: 1ad3 subs r3, r2, r3 8001452: 2b64 cmp r3, #100 ; 0x64 8001454: d901 bls.n 800145a { return HAL_TIMEOUT; 8001456: 2303 movs r3, #3 8001458: e1f3 b.n 8001842 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800145a: 4b51 ldr r3, [pc, #324] ; (80015a0 ) 800145c: 681b ldr r3, [r3, #0] 800145e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001462: 2b00 cmp r3, #0 8001464: d1f0 bne.n 8001448 8001466: e000 b.n 800146a if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001468: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800146a: 687b ldr r3, [r7, #4] 800146c: 681b ldr r3, [r3, #0] 800146e: f003 0302 and.w r3, r3, #2 8001472: 2b00 cmp r3, #0 8001474: d063 beq.n 800153e /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ 8001476: 4b4a ldr r3, [pc, #296] ; (80015a0 ) 8001478: 689b ldr r3, [r3, #8] 800147a: f003 030c and.w r3, r3, #12 800147e: 2b00 cmp r3, #0 8001480: d00b beq.n 800149a ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8001482: 4b47 ldr r3, [pc, #284] ; (80015a0 ) 8001484: 689b ldr r3, [r3, #8] 8001486: f003 030c and.w r3, r3, #12 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ 800148a: 2b08 cmp r3, #8 800148c: d11c bne.n 80014c8 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 800148e: 4b44 ldr r3, [pc, #272] ; (80015a0 ) 8001490: 685b ldr r3, [r3, #4] 8001492: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8001496: 2b00 cmp r3, #0 8001498: d116 bne.n 80014c8 { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800149a: 4b41 ldr r3, [pc, #260] ; (80015a0 ) 800149c: 681b ldr r3, [r3, #0] 800149e: f003 0302 and.w r3, r3, #2 80014a2: 2b00 cmp r3, #0 80014a4: d005 beq.n 80014b2 80014a6: 687b ldr r3, [r7, #4] 80014a8: 68db ldr r3, [r3, #12] 80014aa: 2b01 cmp r3, #1 80014ac: d001 beq.n 80014b2 { return HAL_ERROR; 80014ae: 2301 movs r3, #1 80014b0: e1c7 b.n 8001842 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80014b2: 4b3b ldr r3, [pc, #236] ; (80015a0 ) 80014b4: 681b ldr r3, [r3, #0] 80014b6: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80014ba: 687b ldr r3, [r7, #4] 80014bc: 691b ldr r3, [r3, #16] 80014be: 00db lsls r3, r3, #3 80014c0: 4937 ldr r1, [pc, #220] ; (80015a0 ) 80014c2: 4313 orrs r3, r2 80014c4: 600b str r3, [r1, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80014c6: e03a b.n 800153e } } else { /* Check the HSI State */ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) 80014c8: 687b ldr r3, [r7, #4] 80014ca: 68db ldr r3, [r3, #12] 80014cc: 2b00 cmp r3, #0 80014ce: d020 beq.n 8001512 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80014d0: 4b34 ldr r3, [pc, #208] ; (80015a4 ) 80014d2: 2201 movs r2, #1 80014d4: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80014d6: f7ff fc55 bl 8000d84 80014da: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80014dc: e008 b.n 80014f0 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80014de: f7ff fc51 bl 8000d84 80014e2: 4602 mov r2, r0 80014e4: 693b ldr r3, [r7, #16] 80014e6: 1ad3 subs r3, r2, r3 80014e8: 2b02 cmp r3, #2 80014ea: d901 bls.n 80014f0 { return HAL_TIMEOUT; 80014ec: 2303 movs r3, #3 80014ee: e1a8 b.n 8001842 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80014f0: 4b2b ldr r3, [pc, #172] ; (80015a0 ) 80014f2: 681b ldr r3, [r3, #0] 80014f4: f003 0302 and.w r3, r3, #2 80014f8: 2b00 cmp r3, #0 80014fa: d0f0 beq.n 80014de } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80014fc: 4b28 ldr r3, [pc, #160] ; (80015a0 ) 80014fe: 681b ldr r3, [r3, #0] 8001500: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8001504: 687b ldr r3, [r7, #4] 8001506: 691b ldr r3, [r3, #16] 8001508: 00db lsls r3, r3, #3 800150a: 4925 ldr r1, [pc, #148] ; (80015a0 ) 800150c: 4313 orrs r3, r2 800150e: 600b str r3, [r1, #0] 8001510: e015 b.n 800153e } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001512: 4b24 ldr r3, [pc, #144] ; (80015a4 ) 8001514: 2200 movs r2, #0 8001516: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001518: f7ff fc34 bl 8000d84 800151c: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800151e: e008 b.n 8001532 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001520: f7ff fc30 bl 8000d84 8001524: 4602 mov r2, r0 8001526: 693b ldr r3, [r7, #16] 8001528: 1ad3 subs r3, r2, r3 800152a: 2b02 cmp r3, #2 800152c: d901 bls.n 8001532 { return HAL_TIMEOUT; 800152e: 2303 movs r3, #3 8001530: e187 b.n 8001842 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001532: 4b1b ldr r3, [pc, #108] ; (80015a0 ) 8001534: 681b ldr r3, [r3, #0] 8001536: f003 0302 and.w r3, r3, #2 800153a: 2b00 cmp r3, #0 800153c: d1f0 bne.n 8001520 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800153e: 687b ldr r3, [r7, #4] 8001540: 681b ldr r3, [r3, #0] 8001542: f003 0308 and.w r3, r3, #8 8001546: 2b00 cmp r3, #0 8001548: d036 beq.n 80015b8 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) 800154a: 687b ldr r3, [r7, #4] 800154c: 695b ldr r3, [r3, #20] 800154e: 2b00 cmp r3, #0 8001550: d016 beq.n 8001580 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001552: 4b15 ldr r3, [pc, #84] ; (80015a8 ) 8001554: 2201 movs r2, #1 8001556: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001558: f7ff fc14 bl 8000d84 800155c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800155e: e008 b.n 8001572 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001560: f7ff fc10 bl 8000d84 8001564: 4602 mov r2, r0 8001566: 693b ldr r3, [r7, #16] 8001568: 1ad3 subs r3, r2, r3 800156a: 2b02 cmp r3, #2 800156c: d901 bls.n 8001572 { return HAL_TIMEOUT; 800156e: 2303 movs r3, #3 8001570: e167 b.n 8001842 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001572: 4b0b ldr r3, [pc, #44] ; (80015a0 ) 8001574: 6f5b ldr r3, [r3, #116] ; 0x74 8001576: f003 0302 and.w r3, r3, #2 800157a: 2b00 cmp r3, #0 800157c: d0f0 beq.n 8001560 800157e: e01b b.n 80015b8 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001580: 4b09 ldr r3, [pc, #36] ; (80015a8 ) 8001582: 2200 movs r2, #0 8001584: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001586: f7ff fbfd bl 8000d84 800158a: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800158c: e00e b.n 80015ac { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 800158e: f7ff fbf9 bl 8000d84 8001592: 4602 mov r2, r0 8001594: 693b ldr r3, [r7, #16] 8001596: 1ad3 subs r3, r2, r3 8001598: 2b02 cmp r3, #2 800159a: d907 bls.n 80015ac { return HAL_TIMEOUT; 800159c: 2303 movs r3, #3 800159e: e150 b.n 8001842 80015a0: 40023800 .word 0x40023800 80015a4: 42470000 .word 0x42470000 80015a8: 42470e80 .word 0x42470e80 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80015ac: 4b88 ldr r3, [pc, #544] ; (80017d0 ) 80015ae: 6f5b ldr r3, [r3, #116] ; 0x74 80015b0: f003 0302 and.w r3, r3, #2 80015b4: 2b00 cmp r3, #0 80015b6: d1ea bne.n 800158e } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80015b8: 687b ldr r3, [r7, #4] 80015ba: 681b ldr r3, [r3, #0] 80015bc: f003 0304 and.w r3, r3, #4 80015c0: 2b00 cmp r3, #0 80015c2: f000 8097 beq.w 80016f4 { FlagStatus pwrclkchanged = RESET; 80015c6: 2300 movs r3, #0 80015c8: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 80015ca: 4b81 ldr r3, [pc, #516] ; (80017d0 ) 80015cc: 6c1b ldr r3, [r3, #64] ; 0x40 80015ce: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80015d2: 2b00 cmp r3, #0 80015d4: d10f bne.n 80015f6 { __HAL_RCC_PWR_CLK_ENABLE(); 80015d6: 2300 movs r3, #0 80015d8: 60bb str r3, [r7, #8] 80015da: 4b7d ldr r3, [pc, #500] ; (80017d0 ) 80015dc: 6c1b ldr r3, [r3, #64] ; 0x40 80015de: 4a7c ldr r2, [pc, #496] ; (80017d0 ) 80015e0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80015e4: 6413 str r3, [r2, #64] ; 0x40 80015e6: 4b7a ldr r3, [pc, #488] ; (80017d0 ) 80015e8: 6c1b ldr r3, [r3, #64] ; 0x40 80015ea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80015ee: 60bb str r3, [r7, #8] 80015f0: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80015f2: 2301 movs r3, #1 80015f4: 75fb strb r3, [r7, #23] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80015f6: 4b77 ldr r3, [pc, #476] ; (80017d4 ) 80015f8: 681b ldr r3, [r3, #0] 80015fa: f403 7380 and.w r3, r3, #256 ; 0x100 80015fe: 2b00 cmp r3, #0 8001600: d118 bne.n 8001634 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8001602: 4b74 ldr r3, [pc, #464] ; (80017d4 ) 8001604: 681b ldr r3, [r3, #0] 8001606: 4a73 ldr r2, [pc, #460] ; (80017d4 ) 8001608: f443 7380 orr.w r3, r3, #256 ; 0x100 800160c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800160e: f7ff fbb9 bl 8000d84 8001612: 6138 str r0, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001614: e008 b.n 8001628 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8001616: f7ff fbb5 bl 8000d84 800161a: 4602 mov r2, r0 800161c: 693b ldr r3, [r7, #16] 800161e: 1ad3 subs r3, r2, r3 8001620: 2b02 cmp r3, #2 8001622: d901 bls.n 8001628 { return HAL_TIMEOUT; 8001624: 2303 movs r3, #3 8001626: e10c b.n 8001842 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001628: 4b6a ldr r3, [pc, #424] ; (80017d4 ) 800162a: 681b ldr r3, [r3, #0] 800162c: f403 7380 and.w r3, r3, #256 ; 0x100 8001630: 2b00 cmp r3, #0 8001632: d0f0 beq.n 8001616 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8001634: 687b ldr r3, [r7, #4] 8001636: 689b ldr r3, [r3, #8] 8001638: 2b01 cmp r3, #1 800163a: d106 bne.n 800164a 800163c: 4b64 ldr r3, [pc, #400] ; (80017d0 ) 800163e: 6f1b ldr r3, [r3, #112] ; 0x70 8001640: 4a63 ldr r2, [pc, #396] ; (80017d0 ) 8001642: f043 0301 orr.w r3, r3, #1 8001646: 6713 str r3, [r2, #112] ; 0x70 8001648: e01c b.n 8001684 800164a: 687b ldr r3, [r7, #4] 800164c: 689b ldr r3, [r3, #8] 800164e: 2b05 cmp r3, #5 8001650: d10c bne.n 800166c 8001652: 4b5f ldr r3, [pc, #380] ; (80017d0 ) 8001654: 6f1b ldr r3, [r3, #112] ; 0x70 8001656: 4a5e ldr r2, [pc, #376] ; (80017d0 ) 8001658: f043 0304 orr.w r3, r3, #4 800165c: 6713 str r3, [r2, #112] ; 0x70 800165e: 4b5c ldr r3, [pc, #368] ; (80017d0 ) 8001660: 6f1b ldr r3, [r3, #112] ; 0x70 8001662: 4a5b ldr r2, [pc, #364] ; (80017d0 ) 8001664: f043 0301 orr.w r3, r3, #1 8001668: 6713 str r3, [r2, #112] ; 0x70 800166a: e00b b.n 8001684 800166c: 4b58 ldr r3, [pc, #352] ; (80017d0 ) 800166e: 6f1b ldr r3, [r3, #112] ; 0x70 8001670: 4a57 ldr r2, [pc, #348] ; (80017d0 ) 8001672: f023 0301 bic.w r3, r3, #1 8001676: 6713 str r3, [r2, #112] ; 0x70 8001678: 4b55 ldr r3, [pc, #340] ; (80017d0 ) 800167a: 6f1b ldr r3, [r3, #112] ; 0x70 800167c: 4a54 ldr r2, [pc, #336] ; (80017d0 ) 800167e: f023 0304 bic.w r3, r3, #4 8001682: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8001684: 687b ldr r3, [r7, #4] 8001686: 689b ldr r3, [r3, #8] 8001688: 2b00 cmp r3, #0 800168a: d015 beq.n 80016b8 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800168c: f7ff fb7a bl 8000d84 8001690: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001692: e00a b.n 80016aa { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001694: f7ff fb76 bl 8000d84 8001698: 4602 mov r2, r0 800169a: 693b ldr r3, [r7, #16] 800169c: 1ad3 subs r3, r2, r3 800169e: f241 3288 movw r2, #5000 ; 0x1388 80016a2: 4293 cmp r3, r2 80016a4: d901 bls.n 80016aa { return HAL_TIMEOUT; 80016a6: 2303 movs r3, #3 80016a8: e0cb b.n 8001842 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80016aa: 4b49 ldr r3, [pc, #292] ; (80017d0 ) 80016ac: 6f1b ldr r3, [r3, #112] ; 0x70 80016ae: f003 0302 and.w r3, r3, #2 80016b2: 2b00 cmp r3, #0 80016b4: d0ee beq.n 8001694 80016b6: e014 b.n 80016e2 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80016b8: f7ff fb64 bl 8000d84 80016bc: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80016be: e00a b.n 80016d6 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80016c0: f7ff fb60 bl 8000d84 80016c4: 4602 mov r2, r0 80016c6: 693b ldr r3, [r7, #16] 80016c8: 1ad3 subs r3, r2, r3 80016ca: f241 3288 movw r2, #5000 ; 0x1388 80016ce: 4293 cmp r3, r2 80016d0: d901 bls.n 80016d6 { return HAL_TIMEOUT; 80016d2: 2303 movs r3, #3 80016d4: e0b5 b.n 8001842 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80016d6: 4b3e ldr r3, [pc, #248] ; (80017d0 ) 80016d8: 6f1b ldr r3, [r3, #112] ; 0x70 80016da: f003 0302 and.w r3, r3, #2 80016de: 2b00 cmp r3, #0 80016e0: d1ee bne.n 80016c0 } } } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 80016e2: 7dfb ldrb r3, [r7, #23] 80016e4: 2b01 cmp r3, #1 80016e6: d105 bne.n 80016f4 { __HAL_RCC_PWR_CLK_DISABLE(); 80016e8: 4b39 ldr r3, [pc, #228] ; (80017d0 ) 80016ea: 6c1b ldr r3, [r3, #64] ; 0x40 80016ec: 4a38 ldr r2, [pc, #224] ; (80017d0 ) 80016ee: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 80016f2: 6413 str r3, [r2, #64] ; 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80016f4: 687b ldr r3, [r7, #4] 80016f6: 699b ldr r3, [r3, #24] 80016f8: 2b00 cmp r3, #0 80016fa: f000 80a1 beq.w 8001840 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 80016fe: 4b34 ldr r3, [pc, #208] ; (80017d0 ) 8001700: 689b ldr r3, [r3, #8] 8001702: f003 030c and.w r3, r3, #12 8001706: 2b08 cmp r3, #8 8001708: d05c beq.n 80017c4 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800170a: 687b ldr r3, [r7, #4] 800170c: 699b ldr r3, [r3, #24] 800170e: 2b02 cmp r3, #2 8001710: d141 bne.n 8001796 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001712: 4b31 ldr r3, [pc, #196] ; (80017d8 ) 8001714: 2200 movs r2, #0 8001716: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001718: f7ff fb34 bl 8000d84 800171c: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800171e: e008 b.n 8001732 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001720: f7ff fb30 bl 8000d84 8001724: 4602 mov r2, r0 8001726: 693b ldr r3, [r7, #16] 8001728: 1ad3 subs r3, r2, r3 800172a: 2b02 cmp r3, #2 800172c: d901 bls.n 8001732 { return HAL_TIMEOUT; 800172e: 2303 movs r3, #3 8001730: e087 b.n 8001842 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001732: 4b27 ldr r3, [pc, #156] ; (80017d0 ) 8001734: 681b ldr r3, [r3, #0] 8001736: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800173a: 2b00 cmp r3, #0 800173c: d1f0 bne.n 8001720 } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 800173e: 687b ldr r3, [r7, #4] 8001740: 69da ldr r2, [r3, #28] 8001742: 687b ldr r3, [r7, #4] 8001744: 6a1b ldr r3, [r3, #32] 8001746: 431a orrs r2, r3 8001748: 687b ldr r3, [r7, #4] 800174a: 6a5b ldr r3, [r3, #36] ; 0x24 800174c: 019b lsls r3, r3, #6 800174e: 431a orrs r2, r3 8001750: 687b ldr r3, [r7, #4] 8001752: 6a9b ldr r3, [r3, #40] ; 0x28 8001754: 085b lsrs r3, r3, #1 8001756: 3b01 subs r3, #1 8001758: 041b lsls r3, r3, #16 800175a: 431a orrs r2, r3 800175c: 687b ldr r3, [r7, #4] 800175e: 6adb ldr r3, [r3, #44] ; 0x2c 8001760: 061b lsls r3, r3, #24 8001762: 491b ldr r1, [pc, #108] ; (80017d0 ) 8001764: 4313 orrs r3, r2 8001766: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLM | \ (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001768: 4b1b ldr r3, [pc, #108] ; (80017d8 ) 800176a: 2201 movs r2, #1 800176c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800176e: f7ff fb09 bl 8000d84 8001772: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001774: e008 b.n 8001788 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001776: f7ff fb05 bl 8000d84 800177a: 4602 mov r2, r0 800177c: 693b ldr r3, [r7, #16] 800177e: 1ad3 subs r3, r2, r3 8001780: 2b02 cmp r3, #2 8001782: d901 bls.n 8001788 { return HAL_TIMEOUT; 8001784: 2303 movs r3, #3 8001786: e05c b.n 8001842 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001788: 4b11 ldr r3, [pc, #68] ; (80017d0 ) 800178a: 681b ldr r3, [r3, #0] 800178c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001790: 2b00 cmp r3, #0 8001792: d0f0 beq.n 8001776 8001794: e054 b.n 8001840 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001796: 4b10 ldr r3, [pc, #64] ; (80017d8 ) 8001798: 2200 movs r2, #0 800179a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800179c: f7ff faf2 bl 8000d84 80017a0: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80017a2: e008 b.n 80017b6 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80017a4: f7ff faee bl 8000d84 80017a8: 4602 mov r2, r0 80017aa: 693b ldr r3, [r7, #16] 80017ac: 1ad3 subs r3, r2, r3 80017ae: 2b02 cmp r3, #2 80017b0: d901 bls.n 80017b6 { return HAL_TIMEOUT; 80017b2: 2303 movs r3, #3 80017b4: e045 b.n 8001842 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80017b6: 4b06 ldr r3, [pc, #24] ; (80017d0 ) 80017b8: 681b ldr r3, [r3, #0] 80017ba: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80017be: 2b00 cmp r3, #0 80017c0: d1f0 bne.n 80017a4 80017c2: e03d b.n 8001840 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80017c4: 687b ldr r3, [r7, #4] 80017c6: 699b ldr r3, [r3, #24] 80017c8: 2b01 cmp r3, #1 80017ca: d107 bne.n 80017dc { return HAL_ERROR; 80017cc: 2301 movs r3, #1 80017ce: e038 b.n 8001842 80017d0: 40023800 .word 0x40023800 80017d4: 40007000 .word 0x40007000 80017d8: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 80017dc: 4b1b ldr r3, [pc, #108] ; (800184c ) 80017de: 685b ldr r3, [r3, #4] 80017e0: 60fb str r3, [r7, #12] (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) #else if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80017e2: 687b ldr r3, [r7, #4] 80017e4: 699b ldr r3, [r3, #24] 80017e6: 2b01 cmp r3, #1 80017e8: d028 beq.n 800183c (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80017ea: 68fb ldr r3, [r7, #12] 80017ec: f403 0280 and.w r2, r3, #4194304 ; 0x400000 80017f0: 687b ldr r3, [r7, #4] 80017f2: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80017f4: 429a cmp r2, r3 80017f6: d121 bne.n 800183c (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80017f8: 68fb ldr r3, [r7, #12] 80017fa: f003 023f and.w r2, r3, #63 ; 0x3f 80017fe: 687b ldr r3, [r7, #4] 8001800: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001802: 429a cmp r2, r3 8001804: d11a bne.n 800183c (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8001806: 68fa ldr r2, [r7, #12] 8001808: f647 73c0 movw r3, #32704 ; 0x7fc0 800180c: 4013 ands r3, r2 800180e: 687a ldr r2, [r7, #4] 8001810: 6a52 ldr r2, [r2, #36] ; 0x24 8001812: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 8001814: 4293 cmp r3, r2 8001816: d111 bne.n 800183c (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8001818: 68fb ldr r3, [r7, #12] 800181a: f403 3240 and.w r2, r3, #196608 ; 0x30000 800181e: 687b ldr r3, [r7, #4] 8001820: 6a9b ldr r3, [r3, #40] ; 0x28 8001822: 085b lsrs r3, r3, #1 8001824: 3b01 subs r3, #1 8001826: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8001828: 429a cmp r2, r3 800182a: d107 bne.n 800183c (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) 800182c: 68fb ldr r3, [r7, #12] 800182e: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 8001832: 687b ldr r3, [r7, #4] 8001834: 6adb ldr r3, [r3, #44] ; 0x2c 8001836: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8001838: 429a cmp r2, r3 800183a: d001 beq.n 8001840 #endif { return HAL_ERROR; 800183c: 2301 movs r3, #1 800183e: e000 b.n 8001842 } } } } return HAL_OK; 8001840: 2300 movs r3, #0 } 8001842: 4618 mov r0, r3 8001844: 3718 adds r7, #24 8001846: 46bd mov sp, r7 8001848: bd80 pop {r7, pc} 800184a: bf00 nop 800184c: 40023800 .word 0x40023800 08001850 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8001850: b580 push {r7, lr} 8001852: b084 sub sp, #16 8001854: af00 add r7, sp, #0 8001856: 6078 str r0, [r7, #4] 8001858: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 800185a: 687b ldr r3, [r7, #4] 800185c: 2b00 cmp r3, #0 800185e: d101 bne.n 8001864 { return HAL_ERROR; 8001860: 2301 movs r3, #1 8001862: e0cc b.n 80019fe /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8001864: 4b68 ldr r3, [pc, #416] ; (8001a08 ) 8001866: 681b ldr r3, [r3, #0] 8001868: f003 0307 and.w r3, r3, #7 800186c: 683a ldr r2, [r7, #0] 800186e: 429a cmp r2, r3 8001870: d90c bls.n 800188c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001872: 4b65 ldr r3, [pc, #404] ; (8001a08 ) 8001874: 683a ldr r2, [r7, #0] 8001876: b2d2 uxtb r2, r2 8001878: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 800187a: 4b63 ldr r3, [pc, #396] ; (8001a08 ) 800187c: 681b ldr r3, [r3, #0] 800187e: f003 0307 and.w r3, r3, #7 8001882: 683a ldr r2, [r7, #0] 8001884: 429a cmp r2, r3 8001886: d001 beq.n 800188c { return HAL_ERROR; 8001888: 2301 movs r3, #1 800188a: e0b8 b.n 80019fe } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800188c: 687b ldr r3, [r7, #4] 800188e: 681b ldr r3, [r3, #0] 8001890: f003 0302 and.w r3, r3, #2 8001894: 2b00 cmp r3, #0 8001896: d020 beq.n 80018da { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001898: 687b ldr r3, [r7, #4] 800189a: 681b ldr r3, [r3, #0] 800189c: f003 0304 and.w r3, r3, #4 80018a0: 2b00 cmp r3, #0 80018a2: d005 beq.n 80018b0 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 80018a4: 4b59 ldr r3, [pc, #356] ; (8001a0c ) 80018a6: 689b ldr r3, [r3, #8] 80018a8: 4a58 ldr r2, [pc, #352] ; (8001a0c ) 80018aa: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 80018ae: 6093 str r3, [r2, #8] } if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80018b0: 687b ldr r3, [r7, #4] 80018b2: 681b ldr r3, [r3, #0] 80018b4: f003 0308 and.w r3, r3, #8 80018b8: 2b00 cmp r3, #0 80018ba: d005 beq.n 80018c8 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 80018bc: 4b53 ldr r3, [pc, #332] ; (8001a0c ) 80018be: 689b ldr r3, [r3, #8] 80018c0: 4a52 ldr r2, [pc, #328] ; (8001a0c ) 80018c2: f443 4360 orr.w r3, r3, #57344 ; 0xe000 80018c6: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80018c8: 4b50 ldr r3, [pc, #320] ; (8001a0c ) 80018ca: 689b ldr r3, [r3, #8] 80018cc: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80018d0: 687b ldr r3, [r7, #4] 80018d2: 689b ldr r3, [r3, #8] 80018d4: 494d ldr r1, [pc, #308] ; (8001a0c ) 80018d6: 4313 orrs r3, r2 80018d8: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80018da: 687b ldr r3, [r7, #4] 80018dc: 681b ldr r3, [r3, #0] 80018de: f003 0301 and.w r3, r3, #1 80018e2: 2b00 cmp r3, #0 80018e4: d044 beq.n 8001970 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80018e6: 687b ldr r3, [r7, #4] 80018e8: 685b ldr r3, [r3, #4] 80018ea: 2b01 cmp r3, #1 80018ec: d107 bne.n 80018fe { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80018ee: 4b47 ldr r3, [pc, #284] ; (8001a0c ) 80018f0: 681b ldr r3, [r3, #0] 80018f2: f403 3300 and.w r3, r3, #131072 ; 0x20000 80018f6: 2b00 cmp r3, #0 80018f8: d119 bne.n 800192e { return HAL_ERROR; 80018fa: 2301 movs r3, #1 80018fc: e07f b.n 80019fe } } /* PLL is selected as System Clock Source */ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 80018fe: 687b ldr r3, [r7, #4] 8001900: 685b ldr r3, [r3, #4] 8001902: 2b02 cmp r3, #2 8001904: d003 beq.n 800190e (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 8001906: 687b ldr r3, [r7, #4] 8001908: 685b ldr r3, [r3, #4] else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 800190a: 2b03 cmp r3, #3 800190c: d107 bne.n 800191e { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800190e: 4b3f ldr r3, [pc, #252] ; (8001a0c ) 8001910: 681b ldr r3, [r3, #0] 8001912: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001916: 2b00 cmp r3, #0 8001918: d109 bne.n 800192e { return HAL_ERROR; 800191a: 2301 movs r3, #1 800191c: e06f b.n 80019fe } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800191e: 4b3b ldr r3, [pc, #236] ; (8001a0c ) 8001920: 681b ldr r3, [r3, #0] 8001922: f003 0302 and.w r3, r3, #2 8001926: 2b00 cmp r3, #0 8001928: d101 bne.n 800192e { return HAL_ERROR; 800192a: 2301 movs r3, #1 800192c: e067 b.n 80019fe } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800192e: 4b37 ldr r3, [pc, #220] ; (8001a0c ) 8001930: 689b ldr r3, [r3, #8] 8001932: f023 0203 bic.w r2, r3, #3 8001936: 687b ldr r3, [r7, #4] 8001938: 685b ldr r3, [r3, #4] 800193a: 4934 ldr r1, [pc, #208] ; (8001a0c ) 800193c: 4313 orrs r3, r2 800193e: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001940: f7ff fa20 bl 8000d84 8001944: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8001946: e00a b.n 800195e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8001948: f7ff fa1c bl 8000d84 800194c: 4602 mov r2, r0 800194e: 68fb ldr r3, [r7, #12] 8001950: 1ad3 subs r3, r2, r3 8001952: f241 3288 movw r2, #5000 ; 0x1388 8001956: 4293 cmp r3, r2 8001958: d901 bls.n 800195e { return HAL_TIMEOUT; 800195a: 2303 movs r3, #3 800195c: e04f b.n 80019fe while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800195e: 4b2b ldr r3, [pc, #172] ; (8001a0c ) 8001960: 689b ldr r3, [r3, #8] 8001962: f003 020c and.w r2, r3, #12 8001966: 687b ldr r3, [r7, #4] 8001968: 685b ldr r3, [r3, #4] 800196a: 009b lsls r3, r3, #2 800196c: 429a cmp r2, r3 800196e: d1eb bne.n 8001948 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8001970: 4b25 ldr r3, [pc, #148] ; (8001a08 ) 8001972: 681b ldr r3, [r3, #0] 8001974: f003 0307 and.w r3, r3, #7 8001978: 683a ldr r2, [r7, #0] 800197a: 429a cmp r2, r3 800197c: d20c bcs.n 8001998 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800197e: 4b22 ldr r3, [pc, #136] ; (8001a08 ) 8001980: 683a ldr r2, [r7, #0] 8001982: b2d2 uxtb r2, r2 8001984: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001986: 4b20 ldr r3, [pc, #128] ; (8001a08 ) 8001988: 681b ldr r3, [r3, #0] 800198a: f003 0307 and.w r3, r3, #7 800198e: 683a ldr r2, [r7, #0] 8001990: 429a cmp r2, r3 8001992: d001 beq.n 8001998 { return HAL_ERROR; 8001994: 2301 movs r3, #1 8001996: e032 b.n 80019fe } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001998: 687b ldr r3, [r7, #4] 800199a: 681b ldr r3, [r3, #0] 800199c: f003 0304 and.w r3, r3, #4 80019a0: 2b00 cmp r3, #0 80019a2: d008 beq.n 80019b6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80019a4: 4b19 ldr r3, [pc, #100] ; (8001a0c ) 80019a6: 689b ldr r3, [r3, #8] 80019a8: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 80019ac: 687b ldr r3, [r7, #4] 80019ae: 68db ldr r3, [r3, #12] 80019b0: 4916 ldr r1, [pc, #88] ; (8001a0c ) 80019b2: 4313 orrs r3, r2 80019b4: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80019b6: 687b ldr r3, [r7, #4] 80019b8: 681b ldr r3, [r3, #0] 80019ba: f003 0308 and.w r3, r3, #8 80019be: 2b00 cmp r3, #0 80019c0: d009 beq.n 80019d6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 80019c2: 4b12 ldr r3, [pc, #72] ; (8001a0c ) 80019c4: 689b ldr r3, [r3, #8] 80019c6: f423 4260 bic.w r2, r3, #57344 ; 0xe000 80019ca: 687b ldr r3, [r7, #4] 80019cc: 691b ldr r3, [r3, #16] 80019ce: 00db lsls r3, r3, #3 80019d0: 490e ldr r1, [pc, #56] ; (8001a0c ) 80019d2: 4313 orrs r3, r2 80019d4: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; 80019d6: f000 f821 bl 8001a1c 80019da: 4602 mov r2, r0 80019dc: 4b0b ldr r3, [pc, #44] ; (8001a0c ) 80019de: 689b ldr r3, [r3, #8] 80019e0: 091b lsrs r3, r3, #4 80019e2: f003 030f and.w r3, r3, #15 80019e6: 490a ldr r1, [pc, #40] ; (8001a10 ) 80019e8: 5ccb ldrb r3, [r1, r3] 80019ea: fa22 f303 lsr.w r3, r2, r3 80019ee: 4a09 ldr r2, [pc, #36] ; (8001a14 ) 80019f0: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick (uwTickPrio); 80019f2: 4b09 ldr r3, [pc, #36] ; (8001a18 ) 80019f4: 681b ldr r3, [r3, #0] 80019f6: 4618 mov r0, r3 80019f8: f7ff f980 bl 8000cfc return HAL_OK; 80019fc: 2300 movs r3, #0 } 80019fe: 4618 mov r0, r3 8001a00: 3710 adds r7, #16 8001a02: 46bd mov sp, r7 8001a04: bd80 pop {r7, pc} 8001a06: bf00 nop 8001a08: 40023c00 .word 0x40023c00 8001a0c: 40023800 .word 0x40023800 8001a10: 08002f90 .word 0x08002f90 8001a14: 20000004 .word 0x20000004 8001a18: 20000008 .word 0x20000008 08001a1c : * * * @retval SYSCLK frequency */ __weak uint32_t HAL_RCC_GetSysClockFreq(void) { 8001a1c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8001a20: b090 sub sp, #64 ; 0x40 8001a22: af00 add r7, sp, #0 uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; 8001a24: 2300 movs r3, #0 8001a26: 637b str r3, [r7, #52] ; 0x34 8001a28: 2300 movs r3, #0 8001a2a: 63fb str r3, [r7, #60] ; 0x3c 8001a2c: 2300 movs r3, #0 8001a2e: 633b str r3, [r7, #48] ; 0x30 uint32_t sysclockfreq = 0U; 8001a30: 2300 movs r3, #0 8001a32: 63bb str r3, [r7, #56] ; 0x38 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8001a34: 4b59 ldr r3, [pc, #356] ; (8001b9c ) 8001a36: 689b ldr r3, [r3, #8] 8001a38: f003 030c and.w r3, r3, #12 8001a3c: 2b08 cmp r3, #8 8001a3e: d00d beq.n 8001a5c 8001a40: 2b08 cmp r3, #8 8001a42: f200 80a1 bhi.w 8001b88 8001a46: 2b00 cmp r3, #0 8001a48: d002 beq.n 8001a50 8001a4a: 2b04 cmp r3, #4 8001a4c: d003 beq.n 8001a56 8001a4e: e09b b.n 8001b88 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8001a50: 4b53 ldr r3, [pc, #332] ; (8001ba0 ) 8001a52: 63bb str r3, [r7, #56] ; 0x38 break; 8001a54: e09b b.n 8001b8e } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8001a56: 4b53 ldr r3, [pc, #332] ; (8001ba4 ) 8001a58: 63bb str r3, [r7, #56] ; 0x38 break; 8001a5a: e098 b.n 8001b8e } case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8001a5c: 4b4f ldr r3, [pc, #316] ; (8001b9c ) 8001a5e: 685b ldr r3, [r3, #4] 8001a60: f003 033f and.w r3, r3, #63 ; 0x3f 8001a64: 637b str r3, [r7, #52] ; 0x34 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8001a66: 4b4d ldr r3, [pc, #308] ; (8001b9c ) 8001a68: 685b ldr r3, [r3, #4] 8001a6a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8001a6e: 2b00 cmp r3, #0 8001a70: d028 beq.n 8001ac4 { /* HSE used as PLL clock source */ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8001a72: 4b4a ldr r3, [pc, #296] ; (8001b9c ) 8001a74: 685b ldr r3, [r3, #4] 8001a76: 099b lsrs r3, r3, #6 8001a78: 2200 movs r2, #0 8001a7a: 623b str r3, [r7, #32] 8001a7c: 627a str r2, [r7, #36] ; 0x24 8001a7e: 6a3b ldr r3, [r7, #32] 8001a80: f3c3 0008 ubfx r0, r3, #0, #9 8001a84: 2100 movs r1, #0 8001a86: 4b47 ldr r3, [pc, #284] ; (8001ba4 ) 8001a88: fb03 f201 mul.w r2, r3, r1 8001a8c: 2300 movs r3, #0 8001a8e: fb00 f303 mul.w r3, r0, r3 8001a92: 4413 add r3, r2 8001a94: 4a43 ldr r2, [pc, #268] ; (8001ba4 ) 8001a96: fba0 1202 umull r1, r2, r0, r2 8001a9a: 62fa str r2, [r7, #44] ; 0x2c 8001a9c: 460a mov r2, r1 8001a9e: 62ba str r2, [r7, #40] ; 0x28 8001aa0: 6afa ldr r2, [r7, #44] ; 0x2c 8001aa2: 4413 add r3, r2 8001aa4: 62fb str r3, [r7, #44] ; 0x2c 8001aa6: 6b7b ldr r3, [r7, #52] ; 0x34 8001aa8: 2200 movs r2, #0 8001aaa: 61bb str r3, [r7, #24] 8001aac: 61fa str r2, [r7, #28] 8001aae: e9d7 2306 ldrd r2, r3, [r7, #24] 8001ab2: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28 8001ab6: f7fe fb87 bl 80001c8 <__aeabi_uldivmod> 8001aba: 4602 mov r2, r0 8001abc: 460b mov r3, r1 8001abe: 4613 mov r3, r2 8001ac0: 63fb str r3, [r7, #60] ; 0x3c 8001ac2: e053 b.n 8001b6c } else { /* HSI used as PLL clock source */ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8001ac4: 4b35 ldr r3, [pc, #212] ; (8001b9c ) 8001ac6: 685b ldr r3, [r3, #4] 8001ac8: 099b lsrs r3, r3, #6 8001aca: 2200 movs r2, #0 8001acc: 613b str r3, [r7, #16] 8001ace: 617a str r2, [r7, #20] 8001ad0: 693b ldr r3, [r7, #16] 8001ad2: f3c3 0a08 ubfx sl, r3, #0, #9 8001ad6: f04f 0b00 mov.w fp, #0 8001ada: 4652 mov r2, sl 8001adc: 465b mov r3, fp 8001ade: f04f 0000 mov.w r0, #0 8001ae2: f04f 0100 mov.w r1, #0 8001ae6: 0159 lsls r1, r3, #5 8001ae8: ea41 61d2 orr.w r1, r1, r2, lsr #27 8001aec: 0150 lsls r0, r2, #5 8001aee: 4602 mov r2, r0 8001af0: 460b mov r3, r1 8001af2: ebb2 080a subs.w r8, r2, sl 8001af6: eb63 090b sbc.w r9, r3, fp 8001afa: f04f 0200 mov.w r2, #0 8001afe: f04f 0300 mov.w r3, #0 8001b02: ea4f 1389 mov.w r3, r9, lsl #6 8001b06: ea43 6398 orr.w r3, r3, r8, lsr #26 8001b0a: ea4f 1288 mov.w r2, r8, lsl #6 8001b0e: ebb2 0408 subs.w r4, r2, r8 8001b12: eb63 0509 sbc.w r5, r3, r9 8001b16: f04f 0200 mov.w r2, #0 8001b1a: f04f 0300 mov.w r3, #0 8001b1e: 00eb lsls r3, r5, #3 8001b20: ea43 7354 orr.w r3, r3, r4, lsr #29 8001b24: 00e2 lsls r2, r4, #3 8001b26: 4614 mov r4, r2 8001b28: 461d mov r5, r3 8001b2a: eb14 030a adds.w r3, r4, sl 8001b2e: 603b str r3, [r7, #0] 8001b30: eb45 030b adc.w r3, r5, fp 8001b34: 607b str r3, [r7, #4] 8001b36: f04f 0200 mov.w r2, #0 8001b3a: f04f 0300 mov.w r3, #0 8001b3e: e9d7 4500 ldrd r4, r5, [r7] 8001b42: 4629 mov r1, r5 8001b44: 028b lsls r3, r1, #10 8001b46: 4621 mov r1, r4 8001b48: ea43 5391 orr.w r3, r3, r1, lsr #22 8001b4c: 4621 mov r1, r4 8001b4e: 028a lsls r2, r1, #10 8001b50: 4610 mov r0, r2 8001b52: 4619 mov r1, r3 8001b54: 6b7b ldr r3, [r7, #52] ; 0x34 8001b56: 2200 movs r2, #0 8001b58: 60bb str r3, [r7, #8] 8001b5a: 60fa str r2, [r7, #12] 8001b5c: e9d7 2302 ldrd r2, r3, [r7, #8] 8001b60: f7fe fb32 bl 80001c8 <__aeabi_uldivmod> 8001b64: 4602 mov r2, r0 8001b66: 460b mov r3, r1 8001b68: 4613 mov r3, r2 8001b6a: 63fb str r3, [r7, #60] ; 0x3c } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); 8001b6c: 4b0b ldr r3, [pc, #44] ; (8001b9c ) 8001b6e: 685b ldr r3, [r3, #4] 8001b70: 0c1b lsrs r3, r3, #16 8001b72: f003 0303 and.w r3, r3, #3 8001b76: 3301 adds r3, #1 8001b78: 005b lsls r3, r3, #1 8001b7a: 633b str r3, [r7, #48] ; 0x30 sysclockfreq = pllvco/pllp; 8001b7c: 6bfa ldr r2, [r7, #60] ; 0x3c 8001b7e: 6b3b ldr r3, [r7, #48] ; 0x30 8001b80: fbb2 f3f3 udiv r3, r2, r3 8001b84: 63bb str r3, [r7, #56] ; 0x38 break; 8001b86: e002 b.n 8001b8e } default: { sysclockfreq = HSI_VALUE; 8001b88: 4b05 ldr r3, [pc, #20] ; (8001ba0 ) 8001b8a: 63bb str r3, [r7, #56] ; 0x38 break; 8001b8c: bf00 nop } } return sysclockfreq; 8001b8e: 6bbb ldr r3, [r7, #56] ; 0x38 } 8001b90: 4618 mov r0, r3 8001b92: 3740 adds r7, #64 ; 0x40 8001b94: 46bd mov sp, r7 8001b96: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8001b9a: bf00 nop 8001b9c: 40023800 .word 0x40023800 8001ba0: 00f42400 .word 0x00f42400 8001ba4: 016e3600 .word 0x016e3600 08001ba8 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8001ba8: b580 push {r7, lr} 8001baa: b082 sub sp, #8 8001bac: af00 add r7, sp, #0 8001bae: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8001bb0: 687b ldr r3, [r7, #4] 8001bb2: 2b00 cmp r3, #0 8001bb4: d101 bne.n 8001bba { return HAL_ERROR; 8001bb6: 2301 movs r3, #1 8001bb8: e041 b.n 8001c3e assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8001bba: 687b ldr r3, [r7, #4] 8001bbc: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001bc0: b2db uxtb r3, r3 8001bc2: 2b00 cmp r3, #0 8001bc4: d106 bne.n 8001bd4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8001bc6: 687b ldr r3, [r7, #4] 8001bc8: 2200 movs r2, #0 8001bca: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8001bce: 6878 ldr r0, [r7, #4] 8001bd0: f7fe ff26 bl 8000a20 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8001bd4: 687b ldr r3, [r7, #4] 8001bd6: 2202 movs r2, #2 8001bd8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8001bdc: 687b ldr r3, [r7, #4] 8001bde: 681a ldr r2, [r3, #0] 8001be0: 687b ldr r3, [r7, #4] 8001be2: 3304 adds r3, #4 8001be4: 4619 mov r1, r3 8001be6: 4610 mov r0, r2 8001be8: f000 fda8 bl 800273c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8001bec: 687b ldr r3, [r7, #4] 8001bee: 2201 movs r2, #1 8001bf0: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8001bf4: 687b ldr r3, [r7, #4] 8001bf6: 2201 movs r2, #1 8001bf8: f883 203e strb.w r2, [r3, #62] ; 0x3e 8001bfc: 687b ldr r3, [r7, #4] 8001bfe: 2201 movs r2, #1 8001c00: f883 203f strb.w r2, [r3, #63] ; 0x3f 8001c04: 687b ldr r3, [r7, #4] 8001c06: 2201 movs r2, #1 8001c08: f883 2040 strb.w r2, [r3, #64] ; 0x40 8001c0c: 687b ldr r3, [r7, #4] 8001c0e: 2201 movs r2, #1 8001c10: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8001c14: 687b ldr r3, [r7, #4] 8001c16: 2201 movs r2, #1 8001c18: f883 2042 strb.w r2, [r3, #66] ; 0x42 8001c1c: 687b ldr r3, [r7, #4] 8001c1e: 2201 movs r2, #1 8001c20: f883 2043 strb.w r2, [r3, #67] ; 0x43 8001c24: 687b ldr r3, [r7, #4] 8001c26: 2201 movs r2, #1 8001c28: f883 2044 strb.w r2, [r3, #68] ; 0x44 8001c2c: 687b ldr r3, [r7, #4] 8001c2e: 2201 movs r2, #1 8001c30: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8001c34: 687b ldr r3, [r7, #4] 8001c36: 2201 movs r2, #1 8001c38: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8001c3c: 2300 movs r3, #0 } 8001c3e: 4618 mov r0, r3 8001c40: 3708 adds r7, #8 8001c42: 46bd mov sp, r7 8001c44: bd80 pop {r7, pc} ... 08001c48 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8001c48: b480 push {r7} 8001c4a: b085 sub sp, #20 8001c4c: af00 add r7, sp, #0 8001c4e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 8001c50: 687b ldr r3, [r7, #4] 8001c52: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001c56: b2db uxtb r3, r3 8001c58: 2b01 cmp r3, #1 8001c5a: d001 beq.n 8001c60 { return HAL_ERROR; 8001c5c: 2301 movs r3, #1 8001c5e: e04e b.n 8001cfe } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8001c60: 687b ldr r3, [r7, #4] 8001c62: 2202 movs r2, #2 8001c64: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8001c68: 687b ldr r3, [r7, #4] 8001c6a: 681b ldr r3, [r3, #0] 8001c6c: 68da ldr r2, [r3, #12] 8001c6e: 687b ldr r3, [r7, #4] 8001c70: 681b ldr r3, [r3, #0] 8001c72: f042 0201 orr.w r2, r2, #1 8001c76: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8001c78: 687b ldr r3, [r7, #4] 8001c7a: 681b ldr r3, [r3, #0] 8001c7c: 4a23 ldr r2, [pc, #140] ; (8001d0c ) 8001c7e: 4293 cmp r3, r2 8001c80: d022 beq.n 8001cc8 8001c82: 687b ldr r3, [r7, #4] 8001c84: 681b ldr r3, [r3, #0] 8001c86: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8001c8a: d01d beq.n 8001cc8 8001c8c: 687b ldr r3, [r7, #4] 8001c8e: 681b ldr r3, [r3, #0] 8001c90: 4a1f ldr r2, [pc, #124] ; (8001d10 ) 8001c92: 4293 cmp r3, r2 8001c94: d018 beq.n 8001cc8 8001c96: 687b ldr r3, [r7, #4] 8001c98: 681b ldr r3, [r3, #0] 8001c9a: 4a1e ldr r2, [pc, #120] ; (8001d14 ) 8001c9c: 4293 cmp r3, r2 8001c9e: d013 beq.n 8001cc8 8001ca0: 687b ldr r3, [r7, #4] 8001ca2: 681b ldr r3, [r3, #0] 8001ca4: 4a1c ldr r2, [pc, #112] ; (8001d18 ) 8001ca6: 4293 cmp r3, r2 8001ca8: d00e beq.n 8001cc8 8001caa: 687b ldr r3, [r7, #4] 8001cac: 681b ldr r3, [r3, #0] 8001cae: 4a1b ldr r2, [pc, #108] ; (8001d1c ) 8001cb0: 4293 cmp r3, r2 8001cb2: d009 beq.n 8001cc8 8001cb4: 687b ldr r3, [r7, #4] 8001cb6: 681b ldr r3, [r3, #0] 8001cb8: 4a19 ldr r2, [pc, #100] ; (8001d20 ) 8001cba: 4293 cmp r3, r2 8001cbc: d004 beq.n 8001cc8 8001cbe: 687b ldr r3, [r7, #4] 8001cc0: 681b ldr r3, [r3, #0] 8001cc2: 4a18 ldr r2, [pc, #96] ; (8001d24 ) 8001cc4: 4293 cmp r3, r2 8001cc6: d111 bne.n 8001cec { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8001cc8: 687b ldr r3, [r7, #4] 8001cca: 681b ldr r3, [r3, #0] 8001ccc: 689b ldr r3, [r3, #8] 8001cce: f003 0307 and.w r3, r3, #7 8001cd2: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8001cd4: 68fb ldr r3, [r7, #12] 8001cd6: 2b06 cmp r3, #6 8001cd8: d010 beq.n 8001cfc { __HAL_TIM_ENABLE(htim); 8001cda: 687b ldr r3, [r7, #4] 8001cdc: 681b ldr r3, [r3, #0] 8001cde: 681a ldr r2, [r3, #0] 8001ce0: 687b ldr r3, [r7, #4] 8001ce2: 681b ldr r3, [r3, #0] 8001ce4: f042 0201 orr.w r2, r2, #1 8001ce8: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8001cea: e007 b.n 8001cfc } } else { __HAL_TIM_ENABLE(htim); 8001cec: 687b ldr r3, [r7, #4] 8001cee: 681b ldr r3, [r3, #0] 8001cf0: 681a ldr r2, [r3, #0] 8001cf2: 687b ldr r3, [r7, #4] 8001cf4: 681b ldr r3, [r3, #0] 8001cf6: f042 0201 orr.w r2, r2, #1 8001cfa: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8001cfc: 2300 movs r3, #0 } 8001cfe: 4618 mov r0, r3 8001d00: 3714 adds r7, #20 8001d02: 46bd mov sp, r7 8001d04: f85d 7b04 ldr.w r7, [sp], #4 8001d08: 4770 bx lr 8001d0a: bf00 nop 8001d0c: 40010000 .word 0x40010000 8001d10: 40000400 .word 0x40000400 8001d14: 40000800 .word 0x40000800 8001d18: 40000c00 .word 0x40000c00 8001d1c: 40010400 .word 0x40010400 8001d20: 40014000 .word 0x40014000 8001d24: 40001800 .word 0x40001800 08001d28 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8001d28: b580 push {r7, lr} 8001d2a: b082 sub sp, #8 8001d2c: af00 add r7, sp, #0 8001d2e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8001d30: 687b ldr r3, [r7, #4] 8001d32: 2b00 cmp r3, #0 8001d34: d101 bne.n 8001d3a { return HAL_ERROR; 8001d36: 2301 movs r3, #1 8001d38: e041 b.n 8001dbe assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8001d3a: 687b ldr r3, [r7, #4] 8001d3c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001d40: b2db uxtb r3, r3 8001d42: 2b00 cmp r3, #0 8001d44: d106 bne.n 8001d54 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8001d46: 687b ldr r3, [r7, #4] 8001d48: 2200 movs r2, #0 8001d4a: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 8001d4e: 6878 ldr r0, [r7, #4] 8001d50: f000 f839 bl 8001dc6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8001d54: 687b ldr r3, [r7, #4] 8001d56: 2202 movs r2, #2 8001d58: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8001d5c: 687b ldr r3, [r7, #4] 8001d5e: 681a ldr r2, [r3, #0] 8001d60: 687b ldr r3, [r7, #4] 8001d62: 3304 adds r3, #4 8001d64: 4619 mov r1, r3 8001d66: 4610 mov r0, r2 8001d68: f000 fce8 bl 800273c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8001d6c: 687b ldr r3, [r7, #4] 8001d6e: 2201 movs r2, #1 8001d70: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8001d74: 687b ldr r3, [r7, #4] 8001d76: 2201 movs r2, #1 8001d78: f883 203e strb.w r2, [r3, #62] ; 0x3e 8001d7c: 687b ldr r3, [r7, #4] 8001d7e: 2201 movs r2, #1 8001d80: f883 203f strb.w r2, [r3, #63] ; 0x3f 8001d84: 687b ldr r3, [r7, #4] 8001d86: 2201 movs r2, #1 8001d88: f883 2040 strb.w r2, [r3, #64] ; 0x40 8001d8c: 687b ldr r3, [r7, #4] 8001d8e: 2201 movs r2, #1 8001d90: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8001d94: 687b ldr r3, [r7, #4] 8001d96: 2201 movs r2, #1 8001d98: f883 2042 strb.w r2, [r3, #66] ; 0x42 8001d9c: 687b ldr r3, [r7, #4] 8001d9e: 2201 movs r2, #1 8001da0: f883 2043 strb.w r2, [r3, #67] ; 0x43 8001da4: 687b ldr r3, [r7, #4] 8001da6: 2201 movs r2, #1 8001da8: f883 2044 strb.w r2, [r3, #68] ; 0x44 8001dac: 687b ldr r3, [r7, #4] 8001dae: 2201 movs r2, #1 8001db0: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8001db4: 687b ldr r3, [r7, #4] 8001db6: 2201 movs r2, #1 8001db8: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8001dbc: 2300 movs r3, #0 } 8001dbe: 4618 mov r0, r3 8001dc0: 3708 adds r7, #8 8001dc2: 46bd mov sp, r7 8001dc4: bd80 pop {r7, pc} 08001dc6 : * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { 8001dc6: b480 push {r7} 8001dc8: b083 sub sp, #12 8001dca: af00 add r7, sp, #0 8001dcc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } 8001dce: bf00 nop 8001dd0: 370c adds r7, #12 8001dd2: 46bd mov sp, r7 8001dd4: f85d 7b04 ldr.w r7, [sp], #4 8001dd8: 4770 bx lr 08001dda : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8001dda: b580 push {r7, lr} 8001ddc: b082 sub sp, #8 8001dde: af00 add r7, sp, #0 8001de0: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8001de2: 687b ldr r3, [r7, #4] 8001de4: 2b00 cmp r3, #0 8001de6: d101 bne.n 8001dec { return HAL_ERROR; 8001de8: 2301 movs r3, #1 8001dea: e041 b.n 8001e70 assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8001dec: 687b ldr r3, [r7, #4] 8001dee: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001df2: b2db uxtb r3, r3 8001df4: 2b00 cmp r3, #0 8001df6: d106 bne.n 8001e06 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8001df8: 687b ldr r3, [r7, #4] 8001dfa: 2200 movs r2, #0 8001dfc: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 8001e00: 6878 ldr r0, [r7, #4] 8001e02: f000 f839 bl 8001e78 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8001e06: 687b ldr r3, [r7, #4] 8001e08: 2202 movs r2, #2 8001e0a: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8001e0e: 687b ldr r3, [r7, #4] 8001e10: 681a ldr r2, [r3, #0] 8001e12: 687b ldr r3, [r7, #4] 8001e14: 3304 adds r3, #4 8001e16: 4619 mov r1, r3 8001e18: 4610 mov r0, r2 8001e1a: f000 fc8f bl 800273c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8001e1e: 687b ldr r3, [r7, #4] 8001e20: 2201 movs r2, #1 8001e22: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8001e26: 687b ldr r3, [r7, #4] 8001e28: 2201 movs r2, #1 8001e2a: f883 203e strb.w r2, [r3, #62] ; 0x3e 8001e2e: 687b ldr r3, [r7, #4] 8001e30: 2201 movs r2, #1 8001e32: f883 203f strb.w r2, [r3, #63] ; 0x3f 8001e36: 687b ldr r3, [r7, #4] 8001e38: 2201 movs r2, #1 8001e3a: f883 2040 strb.w r2, [r3, #64] ; 0x40 8001e3e: 687b ldr r3, [r7, #4] 8001e40: 2201 movs r2, #1 8001e42: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8001e46: 687b ldr r3, [r7, #4] 8001e48: 2201 movs r2, #1 8001e4a: f883 2042 strb.w r2, [r3, #66] ; 0x42 8001e4e: 687b ldr r3, [r7, #4] 8001e50: 2201 movs r2, #1 8001e52: f883 2043 strb.w r2, [r3, #67] ; 0x43 8001e56: 687b ldr r3, [r7, #4] 8001e58: 2201 movs r2, #1 8001e5a: f883 2044 strb.w r2, [r3, #68] ; 0x44 8001e5e: 687b ldr r3, [r7, #4] 8001e60: 2201 movs r2, #1 8001e62: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8001e66: 687b ldr r3, [r7, #4] 8001e68: 2201 movs r2, #1 8001e6a: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8001e6e: 2300 movs r3, #0 } 8001e70: 4618 mov r0, r3 8001e72: 3708 adds r7, #8 8001e74: 46bd mov sp, r7 8001e76: bd80 pop {r7, pc} 08001e78 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8001e78: b480 push {r7} 8001e7a: b083 sub sp, #12 8001e7c: af00 add r7, sp, #0 8001e7e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8001e80: bf00 nop 8001e82: 370c adds r7, #12 8001e84: 46bd mov sp, r7 8001e86: f85d 7b04 ldr.w r7, [sp], #4 8001e8a: 4770 bx lr 08001e8c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8001e8c: b580 push {r7, lr} 8001e8e: b084 sub sp, #16 8001e90: af00 add r7, sp, #0 8001e92: 6078 str r0, [r7, #4] 8001e94: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8001e96: 683b ldr r3, [r7, #0] 8001e98: 2b00 cmp r3, #0 8001e9a: d109 bne.n 8001eb0 8001e9c: 687b ldr r3, [r7, #4] 8001e9e: f893 303e ldrb.w r3, [r3, #62] ; 0x3e 8001ea2: b2db uxtb r3, r3 8001ea4: 2b01 cmp r3, #1 8001ea6: bf14 ite ne 8001ea8: 2301 movne r3, #1 8001eaa: 2300 moveq r3, #0 8001eac: b2db uxtb r3, r3 8001eae: e022 b.n 8001ef6 8001eb0: 683b ldr r3, [r7, #0] 8001eb2: 2b04 cmp r3, #4 8001eb4: d109 bne.n 8001eca 8001eb6: 687b ldr r3, [r7, #4] 8001eb8: f893 303f ldrb.w r3, [r3, #63] ; 0x3f 8001ebc: b2db uxtb r3, r3 8001ebe: 2b01 cmp r3, #1 8001ec0: bf14 ite ne 8001ec2: 2301 movne r3, #1 8001ec4: 2300 moveq r3, #0 8001ec6: b2db uxtb r3, r3 8001ec8: e015 b.n 8001ef6 8001eca: 683b ldr r3, [r7, #0] 8001ecc: 2b08 cmp r3, #8 8001ece: d109 bne.n 8001ee4 8001ed0: 687b ldr r3, [r7, #4] 8001ed2: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 8001ed6: b2db uxtb r3, r3 8001ed8: 2b01 cmp r3, #1 8001eda: bf14 ite ne 8001edc: 2301 movne r3, #1 8001ede: 2300 moveq r3, #0 8001ee0: b2db uxtb r3, r3 8001ee2: e008 b.n 8001ef6 8001ee4: 687b ldr r3, [r7, #4] 8001ee6: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 8001eea: b2db uxtb r3, r3 8001eec: 2b01 cmp r3, #1 8001eee: bf14 ite ne 8001ef0: 2301 movne r3, #1 8001ef2: 2300 moveq r3, #0 8001ef4: b2db uxtb r3, r3 8001ef6: 2b00 cmp r3, #0 8001ef8: d001 beq.n 8001efe { return HAL_ERROR; 8001efa: 2301 movs r3, #1 8001efc: e07c b.n 8001ff8 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8001efe: 683b ldr r3, [r7, #0] 8001f00: 2b00 cmp r3, #0 8001f02: d104 bne.n 8001f0e 8001f04: 687b ldr r3, [r7, #4] 8001f06: 2202 movs r2, #2 8001f08: f883 203e strb.w r2, [r3, #62] ; 0x3e 8001f0c: e013 b.n 8001f36 8001f0e: 683b ldr r3, [r7, #0] 8001f10: 2b04 cmp r3, #4 8001f12: d104 bne.n 8001f1e 8001f14: 687b ldr r3, [r7, #4] 8001f16: 2202 movs r2, #2 8001f18: f883 203f strb.w r2, [r3, #63] ; 0x3f 8001f1c: e00b b.n 8001f36 8001f1e: 683b ldr r3, [r7, #0] 8001f20: 2b08 cmp r3, #8 8001f22: d104 bne.n 8001f2e 8001f24: 687b ldr r3, [r7, #4] 8001f26: 2202 movs r2, #2 8001f28: f883 2040 strb.w r2, [r3, #64] ; 0x40 8001f2c: e003 b.n 8001f36 8001f2e: 687b ldr r3, [r7, #4] 8001f30: 2202 movs r2, #2 8001f32: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8001f36: 687b ldr r3, [r7, #4] 8001f38: 681b ldr r3, [r3, #0] 8001f3a: 2201 movs r2, #1 8001f3c: 6839 ldr r1, [r7, #0] 8001f3e: 4618 mov r0, r3 8001f40: f000 fee6 bl 8002d10 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8001f44: 687b ldr r3, [r7, #4] 8001f46: 681b ldr r3, [r3, #0] 8001f48: 4a2d ldr r2, [pc, #180] ; (8002000 ) 8001f4a: 4293 cmp r3, r2 8001f4c: d004 beq.n 8001f58 8001f4e: 687b ldr r3, [r7, #4] 8001f50: 681b ldr r3, [r3, #0] 8001f52: 4a2c ldr r2, [pc, #176] ; (8002004 ) 8001f54: 4293 cmp r3, r2 8001f56: d101 bne.n 8001f5c 8001f58: 2301 movs r3, #1 8001f5a: e000 b.n 8001f5e 8001f5c: 2300 movs r3, #0 8001f5e: 2b00 cmp r3, #0 8001f60: d007 beq.n 8001f72 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8001f62: 687b ldr r3, [r7, #4] 8001f64: 681b ldr r3, [r3, #0] 8001f66: 6c5a ldr r2, [r3, #68] ; 0x44 8001f68: 687b ldr r3, [r7, #4] 8001f6a: 681b ldr r3, [r3, #0] 8001f6c: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8001f70: 645a str r2, [r3, #68] ; 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8001f72: 687b ldr r3, [r7, #4] 8001f74: 681b ldr r3, [r3, #0] 8001f76: 4a22 ldr r2, [pc, #136] ; (8002000 ) 8001f78: 4293 cmp r3, r2 8001f7a: d022 beq.n 8001fc2 8001f7c: 687b ldr r3, [r7, #4] 8001f7e: 681b ldr r3, [r3, #0] 8001f80: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8001f84: d01d beq.n 8001fc2 8001f86: 687b ldr r3, [r7, #4] 8001f88: 681b ldr r3, [r3, #0] 8001f8a: 4a1f ldr r2, [pc, #124] ; (8002008 ) 8001f8c: 4293 cmp r3, r2 8001f8e: d018 beq.n 8001fc2 8001f90: 687b ldr r3, [r7, #4] 8001f92: 681b ldr r3, [r3, #0] 8001f94: 4a1d ldr r2, [pc, #116] ; (800200c ) 8001f96: 4293 cmp r3, r2 8001f98: d013 beq.n 8001fc2 8001f9a: 687b ldr r3, [r7, #4] 8001f9c: 681b ldr r3, [r3, #0] 8001f9e: 4a1c ldr r2, [pc, #112] ; (8002010 ) 8001fa0: 4293 cmp r3, r2 8001fa2: d00e beq.n 8001fc2 8001fa4: 687b ldr r3, [r7, #4] 8001fa6: 681b ldr r3, [r3, #0] 8001fa8: 4a16 ldr r2, [pc, #88] ; (8002004 ) 8001faa: 4293 cmp r3, r2 8001fac: d009 beq.n 8001fc2 8001fae: 687b ldr r3, [r7, #4] 8001fb0: 681b ldr r3, [r3, #0] 8001fb2: 4a18 ldr r2, [pc, #96] ; (8002014 ) 8001fb4: 4293 cmp r3, r2 8001fb6: d004 beq.n 8001fc2 8001fb8: 687b ldr r3, [r7, #4] 8001fba: 681b ldr r3, [r3, #0] 8001fbc: 4a16 ldr r2, [pc, #88] ; (8002018 ) 8001fbe: 4293 cmp r3, r2 8001fc0: d111 bne.n 8001fe6 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8001fc2: 687b ldr r3, [r7, #4] 8001fc4: 681b ldr r3, [r3, #0] 8001fc6: 689b ldr r3, [r3, #8] 8001fc8: f003 0307 and.w r3, r3, #7 8001fcc: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8001fce: 68fb ldr r3, [r7, #12] 8001fd0: 2b06 cmp r3, #6 8001fd2: d010 beq.n 8001ff6 { __HAL_TIM_ENABLE(htim); 8001fd4: 687b ldr r3, [r7, #4] 8001fd6: 681b ldr r3, [r3, #0] 8001fd8: 681a ldr r2, [r3, #0] 8001fda: 687b ldr r3, [r7, #4] 8001fdc: 681b ldr r3, [r3, #0] 8001fde: f042 0201 orr.w r2, r2, #1 8001fe2: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8001fe4: e007 b.n 8001ff6 } } else { __HAL_TIM_ENABLE(htim); 8001fe6: 687b ldr r3, [r7, #4] 8001fe8: 681b ldr r3, [r3, #0] 8001fea: 681a ldr r2, [r3, #0] 8001fec: 687b ldr r3, [r7, #4] 8001fee: 681b ldr r3, [r3, #0] 8001ff0: f042 0201 orr.w r2, r2, #1 8001ff4: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8001ff6: 2300 movs r3, #0 } 8001ff8: 4618 mov r0, r3 8001ffa: 3710 adds r7, #16 8001ffc: 46bd mov sp, r7 8001ffe: bd80 pop {r7, pc} 8002000: 40010000 .word 0x40010000 8002004: 40010400 .word 0x40010400 8002008: 40000400 .word 0x40000400 800200c: 40000800 .word 0x40000800 8002010: 40000c00 .word 0x40000c00 8002014: 40014000 .word 0x40014000 8002018: 40001800 .word 0x40001800 0800201c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { 800201c: b580 push {r7, lr} 800201e: b082 sub sp, #8 8002020: af00 add r7, sp, #0 8002022: 6078 str r0, [r7, #4] 8002024: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 8002026: 687b ldr r3, [r7, #4] 8002028: 681b ldr r3, [r3, #0] 800202a: 2200 movs r2, #0 800202c: 6839 ldr r1, [r7, #0] 800202e: 4618 mov r0, r3 8002030: f000 fe6e bl 8002d10 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8002034: 687b ldr r3, [r7, #4] 8002036: 681b ldr r3, [r3, #0] 8002038: 4a2e ldr r2, [pc, #184] ; (80020f4 ) 800203a: 4293 cmp r3, r2 800203c: d004 beq.n 8002048 800203e: 687b ldr r3, [r7, #4] 8002040: 681b ldr r3, [r3, #0] 8002042: 4a2d ldr r2, [pc, #180] ; (80020f8 ) 8002044: 4293 cmp r3, r2 8002046: d101 bne.n 800204c 8002048: 2301 movs r3, #1 800204a: e000 b.n 800204e 800204c: 2300 movs r3, #0 800204e: 2b00 cmp r3, #0 8002050: d017 beq.n 8002082 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 8002052: 687b ldr r3, [r7, #4] 8002054: 681b ldr r3, [r3, #0] 8002056: 6a1a ldr r2, [r3, #32] 8002058: f241 1311 movw r3, #4369 ; 0x1111 800205c: 4013 ands r3, r2 800205e: 2b00 cmp r3, #0 8002060: d10f bne.n 8002082 8002062: 687b ldr r3, [r7, #4] 8002064: 681b ldr r3, [r3, #0] 8002066: 6a1a ldr r2, [r3, #32] 8002068: f240 4344 movw r3, #1092 ; 0x444 800206c: 4013 ands r3, r2 800206e: 2b00 cmp r3, #0 8002070: d107 bne.n 8002082 8002072: 687b ldr r3, [r7, #4] 8002074: 681b ldr r3, [r3, #0] 8002076: 6c5a ldr r2, [r3, #68] ; 0x44 8002078: 687b ldr r3, [r7, #4] 800207a: 681b ldr r3, [r3, #0] 800207c: f422 4200 bic.w r2, r2, #32768 ; 0x8000 8002080: 645a str r2, [r3, #68] ; 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 8002082: 687b ldr r3, [r7, #4] 8002084: 681b ldr r3, [r3, #0] 8002086: 6a1a ldr r2, [r3, #32] 8002088: f241 1311 movw r3, #4369 ; 0x1111 800208c: 4013 ands r3, r2 800208e: 2b00 cmp r3, #0 8002090: d10f bne.n 80020b2 8002092: 687b ldr r3, [r7, #4] 8002094: 681b ldr r3, [r3, #0] 8002096: 6a1a ldr r2, [r3, #32] 8002098: f240 4344 movw r3, #1092 ; 0x444 800209c: 4013 ands r3, r2 800209e: 2b00 cmp r3, #0 80020a0: d107 bne.n 80020b2 80020a2: 687b ldr r3, [r7, #4] 80020a4: 681b ldr r3, [r3, #0] 80020a6: 681a ldr r2, [r3, #0] 80020a8: 687b ldr r3, [r7, #4] 80020aa: 681b ldr r3, [r3, #0] 80020ac: f022 0201 bic.w r2, r2, #1 80020b0: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 80020b2: 683b ldr r3, [r7, #0] 80020b4: 2b00 cmp r3, #0 80020b6: d104 bne.n 80020c2 80020b8: 687b ldr r3, [r7, #4] 80020ba: 2201 movs r2, #1 80020bc: f883 203e strb.w r2, [r3, #62] ; 0x3e 80020c0: e013 b.n 80020ea 80020c2: 683b ldr r3, [r7, #0] 80020c4: 2b04 cmp r3, #4 80020c6: d104 bne.n 80020d2 80020c8: 687b ldr r3, [r7, #4] 80020ca: 2201 movs r2, #1 80020cc: f883 203f strb.w r2, [r3, #63] ; 0x3f 80020d0: e00b b.n 80020ea 80020d2: 683b ldr r3, [r7, #0] 80020d4: 2b08 cmp r3, #8 80020d6: d104 bne.n 80020e2 80020d8: 687b ldr r3, [r7, #4] 80020da: 2201 movs r2, #1 80020dc: f883 2040 strb.w r2, [r3, #64] ; 0x40 80020e0: e003 b.n 80020ea 80020e2: 687b ldr r3, [r7, #4] 80020e4: 2201 movs r2, #1 80020e6: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Return function status */ return HAL_OK; 80020ea: 2300 movs r3, #0 } 80020ec: 4618 mov r0, r3 80020ee: 3708 adds r7, #8 80020f0: 46bd mov sp, r7 80020f2: bd80 pop {r7, pc} 80020f4: 40010000 .word 0x40010000 80020f8: 40010400 .word 0x40010400 080020fc : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 80020fc: b580 push {r7, lr} 80020fe: b082 sub sp, #8 8002100: af00 add r7, sp, #0 8002102: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 8002104: 687b ldr r3, [r7, #4] 8002106: 681b ldr r3, [r3, #0] 8002108: 691b ldr r3, [r3, #16] 800210a: f003 0302 and.w r3, r3, #2 800210e: 2b02 cmp r3, #2 8002110: d122 bne.n 8002158 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 8002112: 687b ldr r3, [r7, #4] 8002114: 681b ldr r3, [r3, #0] 8002116: 68db ldr r3, [r3, #12] 8002118: f003 0302 and.w r3, r3, #2 800211c: 2b02 cmp r3, #2 800211e: d11b bne.n 8002158 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 8002120: 687b ldr r3, [r7, #4] 8002122: 681b ldr r3, [r3, #0] 8002124: f06f 0202 mvn.w r2, #2 8002128: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800212a: 687b ldr r3, [r7, #4] 800212c: 2201 movs r2, #1 800212e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8002130: 687b ldr r3, [r7, #4] 8002132: 681b ldr r3, [r3, #0] 8002134: 699b ldr r3, [r3, #24] 8002136: f003 0303 and.w r3, r3, #3 800213a: 2b00 cmp r3, #0 800213c: d003 beq.n 8002146 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800213e: 6878 ldr r0, [r7, #4] 8002140: f000 fadd bl 80026fe 8002144: e005 b.n 8002152 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002146: 6878 ldr r0, [r7, #4] 8002148: f000 facf bl 80026ea HAL_TIM_PWM_PulseFinishedCallback(htim); 800214c: 6878 ldr r0, [r7, #4] 800214e: f000 fae0 bl 8002712 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8002152: 687b ldr r3, [r7, #4] 8002154: 2200 movs r2, #0 8002156: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 8002158: 687b ldr r3, [r7, #4] 800215a: 681b ldr r3, [r3, #0] 800215c: 691b ldr r3, [r3, #16] 800215e: f003 0304 and.w r3, r3, #4 8002162: 2b04 cmp r3, #4 8002164: d122 bne.n 80021ac { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 8002166: 687b ldr r3, [r7, #4] 8002168: 681b ldr r3, [r3, #0] 800216a: 68db ldr r3, [r3, #12] 800216c: f003 0304 and.w r3, r3, #4 8002170: 2b04 cmp r3, #4 8002172: d11b bne.n 80021ac { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 8002174: 687b ldr r3, [r7, #4] 8002176: 681b ldr r3, [r3, #0] 8002178: f06f 0204 mvn.w r2, #4 800217c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800217e: 687b ldr r3, [r7, #4] 8002180: 2202 movs r2, #2 8002182: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8002184: 687b ldr r3, [r7, #4] 8002186: 681b ldr r3, [r3, #0] 8002188: 699b ldr r3, [r3, #24] 800218a: f403 7340 and.w r3, r3, #768 ; 0x300 800218e: 2b00 cmp r3, #0 8002190: d003 beq.n 800219a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8002192: 6878 ldr r0, [r7, #4] 8002194: f000 fab3 bl 80026fe 8002198: e005 b.n 80021a6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800219a: 6878 ldr r0, [r7, #4] 800219c: f000 faa5 bl 80026ea HAL_TIM_PWM_PulseFinishedCallback(htim); 80021a0: 6878 ldr r0, [r7, #4] 80021a2: f000 fab6 bl 8002712 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80021a6: 687b ldr r3, [r7, #4] 80021a8: 2200 movs r2, #0 80021aa: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 80021ac: 687b ldr r3, [r7, #4] 80021ae: 681b ldr r3, [r3, #0] 80021b0: 691b ldr r3, [r3, #16] 80021b2: f003 0308 and.w r3, r3, #8 80021b6: 2b08 cmp r3, #8 80021b8: d122 bne.n 8002200 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 80021ba: 687b ldr r3, [r7, #4] 80021bc: 681b ldr r3, [r3, #0] 80021be: 68db ldr r3, [r3, #12] 80021c0: f003 0308 and.w r3, r3, #8 80021c4: 2b08 cmp r3, #8 80021c6: d11b bne.n 8002200 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 80021c8: 687b ldr r3, [r7, #4] 80021ca: 681b ldr r3, [r3, #0] 80021cc: f06f 0208 mvn.w r2, #8 80021d0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 80021d2: 687b ldr r3, [r7, #4] 80021d4: 2204 movs r2, #4 80021d6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 80021d8: 687b ldr r3, [r7, #4] 80021da: 681b ldr r3, [r3, #0] 80021dc: 69db ldr r3, [r3, #28] 80021de: f003 0303 and.w r3, r3, #3 80021e2: 2b00 cmp r3, #0 80021e4: d003 beq.n 80021ee { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80021e6: 6878 ldr r0, [r7, #4] 80021e8: f000 fa89 bl 80026fe 80021ec: e005 b.n 80021fa { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80021ee: 6878 ldr r0, [r7, #4] 80021f0: f000 fa7b bl 80026ea HAL_TIM_PWM_PulseFinishedCallback(htim); 80021f4: 6878 ldr r0, [r7, #4] 80021f6: f000 fa8c bl 8002712 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80021fa: 687b ldr r3, [r7, #4] 80021fc: 2200 movs r2, #0 80021fe: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 8002200: 687b ldr r3, [r7, #4] 8002202: 681b ldr r3, [r3, #0] 8002204: 691b ldr r3, [r3, #16] 8002206: f003 0310 and.w r3, r3, #16 800220a: 2b10 cmp r3, #16 800220c: d122 bne.n 8002254 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 800220e: 687b ldr r3, [r7, #4] 8002210: 681b ldr r3, [r3, #0] 8002212: 68db ldr r3, [r3, #12] 8002214: f003 0310 and.w r3, r3, #16 8002218: 2b10 cmp r3, #16 800221a: d11b bne.n 8002254 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 800221c: 687b ldr r3, [r7, #4] 800221e: 681b ldr r3, [r3, #0] 8002220: f06f 0210 mvn.w r2, #16 8002224: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8002226: 687b ldr r3, [r7, #4] 8002228: 2208 movs r2, #8 800222a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800222c: 687b ldr r3, [r7, #4] 800222e: 681b ldr r3, [r3, #0] 8002230: 69db ldr r3, [r3, #28] 8002232: f403 7340 and.w r3, r3, #768 ; 0x300 8002236: 2b00 cmp r3, #0 8002238: d003 beq.n 8002242 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800223a: 6878 ldr r0, [r7, #4] 800223c: f000 fa5f bl 80026fe 8002240: e005 b.n 800224e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002242: 6878 ldr r0, [r7, #4] 8002244: f000 fa51 bl 80026ea HAL_TIM_PWM_PulseFinishedCallback(htim); 8002248: 6878 ldr r0, [r7, #4] 800224a: f000 fa62 bl 8002712 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800224e: 687b ldr r3, [r7, #4] 8002250: 2200 movs r2, #0 8002252: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 8002254: 687b ldr r3, [r7, #4] 8002256: 681b ldr r3, [r3, #0] 8002258: 691b ldr r3, [r3, #16] 800225a: f003 0301 and.w r3, r3, #1 800225e: 2b01 cmp r3, #1 8002260: d10e bne.n 8002280 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 8002262: 687b ldr r3, [r7, #4] 8002264: 681b ldr r3, [r3, #0] 8002266: 68db ldr r3, [r3, #12] 8002268: f003 0301 and.w r3, r3, #1 800226c: 2b01 cmp r3, #1 800226e: d107 bne.n 8002280 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 8002270: 687b ldr r3, [r7, #4] 8002272: 681b ldr r3, [r3, #0] 8002274: f06f 0201 mvn.w r2, #1 8002278: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800227a: 6878 ldr r0, [r7, #4] 800227c: f000 fa2b bl 80026d6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 8002280: 687b ldr r3, [r7, #4] 8002282: 681b ldr r3, [r3, #0] 8002284: 691b ldr r3, [r3, #16] 8002286: f003 0380 and.w r3, r3, #128 ; 0x80 800228a: 2b80 cmp r3, #128 ; 0x80 800228c: d10e bne.n 80022ac { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 800228e: 687b ldr r3, [r7, #4] 8002290: 681b ldr r3, [r3, #0] 8002292: 68db ldr r3, [r3, #12] 8002294: f003 0380 and.w r3, r3, #128 ; 0x80 8002298: 2b80 cmp r3, #128 ; 0x80 800229a: d107 bne.n 80022ac { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 800229c: 687b ldr r3, [r7, #4] 800229e: 681b ldr r3, [r3, #0] 80022a0: f06f 0280 mvn.w r2, #128 ; 0x80 80022a4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80022a6: 6878 ldr r0, [r7, #4] 80022a8: f000 fe30 bl 8002f0c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 80022ac: 687b ldr r3, [r7, #4] 80022ae: 681b ldr r3, [r3, #0] 80022b0: 691b ldr r3, [r3, #16] 80022b2: f003 0340 and.w r3, r3, #64 ; 0x40 80022b6: 2b40 cmp r3, #64 ; 0x40 80022b8: d10e bne.n 80022d8 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 80022ba: 687b ldr r3, [r7, #4] 80022bc: 681b ldr r3, [r3, #0] 80022be: 68db ldr r3, [r3, #12] 80022c0: f003 0340 and.w r3, r3, #64 ; 0x40 80022c4: 2b40 cmp r3, #64 ; 0x40 80022c6: d107 bne.n 80022d8 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 80022c8: 687b ldr r3, [r7, #4] 80022ca: 681b ldr r3, [r3, #0] 80022cc: f06f 0240 mvn.w r2, #64 ; 0x40 80022d0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 80022d2: 6878 ldr r0, [r7, #4] 80022d4: f000 fa27 bl 8002726 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 80022d8: 687b ldr r3, [r7, #4] 80022da: 681b ldr r3, [r3, #0] 80022dc: 691b ldr r3, [r3, #16] 80022de: f003 0320 and.w r3, r3, #32 80022e2: 2b20 cmp r3, #32 80022e4: d10e bne.n 8002304 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 80022e6: 687b ldr r3, [r7, #4] 80022e8: 681b ldr r3, [r3, #0] 80022ea: 68db ldr r3, [r3, #12] 80022ec: f003 0320 and.w r3, r3, #32 80022f0: 2b20 cmp r3, #32 80022f2: d107 bne.n 8002304 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 80022f4: 687b ldr r3, [r7, #4] 80022f6: 681b ldr r3, [r3, #0] 80022f8: f06f 0220 mvn.w r2, #32 80022fc: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 80022fe: 6878 ldr r0, [r7, #4] 8002300: f000 fdfa bl 8002ef8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8002304: bf00 nop 8002306: 3708 adds r7, #8 8002308: 46bd mov sp, r7 800230a: bd80 pop {r7, pc} 0800230c : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 800230c: b580 push {r7, lr} 800230e: b086 sub sp, #24 8002310: af00 add r7, sp, #0 8002312: 60f8 str r0, [r7, #12] 8002314: 60b9 str r1, [r7, #8] 8002316: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002318: 2300 movs r3, #0 800231a: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 800231c: 68fb ldr r3, [r7, #12] 800231e: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8002322: 2b01 cmp r3, #1 8002324: d101 bne.n 800232a 8002326: 2302 movs r3, #2 8002328: e048 b.n 80023bc 800232a: 68fb ldr r3, [r7, #12] 800232c: 2201 movs r2, #1 800232e: f883 203c strb.w r2, [r3, #60] ; 0x3c switch (Channel) 8002332: 687b ldr r3, [r7, #4] 8002334: 2b0c cmp r3, #12 8002336: d839 bhi.n 80023ac 8002338: a201 add r2, pc, #4 ; (adr r2, 8002340 ) 800233a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800233e: bf00 nop 8002340: 08002375 .word 0x08002375 8002344: 080023ad .word 0x080023ad 8002348: 080023ad .word 0x080023ad 800234c: 080023ad .word 0x080023ad 8002350: 08002383 .word 0x08002383 8002354: 080023ad .word 0x080023ad 8002358: 080023ad .word 0x080023ad 800235c: 080023ad .word 0x080023ad 8002360: 08002391 .word 0x08002391 8002364: 080023ad .word 0x080023ad 8002368: 080023ad .word 0x080023ad 800236c: 080023ad .word 0x080023ad 8002370: 0800239f .word 0x0800239f { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8002374: 68fb ldr r3, [r7, #12] 8002376: 681b ldr r3, [r3, #0] 8002378: 68b9 ldr r1, [r7, #8] 800237a: 4618 mov r0, r3 800237c: f000 fa7e bl 800287c break; 8002380: e017 b.n 80023b2 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8002382: 68fb ldr r3, [r7, #12] 8002384: 681b ldr r3, [r3, #0] 8002386: 68b9 ldr r1, [r7, #8] 8002388: 4618 mov r0, r3 800238a: f000 fae7 bl 800295c break; 800238e: e010 b.n 80023b2 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8002390: 68fb ldr r3, [r7, #12] 8002392: 681b ldr r3, [r3, #0] 8002394: 68b9 ldr r1, [r7, #8] 8002396: 4618 mov r0, r3 8002398: f000 fb56 bl 8002a48 break; 800239c: e009 b.n 80023b2 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 800239e: 68fb ldr r3, [r7, #12] 80023a0: 681b ldr r3, [r3, #0] 80023a2: 68b9 ldr r1, [r7, #8] 80023a4: 4618 mov r0, r3 80023a6: f000 fbc3 bl 8002b30 break; 80023aa: e002 b.n 80023b2 } default: status = HAL_ERROR; 80023ac: 2301 movs r3, #1 80023ae: 75fb strb r3, [r7, #23] break; 80023b0: bf00 nop } __HAL_UNLOCK(htim); 80023b2: 68fb ldr r3, [r7, #12] 80023b4: 2200 movs r2, #0 80023b6: f883 203c strb.w r2, [r3, #60] ; 0x3c return status; 80023ba: 7dfb ldrb r3, [r7, #23] } 80023bc: 4618 mov r0, r3 80023be: 3718 adds r7, #24 80023c0: 46bd mov sp, r7 80023c2: bd80 pop {r7, pc} 080023c4 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80023c4: b580 push {r7, lr} 80023c6: b086 sub sp, #24 80023c8: af00 add r7, sp, #0 80023ca: 60f8 str r0, [r7, #12] 80023cc: 60b9 str r1, [r7, #8] 80023ce: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80023d0: 2300 movs r3, #0 80023d2: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 80023d4: 68fb ldr r3, [r7, #12] 80023d6: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 80023da: 2b01 cmp r3, #1 80023dc: d101 bne.n 80023e2 80023de: 2302 movs r3, #2 80023e0: e0ae b.n 8002540 80023e2: 68fb ldr r3, [r7, #12] 80023e4: 2201 movs r2, #1 80023e6: f883 203c strb.w r2, [r3, #60] ; 0x3c switch (Channel) 80023ea: 687b ldr r3, [r7, #4] 80023ec: 2b0c cmp r3, #12 80023ee: f200 809f bhi.w 8002530 80023f2: a201 add r2, pc, #4 ; (adr r2, 80023f8 ) 80023f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80023f8: 0800242d .word 0x0800242d 80023fc: 08002531 .word 0x08002531 8002400: 08002531 .word 0x08002531 8002404: 08002531 .word 0x08002531 8002408: 0800246d .word 0x0800246d 800240c: 08002531 .word 0x08002531 8002410: 08002531 .word 0x08002531 8002414: 08002531 .word 0x08002531 8002418: 080024af .word 0x080024af 800241c: 08002531 .word 0x08002531 8002420: 08002531 .word 0x08002531 8002424: 08002531 .word 0x08002531 8002428: 080024ef .word 0x080024ef { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 800242c: 68fb ldr r3, [r7, #12] 800242e: 681b ldr r3, [r3, #0] 8002430: 68b9 ldr r1, [r7, #8] 8002432: 4618 mov r0, r3 8002434: f000 fa22 bl 800287c /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8002438: 68fb ldr r3, [r7, #12] 800243a: 681b ldr r3, [r3, #0] 800243c: 699a ldr r2, [r3, #24] 800243e: 68fb ldr r3, [r7, #12] 8002440: 681b ldr r3, [r3, #0] 8002442: f042 0208 orr.w r2, r2, #8 8002446: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8002448: 68fb ldr r3, [r7, #12] 800244a: 681b ldr r3, [r3, #0] 800244c: 699a ldr r2, [r3, #24] 800244e: 68fb ldr r3, [r7, #12] 8002450: 681b ldr r3, [r3, #0] 8002452: f022 0204 bic.w r2, r2, #4 8002456: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8002458: 68fb ldr r3, [r7, #12] 800245a: 681b ldr r3, [r3, #0] 800245c: 6999 ldr r1, [r3, #24] 800245e: 68bb ldr r3, [r7, #8] 8002460: 691a ldr r2, [r3, #16] 8002462: 68fb ldr r3, [r7, #12] 8002464: 681b ldr r3, [r3, #0] 8002466: 430a orrs r2, r1 8002468: 619a str r2, [r3, #24] break; 800246a: e064 b.n 8002536 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 800246c: 68fb ldr r3, [r7, #12] 800246e: 681b ldr r3, [r3, #0] 8002470: 68b9 ldr r1, [r7, #8] 8002472: 4618 mov r0, r3 8002474: f000 fa72 bl 800295c /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8002478: 68fb ldr r3, [r7, #12] 800247a: 681b ldr r3, [r3, #0] 800247c: 699a ldr r2, [r3, #24] 800247e: 68fb ldr r3, [r7, #12] 8002480: 681b ldr r3, [r3, #0] 8002482: f442 6200 orr.w r2, r2, #2048 ; 0x800 8002486: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8002488: 68fb ldr r3, [r7, #12] 800248a: 681b ldr r3, [r3, #0] 800248c: 699a ldr r2, [r3, #24] 800248e: 68fb ldr r3, [r7, #12] 8002490: 681b ldr r3, [r3, #0] 8002492: f422 6280 bic.w r2, r2, #1024 ; 0x400 8002496: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8002498: 68fb ldr r3, [r7, #12] 800249a: 681b ldr r3, [r3, #0] 800249c: 6999 ldr r1, [r3, #24] 800249e: 68bb ldr r3, [r7, #8] 80024a0: 691b ldr r3, [r3, #16] 80024a2: 021a lsls r2, r3, #8 80024a4: 68fb ldr r3, [r7, #12] 80024a6: 681b ldr r3, [r3, #0] 80024a8: 430a orrs r2, r1 80024aa: 619a str r2, [r3, #24] break; 80024ac: e043 b.n 8002536 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 80024ae: 68fb ldr r3, [r7, #12] 80024b0: 681b ldr r3, [r3, #0] 80024b2: 68b9 ldr r1, [r7, #8] 80024b4: 4618 mov r0, r3 80024b6: f000 fac7 bl 8002a48 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 80024ba: 68fb ldr r3, [r7, #12] 80024bc: 681b ldr r3, [r3, #0] 80024be: 69da ldr r2, [r3, #28] 80024c0: 68fb ldr r3, [r7, #12] 80024c2: 681b ldr r3, [r3, #0] 80024c4: f042 0208 orr.w r2, r2, #8 80024c8: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 80024ca: 68fb ldr r3, [r7, #12] 80024cc: 681b ldr r3, [r3, #0] 80024ce: 69da ldr r2, [r3, #28] 80024d0: 68fb ldr r3, [r7, #12] 80024d2: 681b ldr r3, [r3, #0] 80024d4: f022 0204 bic.w r2, r2, #4 80024d8: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 80024da: 68fb ldr r3, [r7, #12] 80024dc: 681b ldr r3, [r3, #0] 80024de: 69d9 ldr r1, [r3, #28] 80024e0: 68bb ldr r3, [r7, #8] 80024e2: 691a ldr r2, [r3, #16] 80024e4: 68fb ldr r3, [r7, #12] 80024e6: 681b ldr r3, [r3, #0] 80024e8: 430a orrs r2, r1 80024ea: 61da str r2, [r3, #28] break; 80024ec: e023 b.n 8002536 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80024ee: 68fb ldr r3, [r7, #12] 80024f0: 681b ldr r3, [r3, #0] 80024f2: 68b9 ldr r1, [r7, #8] 80024f4: 4618 mov r0, r3 80024f6: f000 fb1b bl 8002b30 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80024fa: 68fb ldr r3, [r7, #12] 80024fc: 681b ldr r3, [r3, #0] 80024fe: 69da ldr r2, [r3, #28] 8002500: 68fb ldr r3, [r7, #12] 8002502: 681b ldr r3, [r3, #0] 8002504: f442 6200 orr.w r2, r2, #2048 ; 0x800 8002508: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 800250a: 68fb ldr r3, [r7, #12] 800250c: 681b ldr r3, [r3, #0] 800250e: 69da ldr r2, [r3, #28] 8002510: 68fb ldr r3, [r7, #12] 8002512: 681b ldr r3, [r3, #0] 8002514: f422 6280 bic.w r2, r2, #1024 ; 0x400 8002518: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800251a: 68fb ldr r3, [r7, #12] 800251c: 681b ldr r3, [r3, #0] 800251e: 69d9 ldr r1, [r3, #28] 8002520: 68bb ldr r3, [r7, #8] 8002522: 691b ldr r3, [r3, #16] 8002524: 021a lsls r2, r3, #8 8002526: 68fb ldr r3, [r7, #12] 8002528: 681b ldr r3, [r3, #0] 800252a: 430a orrs r2, r1 800252c: 61da str r2, [r3, #28] break; 800252e: e002 b.n 8002536 } default: status = HAL_ERROR; 8002530: 2301 movs r3, #1 8002532: 75fb strb r3, [r7, #23] break; 8002534: bf00 nop } __HAL_UNLOCK(htim); 8002536: 68fb ldr r3, [r7, #12] 8002538: 2200 movs r2, #0 800253a: f883 203c strb.w r2, [r3, #60] ; 0x3c return status; 800253e: 7dfb ldrb r3, [r7, #23] } 8002540: 4618 mov r0, r3 8002542: 3718 adds r7, #24 8002544: 46bd mov sp, r7 8002546: bd80 pop {r7, pc} 08002548 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { 8002548: b580 push {r7, lr} 800254a: b084 sub sp, #16 800254c: af00 add r7, sp, #0 800254e: 6078 str r0, [r7, #4] 8002550: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8002552: 2300 movs r3, #0 8002554: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8002556: 687b ldr r3, [r7, #4] 8002558: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800255c: 2b01 cmp r3, #1 800255e: d101 bne.n 8002564 8002560: 2302 movs r3, #2 8002562: e0b4 b.n 80026ce 8002564: 687b ldr r3, [r7, #4] 8002566: 2201 movs r2, #1 8002568: f883 203c strb.w r2, [r3, #60] ; 0x3c htim->State = HAL_TIM_STATE_BUSY; 800256c: 687b ldr r3, [r7, #4] 800256e: 2202 movs r2, #2 8002570: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8002574: 687b ldr r3, [r7, #4] 8002576: 681b ldr r3, [r3, #0] 8002578: 689b ldr r3, [r3, #8] 800257a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 800257c: 68bb ldr r3, [r7, #8] 800257e: f023 0377 bic.w r3, r3, #119 ; 0x77 8002582: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8002584: 68bb ldr r3, [r7, #8] 8002586: f423 437f bic.w r3, r3, #65280 ; 0xff00 800258a: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 800258c: 687b ldr r3, [r7, #4] 800258e: 681b ldr r3, [r3, #0] 8002590: 68ba ldr r2, [r7, #8] 8002592: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8002594: 683b ldr r3, [r7, #0] 8002596: 681b ldr r3, [r3, #0] 8002598: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800259c: d03e beq.n 800261c 800259e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80025a2: f200 8087 bhi.w 80026b4 80025a6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80025aa: f000 8086 beq.w 80026ba 80025ae: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80025b2: d87f bhi.n 80026b4 80025b4: 2b70 cmp r3, #112 ; 0x70 80025b6: d01a beq.n 80025ee 80025b8: 2b70 cmp r3, #112 ; 0x70 80025ba: d87b bhi.n 80026b4 80025bc: 2b60 cmp r3, #96 ; 0x60 80025be: d050 beq.n 8002662 80025c0: 2b60 cmp r3, #96 ; 0x60 80025c2: d877 bhi.n 80026b4 80025c4: 2b50 cmp r3, #80 ; 0x50 80025c6: d03c beq.n 8002642 80025c8: 2b50 cmp r3, #80 ; 0x50 80025ca: d873 bhi.n 80026b4 80025cc: 2b40 cmp r3, #64 ; 0x40 80025ce: d058 beq.n 8002682 80025d0: 2b40 cmp r3, #64 ; 0x40 80025d2: d86f bhi.n 80026b4 80025d4: 2b30 cmp r3, #48 ; 0x30 80025d6: d064 beq.n 80026a2 80025d8: 2b30 cmp r3, #48 ; 0x30 80025da: d86b bhi.n 80026b4 80025dc: 2b20 cmp r3, #32 80025de: d060 beq.n 80026a2 80025e0: 2b20 cmp r3, #32 80025e2: d867 bhi.n 80026b4 80025e4: 2b00 cmp r3, #0 80025e6: d05c beq.n 80026a2 80025e8: 2b10 cmp r3, #16 80025ea: d05a beq.n 80026a2 80025ec: e062 b.n 80026b4 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80025ee: 687b ldr r3, [r7, #4] 80025f0: 6818 ldr r0, [r3, #0] 80025f2: 683b ldr r3, [r7, #0] 80025f4: 6899 ldr r1, [r3, #8] 80025f6: 683b ldr r3, [r7, #0] 80025f8: 685a ldr r2, [r3, #4] 80025fa: 683b ldr r3, [r7, #0] 80025fc: 68db ldr r3, [r3, #12] 80025fe: f000 fb67 bl 8002cd0 sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8002602: 687b ldr r3, [r7, #4] 8002604: 681b ldr r3, [r3, #0] 8002606: 689b ldr r3, [r3, #8] 8002608: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 800260a: 68bb ldr r3, [r7, #8] 800260c: f043 0377 orr.w r3, r3, #119 ; 0x77 8002610: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8002612: 687b ldr r3, [r7, #4] 8002614: 681b ldr r3, [r3, #0] 8002616: 68ba ldr r2, [r7, #8] 8002618: 609a str r2, [r3, #8] break; 800261a: e04f b.n 80026bc assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800261c: 687b ldr r3, [r7, #4] 800261e: 6818 ldr r0, [r3, #0] 8002620: 683b ldr r3, [r7, #0] 8002622: 6899 ldr r1, [r3, #8] 8002624: 683b ldr r3, [r7, #0] 8002626: 685a ldr r2, [r3, #4] 8002628: 683b ldr r3, [r7, #0] 800262a: 68db ldr r3, [r3, #12] 800262c: f000 fb50 bl 8002cd0 sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8002630: 687b ldr r3, [r7, #4] 8002632: 681b ldr r3, [r3, #0] 8002634: 689a ldr r2, [r3, #8] 8002636: 687b ldr r3, [r7, #4] 8002638: 681b ldr r3, [r3, #0] 800263a: f442 4280 orr.w r2, r2, #16384 ; 0x4000 800263e: 609a str r2, [r3, #8] break; 8002640: e03c b.n 80026bc /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8002642: 687b ldr r3, [r7, #4] 8002644: 6818 ldr r0, [r3, #0] 8002646: 683b ldr r3, [r7, #0] 8002648: 6859 ldr r1, [r3, #4] 800264a: 683b ldr r3, [r7, #0] 800264c: 68db ldr r3, [r3, #12] 800264e: 461a mov r2, r3 8002650: f000 fac4 bl 8002bdc sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8002654: 687b ldr r3, [r7, #4] 8002656: 681b ldr r3, [r3, #0] 8002658: 2150 movs r1, #80 ; 0x50 800265a: 4618 mov r0, r3 800265c: f000 fb1d bl 8002c9a break; 8002660: e02c b.n 80026bc /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 8002662: 687b ldr r3, [r7, #4] 8002664: 6818 ldr r0, [r3, #0] 8002666: 683b ldr r3, [r7, #0] 8002668: 6859 ldr r1, [r3, #4] 800266a: 683b ldr r3, [r7, #0] 800266c: 68db ldr r3, [r3, #12] 800266e: 461a mov r2, r3 8002670: f000 fae3 bl 8002c3a sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8002674: 687b ldr r3, [r7, #4] 8002676: 681b ldr r3, [r3, #0] 8002678: 2160 movs r1, #96 ; 0x60 800267a: 4618 mov r0, r3 800267c: f000 fb0d bl 8002c9a break; 8002680: e01c b.n 80026bc /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8002682: 687b ldr r3, [r7, #4] 8002684: 6818 ldr r0, [r3, #0] 8002686: 683b ldr r3, [r7, #0] 8002688: 6859 ldr r1, [r3, #4] 800268a: 683b ldr r3, [r7, #0] 800268c: 68db ldr r3, [r3, #12] 800268e: 461a mov r2, r3 8002690: f000 faa4 bl 8002bdc sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8002694: 687b ldr r3, [r7, #4] 8002696: 681b ldr r3, [r3, #0] 8002698: 2140 movs r1, #64 ; 0x40 800269a: 4618 mov r0, r3 800269c: f000 fafd bl 8002c9a break; 80026a0: e00c b.n 80026bc case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 80026a2: 687b ldr r3, [r7, #4] 80026a4: 681a ldr r2, [r3, #0] 80026a6: 683b ldr r3, [r7, #0] 80026a8: 681b ldr r3, [r3, #0] 80026aa: 4619 mov r1, r3 80026ac: 4610 mov r0, r2 80026ae: f000 faf4 bl 8002c9a break; 80026b2: e003 b.n 80026bc } default: status = HAL_ERROR; 80026b4: 2301 movs r3, #1 80026b6: 73fb strb r3, [r7, #15] break; 80026b8: e000 b.n 80026bc break; 80026ba: bf00 nop } htim->State = HAL_TIM_STATE_READY; 80026bc: 687b ldr r3, [r7, #4] 80026be: 2201 movs r2, #1 80026c0: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 80026c4: 687b ldr r3, [r7, #4] 80026c6: 2200 movs r2, #0 80026c8: f883 203c strb.w r2, [r3, #60] ; 0x3c return status; 80026cc: 7bfb ldrb r3, [r7, #15] } 80026ce: 4618 mov r0, r3 80026d0: 3710 adds r7, #16 80026d2: 46bd mov sp, r7 80026d4: bd80 pop {r7, pc} 080026d6 : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 80026d6: b480 push {r7} 80026d8: b083 sub sp, #12 80026da: af00 add r7, sp, #0 80026dc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 80026de: bf00 nop 80026e0: 370c adds r7, #12 80026e2: 46bd mov sp, r7 80026e4: f85d 7b04 ldr.w r7, [sp], #4 80026e8: 4770 bx lr 080026ea : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80026ea: b480 push {r7} 80026ec: b083 sub sp, #12 80026ee: af00 add r7, sp, #0 80026f0: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80026f2: bf00 nop 80026f4: 370c adds r7, #12 80026f6: 46bd mov sp, r7 80026f8: f85d 7b04 ldr.w r7, [sp], #4 80026fc: 4770 bx lr 080026fe : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80026fe: b480 push {r7} 8002700: b083 sub sp, #12 8002702: af00 add r7, sp, #0 8002704: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8002706: bf00 nop 8002708: 370c adds r7, #12 800270a: 46bd mov sp, r7 800270c: f85d 7b04 ldr.w r7, [sp], #4 8002710: 4770 bx lr 08002712 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8002712: b480 push {r7} 8002714: b083 sub sp, #12 8002716: af00 add r7, sp, #0 8002718: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 800271a: bf00 nop 800271c: 370c adds r7, #12 800271e: 46bd mov sp, r7 8002720: f85d 7b04 ldr.w r7, [sp], #4 8002724: 4770 bx lr 08002726 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8002726: b480 push {r7} 8002728: b083 sub sp, #12 800272a: af00 add r7, sp, #0 800272c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 800272e: bf00 nop 8002730: 370c adds r7, #12 8002732: 46bd mov sp, r7 8002734: f85d 7b04 ldr.w r7, [sp], #4 8002738: 4770 bx lr ... 0800273c : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 800273c: b480 push {r7} 800273e: b085 sub sp, #20 8002740: af00 add r7, sp, #0 8002742: 6078 str r0, [r7, #4] 8002744: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8002746: 687b ldr r3, [r7, #4] 8002748: 681b ldr r3, [r3, #0] 800274a: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800274c: 687b ldr r3, [r7, #4] 800274e: 4a40 ldr r2, [pc, #256] ; (8002850 ) 8002750: 4293 cmp r3, r2 8002752: d013 beq.n 800277c 8002754: 687b ldr r3, [r7, #4] 8002756: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800275a: d00f beq.n 800277c 800275c: 687b ldr r3, [r7, #4] 800275e: 4a3d ldr r2, [pc, #244] ; (8002854 ) 8002760: 4293 cmp r3, r2 8002762: d00b beq.n 800277c 8002764: 687b ldr r3, [r7, #4] 8002766: 4a3c ldr r2, [pc, #240] ; (8002858 ) 8002768: 4293 cmp r3, r2 800276a: d007 beq.n 800277c 800276c: 687b ldr r3, [r7, #4] 800276e: 4a3b ldr r2, [pc, #236] ; (800285c ) 8002770: 4293 cmp r3, r2 8002772: d003 beq.n 800277c 8002774: 687b ldr r3, [r7, #4] 8002776: 4a3a ldr r2, [pc, #232] ; (8002860 ) 8002778: 4293 cmp r3, r2 800277a: d108 bne.n 800278e { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800277c: 68fb ldr r3, [r7, #12] 800277e: f023 0370 bic.w r3, r3, #112 ; 0x70 8002782: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8002784: 683b ldr r3, [r7, #0] 8002786: 685b ldr r3, [r3, #4] 8002788: 68fa ldr r2, [r7, #12] 800278a: 4313 orrs r3, r2 800278c: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800278e: 687b ldr r3, [r7, #4] 8002790: 4a2f ldr r2, [pc, #188] ; (8002850 ) 8002792: 4293 cmp r3, r2 8002794: d02b beq.n 80027ee 8002796: 687b ldr r3, [r7, #4] 8002798: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800279c: d027 beq.n 80027ee 800279e: 687b ldr r3, [r7, #4] 80027a0: 4a2c ldr r2, [pc, #176] ; (8002854 ) 80027a2: 4293 cmp r3, r2 80027a4: d023 beq.n 80027ee 80027a6: 687b ldr r3, [r7, #4] 80027a8: 4a2b ldr r2, [pc, #172] ; (8002858 ) 80027aa: 4293 cmp r3, r2 80027ac: d01f beq.n 80027ee 80027ae: 687b ldr r3, [r7, #4] 80027b0: 4a2a ldr r2, [pc, #168] ; (800285c ) 80027b2: 4293 cmp r3, r2 80027b4: d01b beq.n 80027ee 80027b6: 687b ldr r3, [r7, #4] 80027b8: 4a29 ldr r2, [pc, #164] ; (8002860 ) 80027ba: 4293 cmp r3, r2 80027bc: d017 beq.n 80027ee 80027be: 687b ldr r3, [r7, #4] 80027c0: 4a28 ldr r2, [pc, #160] ; (8002864 ) 80027c2: 4293 cmp r3, r2 80027c4: d013 beq.n 80027ee 80027c6: 687b ldr r3, [r7, #4] 80027c8: 4a27 ldr r2, [pc, #156] ; (8002868 ) 80027ca: 4293 cmp r3, r2 80027cc: d00f beq.n 80027ee 80027ce: 687b ldr r3, [r7, #4] 80027d0: 4a26 ldr r2, [pc, #152] ; (800286c ) 80027d2: 4293 cmp r3, r2 80027d4: d00b beq.n 80027ee 80027d6: 687b ldr r3, [r7, #4] 80027d8: 4a25 ldr r2, [pc, #148] ; (8002870 ) 80027da: 4293 cmp r3, r2 80027dc: d007 beq.n 80027ee 80027de: 687b ldr r3, [r7, #4] 80027e0: 4a24 ldr r2, [pc, #144] ; (8002874 ) 80027e2: 4293 cmp r3, r2 80027e4: d003 beq.n 80027ee 80027e6: 687b ldr r3, [r7, #4] 80027e8: 4a23 ldr r2, [pc, #140] ; (8002878 ) 80027ea: 4293 cmp r3, r2 80027ec: d108 bne.n 8002800 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80027ee: 68fb ldr r3, [r7, #12] 80027f0: f423 7340 bic.w r3, r3, #768 ; 0x300 80027f4: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80027f6: 683b ldr r3, [r7, #0] 80027f8: 68db ldr r3, [r3, #12] 80027fa: 68fa ldr r2, [r7, #12] 80027fc: 4313 orrs r3, r2 80027fe: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8002800: 68fb ldr r3, [r7, #12] 8002802: f023 0280 bic.w r2, r3, #128 ; 0x80 8002806: 683b ldr r3, [r7, #0] 8002808: 695b ldr r3, [r3, #20] 800280a: 4313 orrs r3, r2 800280c: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800280e: 687b ldr r3, [r7, #4] 8002810: 68fa ldr r2, [r7, #12] 8002812: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8002814: 683b ldr r3, [r7, #0] 8002816: 689a ldr r2, [r3, #8] 8002818: 687b ldr r3, [r7, #4] 800281a: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800281c: 683b ldr r3, [r7, #0] 800281e: 681a ldr r2, [r3, #0] 8002820: 687b ldr r3, [r7, #4] 8002822: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8002824: 687b ldr r3, [r7, #4] 8002826: 4a0a ldr r2, [pc, #40] ; (8002850 ) 8002828: 4293 cmp r3, r2 800282a: d003 beq.n 8002834 800282c: 687b ldr r3, [r7, #4] 800282e: 4a0c ldr r2, [pc, #48] ; (8002860 ) 8002830: 4293 cmp r3, r2 8002832: d103 bne.n 800283c { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8002834: 683b ldr r3, [r7, #0] 8002836: 691a ldr r2, [r3, #16] 8002838: 687b ldr r3, [r7, #4] 800283a: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800283c: 687b ldr r3, [r7, #4] 800283e: 2201 movs r2, #1 8002840: 615a str r2, [r3, #20] } 8002842: bf00 nop 8002844: 3714 adds r7, #20 8002846: 46bd mov sp, r7 8002848: f85d 7b04 ldr.w r7, [sp], #4 800284c: 4770 bx lr 800284e: bf00 nop 8002850: 40010000 .word 0x40010000 8002854: 40000400 .word 0x40000400 8002858: 40000800 .word 0x40000800 800285c: 40000c00 .word 0x40000c00 8002860: 40010400 .word 0x40010400 8002864: 40014000 .word 0x40014000 8002868: 40014400 .word 0x40014400 800286c: 40014800 .word 0x40014800 8002870: 40001800 .word 0x40001800 8002874: 40001c00 .word 0x40001c00 8002878: 40002000 .word 0x40002000 0800287c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 800287c: b480 push {r7} 800287e: b087 sub sp, #28 8002880: af00 add r7, sp, #0 8002882: 6078 str r0, [r7, #4] 8002884: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8002886: 687b ldr r3, [r7, #4] 8002888: 6a1b ldr r3, [r3, #32] 800288a: f023 0201 bic.w r2, r3, #1 800288e: 687b ldr r3, [r7, #4] 8002890: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8002892: 687b ldr r3, [r7, #4] 8002894: 6a1b ldr r3, [r3, #32] 8002896: 617b str r3, [r7, #20] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8002898: 687b ldr r3, [r7, #4] 800289a: 685b ldr r3, [r3, #4] 800289c: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800289e: 687b ldr r3, [r7, #4] 80028a0: 699b ldr r3, [r3, #24] 80028a2: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80028a4: 68fb ldr r3, [r7, #12] 80028a6: f023 0370 bic.w r3, r3, #112 ; 0x70 80028aa: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80028ac: 68fb ldr r3, [r7, #12] 80028ae: f023 0303 bic.w r3, r3, #3 80028b2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80028b4: 683b ldr r3, [r7, #0] 80028b6: 681b ldr r3, [r3, #0] 80028b8: 68fa ldr r2, [r7, #12] 80028ba: 4313 orrs r3, r2 80028bc: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80028be: 697b ldr r3, [r7, #20] 80028c0: f023 0302 bic.w r3, r3, #2 80028c4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 80028c6: 683b ldr r3, [r7, #0] 80028c8: 689b ldr r3, [r3, #8] 80028ca: 697a ldr r2, [r7, #20] 80028cc: 4313 orrs r3, r2 80028ce: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80028d0: 687b ldr r3, [r7, #4] 80028d2: 4a20 ldr r2, [pc, #128] ; (8002954 ) 80028d4: 4293 cmp r3, r2 80028d6: d003 beq.n 80028e0 80028d8: 687b ldr r3, [r7, #4] 80028da: 4a1f ldr r2, [pc, #124] ; (8002958 ) 80028dc: 4293 cmp r3, r2 80028de: d10c bne.n 80028fa { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 80028e0: 697b ldr r3, [r7, #20] 80028e2: f023 0308 bic.w r3, r3, #8 80028e6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 80028e8: 683b ldr r3, [r7, #0] 80028ea: 68db ldr r3, [r3, #12] 80028ec: 697a ldr r2, [r7, #20] 80028ee: 4313 orrs r3, r2 80028f0: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 80028f2: 697b ldr r3, [r7, #20] 80028f4: f023 0304 bic.w r3, r3, #4 80028f8: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80028fa: 687b ldr r3, [r7, #4] 80028fc: 4a15 ldr r2, [pc, #84] ; (8002954 ) 80028fe: 4293 cmp r3, r2 8002900: d003 beq.n 800290a 8002902: 687b ldr r3, [r7, #4] 8002904: 4a14 ldr r2, [pc, #80] ; (8002958 ) 8002906: 4293 cmp r3, r2 8002908: d111 bne.n 800292e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 800290a: 693b ldr r3, [r7, #16] 800290c: f423 7380 bic.w r3, r3, #256 ; 0x100 8002910: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8002912: 693b ldr r3, [r7, #16] 8002914: f423 7300 bic.w r3, r3, #512 ; 0x200 8002918: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 800291a: 683b ldr r3, [r7, #0] 800291c: 695b ldr r3, [r3, #20] 800291e: 693a ldr r2, [r7, #16] 8002920: 4313 orrs r3, r2 8002922: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8002924: 683b ldr r3, [r7, #0] 8002926: 699b ldr r3, [r3, #24] 8002928: 693a ldr r2, [r7, #16] 800292a: 4313 orrs r3, r2 800292c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800292e: 687b ldr r3, [r7, #4] 8002930: 693a ldr r2, [r7, #16] 8002932: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8002934: 687b ldr r3, [r7, #4] 8002936: 68fa ldr r2, [r7, #12] 8002938: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 800293a: 683b ldr r3, [r7, #0] 800293c: 685a ldr r2, [r3, #4] 800293e: 687b ldr r3, [r7, #4] 8002940: 635a str r2, [r3, #52] ; 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8002942: 687b ldr r3, [r7, #4] 8002944: 697a ldr r2, [r7, #20] 8002946: 621a str r2, [r3, #32] } 8002948: bf00 nop 800294a: 371c adds r7, #28 800294c: 46bd mov sp, r7 800294e: f85d 7b04 ldr.w r7, [sp], #4 8002952: 4770 bx lr 8002954: 40010000 .word 0x40010000 8002958: 40010400 .word 0x40010400 0800295c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 800295c: b480 push {r7} 800295e: b087 sub sp, #28 8002960: af00 add r7, sp, #0 8002962: 6078 str r0, [r7, #4] 8002964: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8002966: 687b ldr r3, [r7, #4] 8002968: 6a1b ldr r3, [r3, #32] 800296a: f023 0210 bic.w r2, r3, #16 800296e: 687b ldr r3, [r7, #4] 8002970: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8002972: 687b ldr r3, [r7, #4] 8002974: 6a1b ldr r3, [r3, #32] 8002976: 617b str r3, [r7, #20] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8002978: 687b ldr r3, [r7, #4] 800297a: 685b ldr r3, [r3, #4] 800297c: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800297e: 687b ldr r3, [r7, #4] 8002980: 699b ldr r3, [r3, #24] 8002982: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8002984: 68fb ldr r3, [r7, #12] 8002986: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 800298a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 800298c: 68fb ldr r3, [r7, #12] 800298e: f423 7340 bic.w r3, r3, #768 ; 0x300 8002992: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8002994: 683b ldr r3, [r7, #0] 8002996: 681b ldr r3, [r3, #0] 8002998: 021b lsls r3, r3, #8 800299a: 68fa ldr r2, [r7, #12] 800299c: 4313 orrs r3, r2 800299e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80029a0: 697b ldr r3, [r7, #20] 80029a2: f023 0320 bic.w r3, r3, #32 80029a6: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80029a8: 683b ldr r3, [r7, #0] 80029aa: 689b ldr r3, [r3, #8] 80029ac: 011b lsls r3, r3, #4 80029ae: 697a ldr r2, [r7, #20] 80029b0: 4313 orrs r3, r2 80029b2: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80029b4: 687b ldr r3, [r7, #4] 80029b6: 4a22 ldr r2, [pc, #136] ; (8002a40 ) 80029b8: 4293 cmp r3, r2 80029ba: d003 beq.n 80029c4 80029bc: 687b ldr r3, [r7, #4] 80029be: 4a21 ldr r2, [pc, #132] ; (8002a44 ) 80029c0: 4293 cmp r3, r2 80029c2: d10d bne.n 80029e0 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80029c4: 697b ldr r3, [r7, #20] 80029c6: f023 0380 bic.w r3, r3, #128 ; 0x80 80029ca: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 80029cc: 683b ldr r3, [r7, #0] 80029ce: 68db ldr r3, [r3, #12] 80029d0: 011b lsls r3, r3, #4 80029d2: 697a ldr r2, [r7, #20] 80029d4: 4313 orrs r3, r2 80029d6: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 80029d8: 697b ldr r3, [r7, #20] 80029da: f023 0340 bic.w r3, r3, #64 ; 0x40 80029de: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80029e0: 687b ldr r3, [r7, #4] 80029e2: 4a17 ldr r2, [pc, #92] ; (8002a40 ) 80029e4: 4293 cmp r3, r2 80029e6: d003 beq.n 80029f0 80029e8: 687b ldr r3, [r7, #4] 80029ea: 4a16 ldr r2, [pc, #88] ; (8002a44 ) 80029ec: 4293 cmp r3, r2 80029ee: d113 bne.n 8002a18 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 80029f0: 693b ldr r3, [r7, #16] 80029f2: f423 6380 bic.w r3, r3, #1024 ; 0x400 80029f6: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 80029f8: 693b ldr r3, [r7, #16] 80029fa: f423 6300 bic.w r3, r3, #2048 ; 0x800 80029fe: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8002a00: 683b ldr r3, [r7, #0] 8002a02: 695b ldr r3, [r3, #20] 8002a04: 009b lsls r3, r3, #2 8002a06: 693a ldr r2, [r7, #16] 8002a08: 4313 orrs r3, r2 8002a0a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8002a0c: 683b ldr r3, [r7, #0] 8002a0e: 699b ldr r3, [r3, #24] 8002a10: 009b lsls r3, r3, #2 8002a12: 693a ldr r2, [r7, #16] 8002a14: 4313 orrs r3, r2 8002a16: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8002a18: 687b ldr r3, [r7, #4] 8002a1a: 693a ldr r2, [r7, #16] 8002a1c: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8002a1e: 687b ldr r3, [r7, #4] 8002a20: 68fa ldr r2, [r7, #12] 8002a22: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8002a24: 683b ldr r3, [r7, #0] 8002a26: 685a ldr r2, [r3, #4] 8002a28: 687b ldr r3, [r7, #4] 8002a2a: 639a str r2, [r3, #56] ; 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8002a2c: 687b ldr r3, [r7, #4] 8002a2e: 697a ldr r2, [r7, #20] 8002a30: 621a str r2, [r3, #32] } 8002a32: bf00 nop 8002a34: 371c adds r7, #28 8002a36: 46bd mov sp, r7 8002a38: f85d 7b04 ldr.w r7, [sp], #4 8002a3c: 4770 bx lr 8002a3e: bf00 nop 8002a40: 40010000 .word 0x40010000 8002a44: 40010400 .word 0x40010400 08002a48 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 8002a48: b480 push {r7} 8002a4a: b087 sub sp, #28 8002a4c: af00 add r7, sp, #0 8002a4e: 6078 str r0, [r7, #4] 8002a50: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8002a52: 687b ldr r3, [r7, #4] 8002a54: 6a1b ldr r3, [r3, #32] 8002a56: f423 7280 bic.w r2, r3, #256 ; 0x100 8002a5a: 687b ldr r3, [r7, #4] 8002a5c: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8002a5e: 687b ldr r3, [r7, #4] 8002a60: 6a1b ldr r3, [r3, #32] 8002a62: 617b str r3, [r7, #20] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8002a64: 687b ldr r3, [r7, #4] 8002a66: 685b ldr r3, [r3, #4] 8002a68: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8002a6a: 687b ldr r3, [r7, #4] 8002a6c: 69db ldr r3, [r3, #28] 8002a6e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8002a70: 68fb ldr r3, [r7, #12] 8002a72: f023 0370 bic.w r3, r3, #112 ; 0x70 8002a76: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8002a78: 68fb ldr r3, [r7, #12] 8002a7a: f023 0303 bic.w r3, r3, #3 8002a7e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8002a80: 683b ldr r3, [r7, #0] 8002a82: 681b ldr r3, [r3, #0] 8002a84: 68fa ldr r2, [r7, #12] 8002a86: 4313 orrs r3, r2 8002a88: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8002a8a: 697b ldr r3, [r7, #20] 8002a8c: f423 7300 bic.w r3, r3, #512 ; 0x200 8002a90: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8002a92: 683b ldr r3, [r7, #0] 8002a94: 689b ldr r3, [r3, #8] 8002a96: 021b lsls r3, r3, #8 8002a98: 697a ldr r2, [r7, #20] 8002a9a: 4313 orrs r3, r2 8002a9c: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8002a9e: 687b ldr r3, [r7, #4] 8002aa0: 4a21 ldr r2, [pc, #132] ; (8002b28 ) 8002aa2: 4293 cmp r3, r2 8002aa4: d003 beq.n 8002aae 8002aa6: 687b ldr r3, [r7, #4] 8002aa8: 4a20 ldr r2, [pc, #128] ; (8002b2c ) 8002aaa: 4293 cmp r3, r2 8002aac: d10d bne.n 8002aca { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8002aae: 697b ldr r3, [r7, #20] 8002ab0: f423 6300 bic.w r3, r3, #2048 ; 0x800 8002ab4: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8002ab6: 683b ldr r3, [r7, #0] 8002ab8: 68db ldr r3, [r3, #12] 8002aba: 021b lsls r3, r3, #8 8002abc: 697a ldr r2, [r7, #20] 8002abe: 4313 orrs r3, r2 8002ac0: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8002ac2: 697b ldr r3, [r7, #20] 8002ac4: f423 6380 bic.w r3, r3, #1024 ; 0x400 8002ac8: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8002aca: 687b ldr r3, [r7, #4] 8002acc: 4a16 ldr r2, [pc, #88] ; (8002b28 ) 8002ace: 4293 cmp r3, r2 8002ad0: d003 beq.n 8002ada 8002ad2: 687b ldr r3, [r7, #4] 8002ad4: 4a15 ldr r2, [pc, #84] ; (8002b2c ) 8002ad6: 4293 cmp r3, r2 8002ad8: d113 bne.n 8002b02 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8002ada: 693b ldr r3, [r7, #16] 8002adc: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8002ae0: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8002ae2: 693b ldr r3, [r7, #16] 8002ae4: f423 5300 bic.w r3, r3, #8192 ; 0x2000 8002ae8: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8002aea: 683b ldr r3, [r7, #0] 8002aec: 695b ldr r3, [r3, #20] 8002aee: 011b lsls r3, r3, #4 8002af0: 693a ldr r2, [r7, #16] 8002af2: 4313 orrs r3, r2 8002af4: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8002af6: 683b ldr r3, [r7, #0] 8002af8: 699b ldr r3, [r3, #24] 8002afa: 011b lsls r3, r3, #4 8002afc: 693a ldr r2, [r7, #16] 8002afe: 4313 orrs r3, r2 8002b00: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8002b02: 687b ldr r3, [r7, #4] 8002b04: 693a ldr r2, [r7, #16] 8002b06: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8002b08: 687b ldr r3, [r7, #4] 8002b0a: 68fa ldr r2, [r7, #12] 8002b0c: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8002b0e: 683b ldr r3, [r7, #0] 8002b10: 685a ldr r2, [r3, #4] 8002b12: 687b ldr r3, [r7, #4] 8002b14: 63da str r2, [r3, #60] ; 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8002b16: 687b ldr r3, [r7, #4] 8002b18: 697a ldr r2, [r7, #20] 8002b1a: 621a str r2, [r3, #32] } 8002b1c: bf00 nop 8002b1e: 371c adds r7, #28 8002b20: 46bd mov sp, r7 8002b22: f85d 7b04 ldr.w r7, [sp], #4 8002b26: 4770 bx lr 8002b28: 40010000 .word 0x40010000 8002b2c: 40010400 .word 0x40010400 08002b30 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 8002b30: b480 push {r7} 8002b32: b087 sub sp, #28 8002b34: af00 add r7, sp, #0 8002b36: 6078 str r0, [r7, #4] 8002b38: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8002b3a: 687b ldr r3, [r7, #4] 8002b3c: 6a1b ldr r3, [r3, #32] 8002b3e: f423 5280 bic.w r2, r3, #4096 ; 0x1000 8002b42: 687b ldr r3, [r7, #4] 8002b44: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8002b46: 687b ldr r3, [r7, #4] 8002b48: 6a1b ldr r3, [r3, #32] 8002b4a: 613b str r3, [r7, #16] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8002b4c: 687b ldr r3, [r7, #4] 8002b4e: 685b ldr r3, [r3, #4] 8002b50: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8002b52: 687b ldr r3, [r7, #4] 8002b54: 69db ldr r3, [r3, #28] 8002b56: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8002b58: 68fb ldr r3, [r7, #12] 8002b5a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 8002b5e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8002b60: 68fb ldr r3, [r7, #12] 8002b62: f423 7340 bic.w r3, r3, #768 ; 0x300 8002b66: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8002b68: 683b ldr r3, [r7, #0] 8002b6a: 681b ldr r3, [r3, #0] 8002b6c: 021b lsls r3, r3, #8 8002b6e: 68fa ldr r2, [r7, #12] 8002b70: 4313 orrs r3, r2 8002b72: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8002b74: 693b ldr r3, [r7, #16] 8002b76: f423 5300 bic.w r3, r3, #8192 ; 0x2000 8002b7a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8002b7c: 683b ldr r3, [r7, #0] 8002b7e: 689b ldr r3, [r3, #8] 8002b80: 031b lsls r3, r3, #12 8002b82: 693a ldr r2, [r7, #16] 8002b84: 4313 orrs r3, r2 8002b86: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8002b88: 687b ldr r3, [r7, #4] 8002b8a: 4a12 ldr r2, [pc, #72] ; (8002bd4 ) 8002b8c: 4293 cmp r3, r2 8002b8e: d003 beq.n 8002b98 8002b90: 687b ldr r3, [r7, #4] 8002b92: 4a11 ldr r2, [pc, #68] ; (8002bd8 ) 8002b94: 4293 cmp r3, r2 8002b96: d109 bne.n 8002bac { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8002b98: 697b ldr r3, [r7, #20] 8002b9a: f423 4380 bic.w r3, r3, #16384 ; 0x4000 8002b9e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8002ba0: 683b ldr r3, [r7, #0] 8002ba2: 695b ldr r3, [r3, #20] 8002ba4: 019b lsls r3, r3, #6 8002ba6: 697a ldr r2, [r7, #20] 8002ba8: 4313 orrs r3, r2 8002baa: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8002bac: 687b ldr r3, [r7, #4] 8002bae: 697a ldr r2, [r7, #20] 8002bb0: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8002bb2: 687b ldr r3, [r7, #4] 8002bb4: 68fa ldr r2, [r7, #12] 8002bb6: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8002bb8: 683b ldr r3, [r7, #0] 8002bba: 685a ldr r2, [r3, #4] 8002bbc: 687b ldr r3, [r7, #4] 8002bbe: 641a str r2, [r3, #64] ; 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8002bc0: 687b ldr r3, [r7, #4] 8002bc2: 693a ldr r2, [r7, #16] 8002bc4: 621a str r2, [r3, #32] } 8002bc6: bf00 nop 8002bc8: 371c adds r7, #28 8002bca: 46bd mov sp, r7 8002bcc: f85d 7b04 ldr.w r7, [sp], #4 8002bd0: 4770 bx lr 8002bd2: bf00 nop 8002bd4: 40010000 .word 0x40010000 8002bd8: 40010400 .word 0x40010400 08002bdc : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8002bdc: b480 push {r7} 8002bde: b087 sub sp, #28 8002be0: af00 add r7, sp, #0 8002be2: 60f8 str r0, [r7, #12] 8002be4: 60b9 str r1, [r7, #8] 8002be6: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8002be8: 68fb ldr r3, [r7, #12] 8002bea: 6a1b ldr r3, [r3, #32] 8002bec: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8002bee: 68fb ldr r3, [r7, #12] 8002bf0: 6a1b ldr r3, [r3, #32] 8002bf2: f023 0201 bic.w r2, r3, #1 8002bf6: 68fb ldr r3, [r7, #12] 8002bf8: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8002bfa: 68fb ldr r3, [r7, #12] 8002bfc: 699b ldr r3, [r3, #24] 8002bfe: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8002c00: 693b ldr r3, [r7, #16] 8002c02: f023 03f0 bic.w r3, r3, #240 ; 0xf0 8002c06: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8002c08: 687b ldr r3, [r7, #4] 8002c0a: 011b lsls r3, r3, #4 8002c0c: 693a ldr r2, [r7, #16] 8002c0e: 4313 orrs r3, r2 8002c10: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8002c12: 697b ldr r3, [r7, #20] 8002c14: f023 030a bic.w r3, r3, #10 8002c18: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8002c1a: 697a ldr r2, [r7, #20] 8002c1c: 68bb ldr r3, [r7, #8] 8002c1e: 4313 orrs r3, r2 8002c20: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8002c22: 68fb ldr r3, [r7, #12] 8002c24: 693a ldr r2, [r7, #16] 8002c26: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8002c28: 68fb ldr r3, [r7, #12] 8002c2a: 697a ldr r2, [r7, #20] 8002c2c: 621a str r2, [r3, #32] } 8002c2e: bf00 nop 8002c30: 371c adds r7, #28 8002c32: 46bd mov sp, r7 8002c34: f85d 7b04 ldr.w r7, [sp], #4 8002c38: 4770 bx lr 08002c3a : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8002c3a: b480 push {r7} 8002c3c: b087 sub sp, #28 8002c3e: af00 add r7, sp, #0 8002c40: 60f8 str r0, [r7, #12] 8002c42: 60b9 str r1, [r7, #8] 8002c44: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8002c46: 68fb ldr r3, [r7, #12] 8002c48: 6a1b ldr r3, [r3, #32] 8002c4a: f023 0210 bic.w r2, r3, #16 8002c4e: 68fb ldr r3, [r7, #12] 8002c50: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8002c52: 68fb ldr r3, [r7, #12] 8002c54: 699b ldr r3, [r3, #24] 8002c56: 617b str r3, [r7, #20] tmpccer = TIMx->CCER; 8002c58: 68fb ldr r3, [r7, #12] 8002c5a: 6a1b ldr r3, [r3, #32] 8002c5c: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8002c5e: 697b ldr r3, [r7, #20] 8002c60: f423 4370 bic.w r3, r3, #61440 ; 0xf000 8002c64: 617b str r3, [r7, #20] tmpccmr1 |= (TIM_ICFilter << 12U); 8002c66: 687b ldr r3, [r7, #4] 8002c68: 031b lsls r3, r3, #12 8002c6a: 697a ldr r2, [r7, #20] 8002c6c: 4313 orrs r3, r2 8002c6e: 617b str r3, [r7, #20] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8002c70: 693b ldr r3, [r7, #16] 8002c72: f023 03a0 bic.w r3, r3, #160 ; 0xa0 8002c76: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity << 4U); 8002c78: 68bb ldr r3, [r7, #8] 8002c7a: 011b lsls r3, r3, #4 8002c7c: 693a ldr r2, [r7, #16] 8002c7e: 4313 orrs r3, r2 8002c80: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8002c82: 68fb ldr r3, [r7, #12] 8002c84: 697a ldr r2, [r7, #20] 8002c86: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8002c88: 68fb ldr r3, [r7, #12] 8002c8a: 693a ldr r2, [r7, #16] 8002c8c: 621a str r2, [r3, #32] } 8002c8e: bf00 nop 8002c90: 371c adds r7, #28 8002c92: 46bd mov sp, r7 8002c94: f85d 7b04 ldr.w r7, [sp], #4 8002c98: 4770 bx lr 08002c9a : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8002c9a: b480 push {r7} 8002c9c: b085 sub sp, #20 8002c9e: af00 add r7, sp, #0 8002ca0: 6078 str r0, [r7, #4] 8002ca2: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8002ca4: 687b ldr r3, [r7, #4] 8002ca6: 689b ldr r3, [r3, #8] 8002ca8: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8002caa: 68fb ldr r3, [r7, #12] 8002cac: f023 0370 bic.w r3, r3, #112 ; 0x70 8002cb0: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8002cb2: 683a ldr r2, [r7, #0] 8002cb4: 68fb ldr r3, [r7, #12] 8002cb6: 4313 orrs r3, r2 8002cb8: f043 0307 orr.w r3, r3, #7 8002cbc: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8002cbe: 687b ldr r3, [r7, #4] 8002cc0: 68fa ldr r2, [r7, #12] 8002cc2: 609a str r2, [r3, #8] } 8002cc4: bf00 nop 8002cc6: 3714 adds r7, #20 8002cc8: 46bd mov sp, r7 8002cca: f85d 7b04 ldr.w r7, [sp], #4 8002cce: 4770 bx lr 08002cd0 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8002cd0: b480 push {r7} 8002cd2: b087 sub sp, #28 8002cd4: af00 add r7, sp, #0 8002cd6: 60f8 str r0, [r7, #12] 8002cd8: 60b9 str r1, [r7, #8] 8002cda: 607a str r2, [r7, #4] 8002cdc: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8002cde: 68fb ldr r3, [r7, #12] 8002ce0: 689b ldr r3, [r3, #8] 8002ce2: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8002ce4: 697b ldr r3, [r7, #20] 8002ce6: f423 437f bic.w r3, r3, #65280 ; 0xff00 8002cea: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8002cec: 683b ldr r3, [r7, #0] 8002cee: 021a lsls r2, r3, #8 8002cf0: 687b ldr r3, [r7, #4] 8002cf2: 431a orrs r2, r3 8002cf4: 68bb ldr r3, [r7, #8] 8002cf6: 4313 orrs r3, r2 8002cf8: 697a ldr r2, [r7, #20] 8002cfa: 4313 orrs r3, r2 8002cfc: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8002cfe: 68fb ldr r3, [r7, #12] 8002d00: 697a ldr r2, [r7, #20] 8002d02: 609a str r2, [r3, #8] } 8002d04: bf00 nop 8002d06: 371c adds r7, #28 8002d08: 46bd mov sp, r7 8002d0a: f85d 7b04 ldr.w r7, [sp], #4 8002d0e: 4770 bx lr 08002d10 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8002d10: b480 push {r7} 8002d12: b087 sub sp, #28 8002d14: af00 add r7, sp, #0 8002d16: 60f8 str r0, [r7, #12] 8002d18: 60b9 str r1, [r7, #8] 8002d1a: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8002d1c: 68bb ldr r3, [r7, #8] 8002d1e: f003 031f and.w r3, r3, #31 8002d22: 2201 movs r2, #1 8002d24: fa02 f303 lsl.w r3, r2, r3 8002d28: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8002d2a: 68fb ldr r3, [r7, #12] 8002d2c: 6a1a ldr r2, [r3, #32] 8002d2e: 697b ldr r3, [r7, #20] 8002d30: 43db mvns r3, r3 8002d32: 401a ands r2, r3 8002d34: 68fb ldr r3, [r7, #12] 8002d36: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8002d38: 68fb ldr r3, [r7, #12] 8002d3a: 6a1a ldr r2, [r3, #32] 8002d3c: 68bb ldr r3, [r7, #8] 8002d3e: f003 031f and.w r3, r3, #31 8002d42: 6879 ldr r1, [r7, #4] 8002d44: fa01 f303 lsl.w r3, r1, r3 8002d48: 431a orrs r2, r3 8002d4a: 68fb ldr r3, [r7, #12] 8002d4c: 621a str r2, [r3, #32] } 8002d4e: bf00 nop 8002d50: 371c adds r7, #28 8002d52: 46bd mov sp, r7 8002d54: f85d 7b04 ldr.w r7, [sp], #4 8002d58: 4770 bx lr ... 08002d5c : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { 8002d5c: b480 push {r7} 8002d5e: b085 sub sp, #20 8002d60: af00 add r7, sp, #0 8002d62: 6078 str r0, [r7, #4] 8002d64: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8002d66: 687b ldr r3, [r7, #4] 8002d68: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8002d6c: 2b01 cmp r3, #1 8002d6e: d101 bne.n 8002d74 8002d70: 2302 movs r3, #2 8002d72: e05a b.n 8002e2a 8002d74: 687b ldr r3, [r7, #4] 8002d76: 2201 movs r2, #1 8002d78: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8002d7c: 687b ldr r3, [r7, #4] 8002d7e: 2202 movs r2, #2 8002d80: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8002d84: 687b ldr r3, [r7, #4] 8002d86: 681b ldr r3, [r3, #0] 8002d88: 685b ldr r3, [r3, #4] 8002d8a: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8002d8c: 687b ldr r3, [r7, #4] 8002d8e: 681b ldr r3, [r3, #0] 8002d90: 689b ldr r3, [r3, #8] 8002d92: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8002d94: 68fb ldr r3, [r7, #12] 8002d96: f023 0370 bic.w r3, r3, #112 ; 0x70 8002d9a: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8002d9c: 683b ldr r3, [r7, #0] 8002d9e: 681b ldr r3, [r3, #0] 8002da0: 68fa ldr r2, [r7, #12] 8002da2: 4313 orrs r3, r2 8002da4: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8002da6: 687b ldr r3, [r7, #4] 8002da8: 681b ldr r3, [r3, #0] 8002daa: 68fa ldr r2, [r7, #12] 8002dac: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8002dae: 687b ldr r3, [r7, #4] 8002db0: 681b ldr r3, [r3, #0] 8002db2: 4a21 ldr r2, [pc, #132] ; (8002e38 ) 8002db4: 4293 cmp r3, r2 8002db6: d022 beq.n 8002dfe 8002db8: 687b ldr r3, [r7, #4] 8002dba: 681b ldr r3, [r3, #0] 8002dbc: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8002dc0: d01d beq.n 8002dfe 8002dc2: 687b ldr r3, [r7, #4] 8002dc4: 681b ldr r3, [r3, #0] 8002dc6: 4a1d ldr r2, [pc, #116] ; (8002e3c ) 8002dc8: 4293 cmp r3, r2 8002dca: d018 beq.n 8002dfe 8002dcc: 687b ldr r3, [r7, #4] 8002dce: 681b ldr r3, [r3, #0] 8002dd0: 4a1b ldr r2, [pc, #108] ; (8002e40 ) 8002dd2: 4293 cmp r3, r2 8002dd4: d013 beq.n 8002dfe 8002dd6: 687b ldr r3, [r7, #4] 8002dd8: 681b ldr r3, [r3, #0] 8002dda: 4a1a ldr r2, [pc, #104] ; (8002e44 ) 8002ddc: 4293 cmp r3, r2 8002dde: d00e beq.n 8002dfe 8002de0: 687b ldr r3, [r7, #4] 8002de2: 681b ldr r3, [r3, #0] 8002de4: 4a18 ldr r2, [pc, #96] ; (8002e48 ) 8002de6: 4293 cmp r3, r2 8002de8: d009 beq.n 8002dfe 8002dea: 687b ldr r3, [r7, #4] 8002dec: 681b ldr r3, [r3, #0] 8002dee: 4a17 ldr r2, [pc, #92] ; (8002e4c ) 8002df0: 4293 cmp r3, r2 8002df2: d004 beq.n 8002dfe 8002df4: 687b ldr r3, [r7, #4] 8002df6: 681b ldr r3, [r3, #0] 8002df8: 4a15 ldr r2, [pc, #84] ; (8002e50 ) 8002dfa: 4293 cmp r3, r2 8002dfc: d10c bne.n 8002e18 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8002dfe: 68bb ldr r3, [r7, #8] 8002e00: f023 0380 bic.w r3, r3, #128 ; 0x80 8002e04: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8002e06: 683b ldr r3, [r7, #0] 8002e08: 685b ldr r3, [r3, #4] 8002e0a: 68ba ldr r2, [r7, #8] 8002e0c: 4313 orrs r3, r2 8002e0e: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8002e10: 687b ldr r3, [r7, #4] 8002e12: 681b ldr r3, [r3, #0] 8002e14: 68ba ldr r2, [r7, #8] 8002e16: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8002e18: 687b ldr r3, [r7, #4] 8002e1a: 2201 movs r2, #1 8002e1c: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8002e20: 687b ldr r3, [r7, #4] 8002e22: 2200 movs r2, #0 8002e24: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8002e28: 2300 movs r3, #0 } 8002e2a: 4618 mov r0, r3 8002e2c: 3714 adds r7, #20 8002e2e: 46bd mov sp, r7 8002e30: f85d 7b04 ldr.w r7, [sp], #4 8002e34: 4770 bx lr 8002e36: bf00 nop 8002e38: 40010000 .word 0x40010000 8002e3c: 40000400 .word 0x40000400 8002e40: 40000800 .word 0x40000800 8002e44: 40000c00 .word 0x40000c00 8002e48: 40010400 .word 0x40010400 8002e4c: 40014000 .word 0x40014000 8002e50: 40001800 .word 0x40001800 08002e54 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 8002e54: b480 push {r7} 8002e56: b085 sub sp, #20 8002e58: af00 add r7, sp, #0 8002e5a: 6078 str r0, [r7, #4] 8002e5c: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 8002e5e: 2300 movs r3, #0 8002e60: 60fb str r3, [r7, #12] assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); /* Check input state */ __HAL_LOCK(htim); 8002e62: 687b ldr r3, [r7, #4] 8002e64: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8002e68: 2b01 cmp r3, #1 8002e6a: d101 bne.n 8002e70 8002e6c: 2302 movs r3, #2 8002e6e: e03d b.n 8002eec 8002e70: 687b ldr r3, [r7, #4] 8002e72: 2201 movs r2, #1 8002e74: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 8002e78: 68fb ldr r3, [r7, #12] 8002e7a: f023 02ff bic.w r2, r3, #255 ; 0xff 8002e7e: 683b ldr r3, [r7, #0] 8002e80: 68db ldr r3, [r3, #12] 8002e82: 4313 orrs r3, r2 8002e84: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 8002e86: 68fb ldr r3, [r7, #12] 8002e88: f423 7240 bic.w r2, r3, #768 ; 0x300 8002e8c: 683b ldr r3, [r7, #0] 8002e8e: 689b ldr r3, [r3, #8] 8002e90: 4313 orrs r3, r2 8002e92: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 8002e94: 68fb ldr r3, [r7, #12] 8002e96: f423 6280 bic.w r2, r3, #1024 ; 0x400 8002e9a: 683b ldr r3, [r7, #0] 8002e9c: 685b ldr r3, [r3, #4] 8002e9e: 4313 orrs r3, r2 8002ea0: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 8002ea2: 68fb ldr r3, [r7, #12] 8002ea4: f423 6200 bic.w r2, r3, #2048 ; 0x800 8002ea8: 683b ldr r3, [r7, #0] 8002eaa: 681b ldr r3, [r3, #0] 8002eac: 4313 orrs r3, r2 8002eae: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 8002eb0: 68fb ldr r3, [r7, #12] 8002eb2: f423 5280 bic.w r2, r3, #4096 ; 0x1000 8002eb6: 683b ldr r3, [r7, #0] 8002eb8: 691b ldr r3, [r3, #16] 8002eba: 4313 orrs r3, r2 8002ebc: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 8002ebe: 68fb ldr r3, [r7, #12] 8002ec0: f423 5200 bic.w r2, r3, #8192 ; 0x2000 8002ec4: 683b ldr r3, [r7, #0] 8002ec6: 695b ldr r3, [r3, #20] 8002ec8: 4313 orrs r3, r2 8002eca: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 8002ecc: 68fb ldr r3, [r7, #12] 8002ece: f423 4280 bic.w r2, r3, #16384 ; 0x4000 8002ed2: 683b ldr r3, [r7, #0] 8002ed4: 69db ldr r3, [r3, #28] 8002ed6: 4313 orrs r3, r2 8002ed8: 60fb str r3, [r7, #12] /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 8002eda: 687b ldr r3, [r7, #4] 8002edc: 681b ldr r3, [r3, #0] 8002ede: 68fa ldr r2, [r7, #12] 8002ee0: 645a str r2, [r3, #68] ; 0x44 __HAL_UNLOCK(htim); 8002ee2: 687b ldr r3, [r7, #4] 8002ee4: 2200 movs r2, #0 8002ee6: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8002eea: 2300 movs r3, #0 } 8002eec: 4618 mov r0, r3 8002eee: 3714 adds r7, #20 8002ef0: 46bd mov sp, r7 8002ef2: f85d 7b04 ldr.w r7, [sp], #4 8002ef6: 4770 bx lr 08002ef8 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8002ef8: b480 push {r7} 8002efa: b083 sub sp, #12 8002efc: af00 add r7, sp, #0 8002efe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8002f00: bf00 nop 8002f02: 370c adds r7, #12 8002f04: 46bd mov sp, r7 8002f06: f85d 7b04 ldr.w r7, [sp], #4 8002f0a: 4770 bx lr 08002f0c : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8002f0c: b480 push {r7} 8002f0e: b083 sub sp, #12 8002f10: af00 add r7, sp, #0 8002f12: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8002f14: bf00 nop 8002f16: 370c adds r7, #12 8002f18: 46bd mov sp, r7 8002f1a: f85d 7b04 ldr.w r7, [sp], #4 8002f1e: 4770 bx lr 08002f20 : 8002f20: 4402 add r2, r0 8002f22: 4603 mov r3, r0 8002f24: 4293 cmp r3, r2 8002f26: d100 bne.n 8002f2a 8002f28: 4770 bx lr 8002f2a: f803 1b01 strb.w r1, [r3], #1 8002f2e: e7f9 b.n 8002f24 08002f30 <__libc_init_array>: 8002f30: b570 push {r4, r5, r6, lr} 8002f32: 4d0d ldr r5, [pc, #52] ; (8002f68 <__libc_init_array+0x38>) 8002f34: 4c0d ldr r4, [pc, #52] ; (8002f6c <__libc_init_array+0x3c>) 8002f36: 1b64 subs r4, r4, r5 8002f38: 10a4 asrs r4, r4, #2 8002f3a: 2600 movs r6, #0 8002f3c: 42a6 cmp r6, r4 8002f3e: d109 bne.n 8002f54 <__libc_init_array+0x24> 8002f40: 4d0b ldr r5, [pc, #44] ; (8002f70 <__libc_init_array+0x40>) 8002f42: 4c0c ldr r4, [pc, #48] ; (8002f74 <__libc_init_array+0x44>) 8002f44: f000 f818 bl 8002f78 <_init> 8002f48: 1b64 subs r4, r4, r5 8002f4a: 10a4 asrs r4, r4, #2 8002f4c: 2600 movs r6, #0 8002f4e: 42a6 cmp r6, r4 8002f50: d105 bne.n 8002f5e <__libc_init_array+0x2e> 8002f52: bd70 pop {r4, r5, r6, pc} 8002f54: f855 3b04 ldr.w r3, [r5], #4 8002f58: 4798 blx r3 8002f5a: 3601 adds r6, #1 8002f5c: e7ee b.n 8002f3c <__libc_init_array+0xc> 8002f5e: f855 3b04 ldr.w r3, [r5], #4 8002f62: 4798 blx r3 8002f64: 3601 adds r6, #1 8002f66: e7f2 b.n 8002f4e <__libc_init_array+0x1e> 8002f68: 08002fa8 .word 0x08002fa8 8002f6c: 08002fa8 .word 0x08002fa8 8002f70: 08002fa8 .word 0x08002fa8 8002f74: 08002fac .word 0x08002fac 08002f78 <_init>: 8002f78: b5f8 push {r3, r4, r5, r6, r7, lr} 8002f7a: bf00 nop 8002f7c: bcf8 pop {r3, r4, r5, r6, r7} 8002f7e: bc08 pop {r3} 8002f80: 469e mov lr, r3 8002f82: 4770 bx lr 08002f84 <_fini>: 8002f84: b5f8 push {r3, r4, r5, r6, r7, lr} 8002f86: bf00 nop 8002f88: bcf8 pop {r3, r4, r5, r6, r7} 8002f8a: bc08 pop {r3} 8002f8c: 469e mov lr, r3 8002f8e: 4770 bx lr